spi_host Simulation Results

Simulation Results: spi_host

23/01/2026 17:05:23 sha: b61f0df json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
93.55 %

code
95.02 %

assert
95.21 %

func
90.42 %

block
96.82 %

line
98.69 %

branch
93.35 %

toggle
88.02 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		98.95%
V2S		100.00%
unmapped		100.00%

140/140 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	spi_host_smoke	114.000s	5670.077us	50	50	100.00
csr_hw_reset				5	5	100.00
	spi_host_csr_hw_reset	2.000s	16.911us	5	5	100.00
csr_rw				20	20	100.00
	spi_host_csr_rw	2.000s	21.541us	20	20	100.00
csr_bit_bash				5	5	100.00
	spi_host_csr_bit_bash	5.000s	234.912us	5	5	100.00
csr_aliasing				5	5	100.00
	spi_host_csr_aliasing	2.000s	20.835us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	spi_host_csr_mem_rw_with_rand_reset	2.000s	77.157us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	spi_host_csr_rw	2.000s	21.541us	20	20	100.00
	spi_host_csr_aliasing	2.000s	20.835us	5	5	100.00
mem_walk				5	5	100.00
	spi_host_mem_walk	2.000s	14.214us	5	5	100.00
mem_partial_access				5	5	100.00
	spi_host_mem_partial_access	2.000s	22.688us	5	5	100.00

1128/1140 passed

98.95 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
performance				50	50	100.00
	spi_host_performance	26.000s	138.263us	50	50	100.00
error_event_intr				150	150	100.00
	spi_host_overflow_underflow	46.000s	4738.730us	50	50	100.00
	spi_host_error_cmd	4.000s	21.596us	50	50	100.00
	spi_host_event	463.000s	150760.760us	50	50	100.00
clock_rate				48	50	96.00
	spi_host_speed	37.000s	10023.132us	48	50	96.00
speed				48	50	96.00
	spi_host_speed	37.000s	10023.132us	48	50	96.00
chip_select_timing				48	50	96.00
	spi_host_speed	37.000s	10023.132us	48	50	96.00
sw_reset				50	50	100.00
	spi_host_sw_reset	61.000s	3956.990us	50	50	100.00
passthrough_mode				50	50	100.00
	spi_host_passthrough_mode	2.000s	25.252us	50	50	100.00
cpol_cpha				48	50	96.00
	spi_host_speed	37.000s	10023.132us	48	50	96.00
full_cycle				48	50	96.00
	spi_host_speed	37.000s	10023.132us	48	50	96.00
duplex				50	50	100.00
	spi_host_smoke	114.000s	5670.077us	50	50	100.00
tx_rx_only				50	50	100.00
	spi_host_smoke	114.000s	5670.077us	50	50	100.00
stress_all				48	50	96.00
	spi_host_stress_all	202.000s	18897.134us	48	50	96.00
spien				50	50	100.00
	spi_host_spien	229.000s	28785.012us	50	50	100.00
stall				50	50	100.00
	spi_host_status_stall	772.000s	20038.972us	50	50	100.00
Idlecsbactive				50	50	100.00
	spi_host_idlecsbactive	59.000s	9078.674us	50	50	100.00
data_fifo_status				50	50	100.00
	spi_host_overflow_underflow	46.000s	4738.730us	50	50	100.00
alert_test				50	50	100.00
	spi_host_alert_test	2.000s	21.899us	50	50	100.00
intr_test				50	50	100.00
	spi_host_intr_test	2.000s	31.170us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	spi_host_tl_errors	3.000s	33.591us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	spi_host_tl_errors	3.000s	33.591us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	spi_host_csr_hw_reset	2.000s	16.911us	5	5	100.00
	spi_host_csr_rw	2.000s	21.541us	20	20	100.00
	spi_host_csr_aliasing	2.000s	20.835us	5	5	100.00
	spi_host_same_csr_outstanding	2.000s	41.435us	20	20	100.00
tl_d_partial_access				50	50	100.00
	spi_host_csr_hw_reset	2.000s	16.911us	5	5	100.00
	spi_host_csr_rw	2.000s	21.541us	20	20	100.00
	spi_host_csr_aliasing	2.000s	20.835us	5	5	100.00
	spi_host_same_csr_outstanding	2.000s	41.435us	20	20	100.00

V2S

45/45 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	spi_host_sec_cm	2.000s	70.569us	5	5	100.00
	spi_host_tl_intg_err	3.000s	106.722us	20	20	100.00
sec_cm_bus_integrity				20	20	100.00
	spi_host_tl_intg_err	3.000s	106.722us	20	20	100.00

unmapped

10/10 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				10	10	100.00
	spi_host_upper_range_clkdiv	293.000s	11556.465us	10	10	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = ns spi_host_reg_block.status.rxqd (addr=, Comparison=CompareOpEq, exp_data=, call_count=
	spi_host_speed	103213548986253096678835625534181371020087860659782049668097339756842228073646	220	UVM_FATAL @ 10078041695 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0xce5987d4, Comparison=CompareOpEq, exp_data=0x0, call_count=30 UVM_INFO @ 10078041695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	spi_host_stress_all	46459637540323348528168637269583798144951324017018349082458300067720745375573	339	UVM_FATAL @ 10114081289 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x760f5e54, Comparison=CompareOpEq, exp_data=0x0, call_count=73 UVM_INFO @ 10114081289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	spi_host_stress_all	56957875619938818829834197737707195371997332658978178397010753073108767282184	233	UVM_FATAL @ 10065684408 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x8fb2a7d4, Comparison=CompareOpEq, exp_data=0x0, call_count=45 UVM_INFO @ 10065684408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	spi_host_speed	25488041313727382552910871252249463188657071424096216678027181423602446997804	304	UVM_FATAL @ 10023132040 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0xa9a69f54, Comparison=CompareOpEq, exp_data=0x0, call_count=50 UVM_INFO @ 10023132040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---