Simulation Results: sram_ctrl

 
23/01/2026 17:05:23 sha: b61f0df json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.77 %
  • code
  • 96.15 %
  • assert
  • 95.83 %
  • func
  • 98.33 %
  • line
  • 99.11 %
  • branch
  • 98.02 %
  • cond
  • 92.90 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.08%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 105.840s 3909.733us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.000s 66.439us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.040s 57.776us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.470s 539.733us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.070s 17.699us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.400s 2175.922us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.040s 57.776us 20 20 100.00
sram_ctrl_csr_aliasing 1.070s 17.699us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 371.040s 125860.450us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 193.170s 99664.819us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1630.650s 110422.744us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 345.700s 13275.724us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 2670.740s 1914841.685us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1208.690s 85518.411us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 129.020s 127404.517us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1352.370s 23699.184us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 91.290s 1016.046us 50 50 100.00
sram_ctrl_partial_access_b2b 557.040s 41523.484us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 113.810s 5095.491us 50 50 100.00
sram_ctrl_throughput_w_partial_write 99.070s 1308.382us 50 50 100.00
sram_ctrl_throughput_w_readback 102.760s 15254.796us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1153.230s 107289.468us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 5.740s 3371.490us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 6421.950s 268798.952us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.110s 141.058us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 4.980s 177.965us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 4.980s 177.965us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.000s 66.439us 5 5 100.00
sram_ctrl_csr_rw 1.040s 57.776us 20 20 100.00
sram_ctrl_csr_aliasing 1.070s 17.699us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.150s 23.299us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.000s 66.439us 5 5 100.00
sram_ctrl_csr_rw 1.040s 57.776us 20 20 100.00
sram_ctrl_csr_aliasing 1.070s 17.699us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.150s 23.299us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 19 20 95.00
sram_ctrl_passthru_mem_tl_intg_err 51.920s 31967.021us 19 20 95.00
tl_intg_err 20 25 80.00
sram_ctrl_sec_cm 1.020s 15.975us 0 5 0.00
sram_ctrl_tl_intg_err 3.210s 213.218us 20 20 100.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 1.020s 15.975us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 3.210s 213.218us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1153.230s 107289.468us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1153.230s 107289.468us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.040s 57.776us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1352.370s 23699.184us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1352.370s 23699.184us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1352.370s 23699.184us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 129.020s 127404.517us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 44 50 88.00
sram_ctrl_mubi_enc_err 8.780s 2806.959us 44 50 88.00
sec_cm_mem_integrity 19 20 95.00
sram_ctrl_passthru_mem_tl_intg_err 51.920s 31967.021us 19 20 95.00
sec_cm_mem_readback 34 50 68.00
sram_ctrl_readback_err 9.850s 6648.742us 34 50 68.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 105.840s 3909.733us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 105.840s 3909.733us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1352.370s 23699.184us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 1.020s 15.975us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 129.020s 127404.517us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 1.020s 15.975us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.020s 15.975us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 105.840s 3909.733us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.020s 15.975us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 234.640s 2473.641us 50 50 100.00

Error Messages

   Test seed line log context
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 83606023673757044150233583580233367162121811038125256447873029637724718995527 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 3891440773 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 3891440773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 35947453160374186619553471382816202683697008247790204805097248253493727682326 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 1661232160 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 1661232160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 48415363810567809466825669281470617229984446226991219293712552550543559434150 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 670805057 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 670805057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 1526163015665625453098038573602309843638398493728765727516449306968907709044 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 3152826602 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 3152826602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 81615830216960283835761183483009699155760031713286240214819071897987938592945 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 6077468771 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 6077468771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 78940002865595663578567265547785181492273884226160247641370678964816508867643 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 685200256 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 685200256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
sram_ctrl_sec_cm 52805807595563146006377706712669787304150941837453462706810954746725332646508 100
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR @ 9249092 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 9249092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 68400709856556914237148845775609386083939070350688750381506736223392163444981 95
UVM_ERROR @ 2753459332 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x74) != exp (0x0)
UVM_INFO @ 2753459332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 73967596476348747554243487856784679698609704654881615278096808072727403016025 95
UVM_ERROR @ 2742500203 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2) != exp (0x22)
UVM_INFO @ 2742500203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 17424287302991296149812754577762014005785478476758834527622142772834388084114 95
UVM_ERROR @ 657949387 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x11) != exp (0x5b)
UVM_INFO @ 657949387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 49756853788633702053306927513176353918547253887412535020585146297403352531526 95
UVM_ERROR @ 663460878 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x56) != exp (0x60)
UVM_INFO @ 663460878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 68828301645736776151228255205374889970120289207598578316088390746619787043292 95
UVM_ERROR @ 2628387581 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2f) != exp (0x3e)
UVM_INFO @ 2628387581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 98475508188799877562499156572189370659438392483197323055823454651924433868831 95
UVM_ERROR @ 2345985186 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4f) != exp (0x4c)
UVM_INFO @ 2345985186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 102494545650313862194487053420994048080852656886597492698770135833480097535781 95
UVM_ERROR @ 2856811649 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x45) != exp (0x41)
UVM_INFO @ 2856811649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 106034646400100056232284711163751684371936627780586581412415455267664264738563 95
UVM_ERROR @ 5061073828 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x40) != exp (0x67)
UVM_INFO @ 5061073828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 39676011874558188101471416049343557113516823349505450702708881742826918631565 95
UVM_ERROR @ 3459487897 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3e) != exp (0xa)
UVM_INFO @ 3459487897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 21358235847034588104247739610844745177271439972694159277851454981681948534713 95
UVM_ERROR @ 680848189 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2a) != exp (0x25)
UVM_INFO @ 680848189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 73922344711055912122020700377944151140604948214833275234206600528318923300504 95
UVM_ERROR @ 3875553417 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1b) != exp (0x6b)
UVM_INFO @ 3875553417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 44121155807793152108793688826440802809668826635116955129604417375554445371075 95
UVM_ERROR @ 689199488 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6f) != exp (0x22)
UVM_INFO @ 689199488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 103754336156213821075132441535633711171261825619224804268858272299735507299625 95
UVM_ERROR @ 1465870770 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x59) != exp (0x26)
UVM_INFO @ 1465870770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 109132308597825145998114613315772064539620948835738308591370256904392725131392 95
UVM_ERROR @ 669553186 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x18) != exp (0x38)
UVM_INFO @ 669553186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 63319181613340290102389101756620455930122524550836174441787681869460632538862 95
UVM_ERROR @ 1119007875 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x9) != exp (0x56)
UVM_INFO @ 1119007875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 79378798943023698409210980595155287903809133032510265400169581693053751018421 95
UVM_ERROR @ 2627113054 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x49) != exp (0x5a)
UVM_INFO @ 2627113054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 88812862138495001712545122479114691590146434689327279688179391441737748942248 96
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 7336375 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 7336375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 107426036429482146382727596426507383259623395014983713406546904536436231125195 100
UVM_ERROR @ 5483324 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 5483324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 59896454763614950910703472595636056308768624104432446636268197818822966927320 100
UVM_ERROR @ 32058922 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 32058922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 45729359643230306823813409434241260864739163682634654482764467373621962989669 99
UVM_ERROR @ 15974678 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 15974678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
sram_ctrl_passthru_mem_tl_intg_err 2305177160700748372868559627989200464627930361077281494501931924175647096306 96
UVM_ERROR @ 342576762 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 342576762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---