sram_ctrl Simulation Results

Simulation Results: sram_ctrl

23/01/2026 17:05:23 sha: b61f0df json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.75 %

code
96.12 %

assert
95.79 %

func
98.33 %

line
99.07 %

branch
97.98 %

cond
92.90 %

toggle
90.66 %

FSM
100.00 %

Validation stages

V1		98.26%
V2		100.00%
V2S		93.97%
V3		100.00%

226/230 passed

98.26 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	sram_ctrl_smoke	100.960s	145.056us	50	50	100.00
csr_hw_reset				5	5	100.00
	sram_ctrl_csr_hw_reset	0.950s	94.402us	5	5	100.00
csr_rw				20	20	100.00
	sram_ctrl_csr_rw	1.020s	48.918us	20	20	100.00
csr_bit_bash				5	5	100.00
	sram_ctrl_csr_bit_bash	2.540s	630.727us	5	5	100.00
csr_aliasing				5	5	100.00
	sram_ctrl_csr_aliasing	1.150s	69.103us	5	5	100.00
csr_mem_rw_with_rand_reset				16	20	80.00
	sram_ctrl_csr_mem_rw_with_rand_reset	2.580s	39.198us	16	20	80.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	sram_ctrl_csr_rw	1.020s	48.918us	20	20	100.00
	sram_ctrl_csr_aliasing	1.150s	69.103us	5	5	100.00
mem_walk				50	50	100.00
	sram_ctrl_mem_walk	12.980s	1420.620us	50	50	100.00
mem_partial_access				50	50	100.00
	sram_ctrl_mem_partial_access	6.620s	377.938us	50	50	100.00

890/890 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
multiple_keys				50	50	100.00
	sram_ctrl_multiple_keys	1155.700s	15493.186us	50	50	100.00
stress_pipeline				50	50	100.00
	sram_ctrl_stress_pipeline	377.930s	3998.105us	50	50	100.00
bijection				50	50	100.00
	sram_ctrl_bijection	87.400s	4906.430us	50	50	100.00
access_during_key_req				50	50	100.00
	sram_ctrl_access_during_key_req	1302.470s	7726.503us	50	50	100.00
lc_escalation				50	50	100.00
	sram_ctrl_lc_escalation	17.400s	9761.321us	50	50	100.00
executable				50	50	100.00
	sram_ctrl_executable	1333.390s	89878.429us	50	50	100.00
partial_access				100	100	100.00
	sram_ctrl_partial_access	94.050s	1863.916us	50	50	100.00
	sram_ctrl_partial_access_b2b	542.250s	22420.121us	50	50	100.00
max_throughput				150	150	100.00
	sram_ctrl_max_throughput	97.900s	516.275us	50	50	100.00
	sram_ctrl_throughput_w_partial_write	97.420s	619.372us	50	50	100.00
	sram_ctrl_throughput_w_readback	116.640s	584.155us	50	50	100.00
regwen				50	50	100.00
	sram_ctrl_regwen	1465.920s	24215.767us	50	50	100.00
ram_cfg				50	50	100.00
	sram_ctrl_ram_cfg	1.200s	89.617us	50	50	100.00
stress_all				50	50	100.00
	sram_ctrl_stress_all	4295.540s	158607.916us	50	50	100.00
alert_test				50	50	100.00
	sram_ctrl_alert_test	1.060s	22.189us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	sram_ctrl_tl_errors	4.330s	490.999us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	sram_ctrl_tl_errors	4.330s	490.999us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	sram_ctrl_csr_hw_reset	0.950s	94.402us	5	5	100.00
	sram_ctrl_csr_rw	1.020s	48.918us	20	20	100.00
	sram_ctrl_csr_aliasing	1.150s	69.103us	5	5	100.00
	sram_ctrl_same_csr_outstanding	1.190s	50.070us	20	20	100.00
tl_d_partial_access				50	50	100.00
	sram_ctrl_csr_hw_reset	0.950s	94.402us	5	5	100.00
	sram_ctrl_csr_rw	1.020s	48.918us	20	20	100.00
	sram_ctrl_csr_aliasing	1.150s	69.103us	5	5	100.00
	sram_ctrl_same_csr_outstanding	1.190s	50.070us	20	20	100.00

V2S

733/780 passed

93.97 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
passthru_mem_tl_intg_err				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	3.990s	579.386us	20	20	100.00
tl_intg_err				20	25	80.00
	sram_ctrl_sec_cm	0.960s	7.152us	0	5	0.00
	sram_ctrl_tl_intg_err	3.930s	1867.695us	20	20	100.00
prim_count_check				0	5	0.00
	sram_ctrl_sec_cm	0.960s	7.152us	0	5	0.00
sec_cm_bus_integrity				20	20	100.00
	sram_ctrl_tl_intg_err	3.930s	1867.695us	20	20	100.00
sec_cm_ctrl_config_regwen				50	50	100.00
	sram_ctrl_regwen	1465.920s	24215.767us	50	50	100.00
sec_cm_readback_config_regwen				50	50	100.00
	sram_ctrl_regwen	1465.920s	24215.767us	50	50	100.00
sec_cm_exec_config_regwen				20	20	100.00
	sram_ctrl_csr_rw	1.020s	48.918us	20	20	100.00
sec_cm_exec_config_mubi				50	50	100.00
	sram_ctrl_executable	1333.390s	89878.429us	50	50	100.00
sec_cm_exec_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1333.390s	89878.429us	50	50	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1333.390s	89878.429us	50	50	100.00
sec_cm_lc_escalate_en_intersig_mubi				50	50	100.00
	sram_ctrl_lc_escalation	17.400s	9761.321us	50	50	100.00
sec_cm_prim_ram_ctrl_mubi				45	50	90.00
	sram_ctrl_mubi_enc_err	1.730s	84.408us	45	50	90.00
sec_cm_mem_integrity				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	3.990s	579.386us	20	20	100.00
sec_cm_mem_readback				38	50	76.00
	sram_ctrl_readback_err	1.690s	248.355us	38	50	76.00
sec_cm_mem_scramble				50	50	100.00
	sram_ctrl_smoke	100.960s	145.056us	50	50	100.00
sec_cm_addr_scramble				50	50	100.00
	sram_ctrl_smoke	100.960s	145.056us	50	50	100.00
sec_cm_instr_bus_lc_gated				50	50	100.00
	sram_ctrl_executable	1333.390s	89878.429us	50	50	100.00
sec_cm_ram_tl_lc_gate_fsm_sparse				0	5	0.00
	sram_ctrl_sec_cm	0.960s	7.152us	0	5	0.00
sec_cm_key_global_esc				50	50	100.00
	sram_ctrl_lc_escalation	17.400s	9761.321us	50	50	100.00
sec_cm_key_local_esc				0	5	0.00
	sram_ctrl_sec_cm	0.960s	7.152us	0	5	0.00
sec_cm_init_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	0.960s	7.152us	0	5	0.00
sec_cm_scramble_key_sideload				50	50	100.00
	sram_ctrl_smoke	100.960s	145.056us	50	50	100.00
sec_cm_tlul_fifo_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	0.960s	7.152us	0	5	0.00

50/50 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				50	50	100.00
	sram_ctrl_stress_all_with_rand_reset	906.450s	2773.569us	50	50	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act () != exp ()
	sram_ctrl_readback_err	19499045706461094667380685195245824498038566827394884394657974205780566825930	95	UVM_ERROR @ 91760077 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x70) != exp (0x45) UVM_INFO @ 91760077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	57462010324714421474141167868479610036063644231497435507349778841642109963883	95	UVM_ERROR @ 91487176 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x64) != exp (0x60) UVM_INFO @ 91487176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	38381064817232381512847475128786419461468773338731229539733678929041867660333	95	UVM_ERROR @ 187695770 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x33) != exp (0x3) UVM_INFO @ 187695770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	24453516320565306057007463540425811159017424319357632473596091440580872603727	95	UVM_ERROR @ 45965185 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x35) != exp (0x1b) UVM_INFO @ 45965185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	52496525460916560083979010653814071794027378413987762130960881715991646060371	95	UVM_ERROR @ 23290353 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x18) != exp (0x6d) UVM_INFO @ 23290353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	32290327668680724766557917731375881990700974916557535743111445217193791638921	95	UVM_ERROR @ 31058889 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x29) != exp (0x35) UVM_INFO @ 31058889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	43816405962364401234321543567924107208142774056749069363542027349853153182955	95	UVM_ERROR @ 24029330 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x65) != exp (0x69) UVM_INFO @ 24029330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	64588456593617718453184723741869889900437215206110382240571855014652101245808	95	UVM_ERROR @ 69108275 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5d) != exp (0x62) UVM_INFO @ 69108275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	5126264597665601070503098044293754061818016435492604095979814002980571182321	95	UVM_ERROR @ 434241822 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2a) != exp (0x1e) UVM_INFO @ 434241822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	19517029340956634834463854852998568706442019951472091084132110548037500657738	95	UVM_ERROR @ 104251755 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5e) != exp (0x45) UVM_INFO @ 104251755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	45543624220776666806862698090538650136766168960483107076719994052407351612985	95	UVM_ERROR @ 28095965 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6d) != exp (0x3d) UVM_INFO @ 28095965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	10930260990249134408593752313682101988665581258753730749505955591675432406111	95	UVM_ERROR @ 107809992 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3) != exp (0x15) UVM_INFO @ 107809992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.status.init_error reset value:
	sram_ctrl_sec_cm	64467897378694677133858296864915136525358460793618578694524429410067925933706	97	UVM_ERROR @ 7151962 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 7151962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	1361291620647854537728421456385358629808191974019262625884155570547548767007	97	UVM_ERROR @ 7189268 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 7189268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	82641320784150800566660118949190488844151050371669578969904541927488662760909	99	UVM_ERROR @ 4053234 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 4053234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	61101297699547992772971489011808209464138563779350336437226428885293842308801	96	UVM_ERROR @ 2090234 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 2090234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	18240418240823375315220366605212948563713763545915264073991655719550010731007	96	UVM_ERROR @ 5166376 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 5166376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
	sram_ctrl_mubi_enc_err	88476632042695511410057246351013707223374758538305872023333285472158286327761	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 256662544 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 256662544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	95733916966162880782977371066919026526549503625899345341187855066362761294877	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 40277338 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 40277338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	101797077710541907353484329229765860577228797271136836533753363030777045725040	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 24159295 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 24159295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	96419196491171152968759446691662885744702343709127452111648277567251866654989	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 96722170 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 96722170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	12632695971147697357146132083820192375531043903086588834330750090679537915152	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 50752804 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 50752804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.status.init_done reset value:
	sram_ctrl_csr_mem_rw_with_rand_reset	84013559211982896549226782048657440350903353009194942336494801690889674299343	95	UVM_ERROR @ 28617490 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0 UVM_INFO @ 28617490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.status reset value:
	sram_ctrl_csr_mem_rw_with_rand_reset	66567319738280939663528576942098668934593792469790390807950409240353132271242	95	UVM_ERROR @ 96361511 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0 UVM_INFO @ 96361511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_csr_mem_rw_with_rand_reset	95698582176676569632198733838587595210540108755510124072807327873309274649980	101	UVM_ERROR @ 178777008 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0 UVM_INFO @ 178777008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value:
	sram_ctrl_csr_mem_rw_with_rand_reset	5456824365268291995980821244003478652655860285196728721675639371535557928333	101	UVM_ERROR @ 32187990 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (5 [0x5] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9 UVM_INFO @ 32187990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---