{"block":{"name":"clkmgr","variant":null,"commit":"114d1c49baa0199187d94a8aef571ce286b15a72","commit_short":"114d1c4","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/114d1c49baa0199187d94a8aef571ce286b15a72","revision_info":"GitHub Revision: [`114d1c4`](https://github.com/lowrisc/opentitan/tree/114d1c49baa0199187d94a8aef571ce286b15a72)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-03-27T17:03:20Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"clkmgr_smoke":{"max_time":5.43,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.06,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"clkmgr_csr_rw":{"max_time":1.11,"sim_time":0.0,"passed":6,"total":20,"percent":30.0}},"passed":6,"total":20,"percent":30.0},"csr_bit_bash":{"tests":{"clkmgr_csr_bit_bash":{"max_time":6.49,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"csr_aliasing":{"tests":{"clkmgr_csr_aliasing":{"max_time":1.39,"sim_time":0.0,"passed":3,"total":5,"percent":60.0}},"passed":3,"total":5,"percent":60.0},"csr_mem_rw_with_rand_reset":{"tests":{"clkmgr_csr_mem_rw_with_rand_reset":{"max_time":1.38,"sim_time":0.0,"passed":8,"total":20,"percent":40.0}},"passed":8,"total":20,"percent":40.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"clkmgr_csr_rw":{"max_time":1.11,"sim_time":0.0,"passed":6,"total":20,"percent":30.0},"clkmgr_csr_aliasing":{"max_time":1.39,"sim_time":0.0,"passed":3,"total":5,"percent":60.0}},"passed":9,"total":25,"percent":36.0}},"passed":81,"total":130,"percent":62.30769230769231},"V2":{"testpoints":{"peri_enables":{"tests":{"clkmgr_peri":{"max_time":1.96,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"trans_enables":{"tests":{"clkmgr_trans":{"max_time":2.79,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"clk_status":{"tests":{"clkmgr_clk_status":{"max_time":1.59,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"jitter":{"tests":{"clkmgr_smoke":{"max_time":5.43,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"frequency":{"tests":{"clkmgr_frequency":{"max_time":1.21,"sim_time":0.0,"passed":1,"total":50,"percent":2.0}},"passed":1,"total":50,"percent":2.0},"frequency_timeout":{"tests":{"clkmgr_frequency_timeout":{"max_time":0.99,"sim_time":0.0,"passed":2,"total":50,"percent":4.0}},"passed":2,"total":50,"percent":4.0},"frequency_overflow":{"tests":{"clkmgr_frequency":{"max_time":1.21,"sim_time":0.0,"passed":1,"total":50,"percent":2.0}},"passed":1,"total":50,"percent":2.0},"stress_all":{"tests":{"clkmgr_stress_all":{"max_time":8.73,"sim_time":0.0,"passed":6,"total":50,"percent":12.0}},"passed":6,"total":50,"percent":12.0},"alert_test":{"tests":{"clkmgr_alert_test":{"max_time":2.03,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"clkmgr_tl_errors":{"max_time":15.81,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"clkmgr_tl_errors":{"max_time":15.81,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.06,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"clkmgr_csr_rw":{"max_time":1.11,"sim_time":0.0,"passed":6,"total":20,"percent":30.0},"clkmgr_csr_aliasing":{"max_time":1.39,"sim_time":0.0,"passed":3,"total":5,"percent":60.0},"clkmgr_same_csr_outstanding":{"max_time":1.13,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":14,"total":50,"percent":28.0},"tl_d_partial_access":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.06,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"clkmgr_csr_rw":{"max_time":1.11,"sim_time":0.0,"passed":6,"total":20,"percent":30.0},"clkmgr_csr_aliasing":{"max_time":1.39,"sim_time":0.0,"passed":3,"total":5,"percent":60.0},"clkmgr_same_csr_outstanding":{"max_time":1.13,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":14,"total":50,"percent":28.0}},"passed":328,"total":590,"percent":55.59322033898305},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"clkmgr_sec_cm":{"max_time":7.18,"sim_time":0.0,"passed":2,"total":5,"percent":40.0},"clkmgr_tl_intg_err":{"max_time":1.01,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":2,"total":25,"percent":8.0},"shadow_reg_update_error":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":5.86,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_read_clear_staged_value":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":5.86,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_storage_error":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":5.86,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadowed_reset_glitch":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":5.86,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_update_error_with_csr_rw":{"tests":{"clkmgr_shadow_reg_errors_with_csr_rw":{"max_time":1.02,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"sec_cm_bus_integrity":{"tests":{"clkmgr_tl_intg_err":{"max_time":1.01,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"sec_cm_meas_clk_bkgn_chk":{"tests":{"clkmgr_frequency":{"max_time":1.21,"sim_time":0.0,"passed":1,"total":50,"percent":2.0}},"passed":1,"total":50,"percent":2.0},"sec_cm_timeout_clk_bkgn_chk":{"tests":{"clkmgr_frequency_timeout":{"max_time":0.99,"sim_time":0.0,"passed":2,"total":50,"percent":4.0}},"passed":2,"total":50,"percent":4.0},"sec_cm_meas_config_shadow":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":5.86,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_idle_intersig_mubi":{"tests":{"clkmgr_idle_intersig_mubi":{"max_time":2.71,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_jitter_config_mubi":{"tests":{"clkmgr_csr_rw":{"max_time":1.11,"sim_time":0.0,"passed":6,"total":20,"percent":30.0}},"passed":6,"total":20,"percent":30.0},"sec_cm_idle_ctr_redun":{"tests":{"clkmgr_sec_cm":{"max_time":7.18,"sim_time":0.0,"passed":2,"total":5,"percent":40.0}},"passed":2,"total":5,"percent":40.0},"sec_cm_meas_config_regwen":{"tests":{"clkmgr_csr_rw":{"max_time":1.11,"sim_time":0.0,"passed":6,"total":20,"percent":30.0}},"passed":6,"total":20,"percent":30.0},"sec_cm_clk_ctrl_config_regwen":{"tests":{"clkmgr_csr_rw":{"max_time":1.11,"sim_time":0.0,"passed":6,"total":20,"percent":30.0}},"passed":6,"total":20,"percent":30.0},"prim_count_check":{"tests":{"clkmgr_sec_cm":{"max_time":7.18,"sim_time":0.0,"passed":2,"total":5,"percent":40.0}},"passed":2,"total":5,"percent":40.0}},"passed":177,"total":385,"percent":45.97402597402598},"V3":{"testpoints":{"regwen":{"tests":{"clkmgr_regwen":{"max_time":1.04,"sim_time":0.0,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":50,"percent":0.0},"stress_all_with_rand_reset":{"tests":{"clkmgr_stress_all_with_rand_reset":{"max_time":30.98,"sim_time":0.0,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":50,"percent":0.0}},"passed":0,"total":100,"percent":0.0}},"coverage":{"code":{"block":null,"line_statement":92.11,"branch":94.94,"condition_expression":89.6,"toggle":100.0,"fsm":62.5},"assertion":94.63,"functional":76.96},"cov_report_page":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*":[{"name":"clkmgr_frequency","qual_name":"0.clkmgr_frequency.18080937785366532122748575435324956164182385717238499663447169217967806579855","seed":18080937785366532122748575435324956164182385717238499663447169217967806579855,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  10186246 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  10186246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"0.clkmgr_stress_all.98896447597376742867181036219000020453178285890102917114305664780319580963700","seed":98896447597376742867181036219000020453178285890102917114305664780319580963700,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 107565092 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 107565092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"1.clkmgr_frequency.107077036382069885470699427619202237066107712071711689523702691831631365433874","seed":107077036382069885470699427619202237066107712071711689523702691831631365433874,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  11115626 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  11115626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"1.clkmgr_stress_all_with_rand_reset.788024910299871360412784162444410050175993717455251593954718681905221324560","seed":788024910299871360412784162444410050175993717455251593954718681905221324560,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  17708448 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  17708448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"1.clkmgr_stress_all.106796733704438171220727246891685133529400477787346015165772200106849484537394","seed":106796733704438171220727246891685133529400477787346015165772200106849484537394,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   4647242 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4647242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"2.clkmgr_frequency.115135584612934759757552910486603247608095496414469931582694715322251937188605","seed":115135584612934759757552910486603247608095496414469931582694715322251937188605,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   8701275 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   8701275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"2.clkmgr_stress_all_with_rand_reset.27230641676191335746255605022513330306803213900830181246599283111848248773853","seed":27230641676191335746255605022513330306803213900830181246599283111848248773853,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   7850659 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7850659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"2.clkmgr_stress_all.19993888502462570606835988366780330627187528492779438625611295179369006382729","seed":19993888502462570606835988366780330627187528492779438625611295179369006382729,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  33172610 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  33172610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"3.clkmgr_frequency.16808471814438046303237666260503020976969594564725480487007111341315620558826","seed":16808471814438046303237666260503020976969594564725480487007111341315620558826,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  15333835 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  15333835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"3.clkmgr_stress_all_with_rand_reset.105519420913644525020949736448612142554724441118080664780745364674963596527138","seed":105519420913644525020949736448612142554724441118080664780745364674963596527138,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  19012184 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  19012184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"4.clkmgr_stress_all.42600756777676947835500243087791499197076249783825200826610841032755890925728","seed":42600756777676947835500243087791499197076249783825200826610841032755890925728,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  33727665 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  33727665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"5.clkmgr_frequency.97182240944925573624442805559809492238544610859772748373958037563876937459813","seed":97182240944925573624442805559809492238544610859772748373958037563876937459813,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  11085692 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  11085692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"5.clkmgr_stress_all_with_rand_reset.110656429307282041103796398453205401539087242544414912180694706398045132971997","seed":110656429307282041103796398453205401539087242544414912180694706398045132971997,"line":126,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 426191704 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 426191704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"6.clkmgr_frequency.17004381152576426616676197316846239664568929712047880464076076107138443497583","seed":17004381152576426616676197316846239664568929712047880464076076107138443497583,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5487209 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5487209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"7.clkmgr_frequency.70703146108155164617050217502703123164879604472952734705369504250787828370631","seed":70703146108155164617050217502703123164879604472952734705369504250787828370631,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  20080056 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  20080056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"8.clkmgr_frequency.89905510825666099038930161598031000367314562317574411751371997812299418335073","seed":89905510825666099038930161598031000367314562317574411751371997812299418335073,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   9503704 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   9503704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"8.clkmgr_stress_all_with_rand_reset.50084669059441542150856499086943125833176803406400140299310048778294818511657","seed":50084669059441542150856499086943125833176803406400140299310048778294818511657,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  85022624 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  85022624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"8.clkmgr_stress_all.89619142134665833674233129561132557080801202748683062072689572844915076375945","seed":89619142134665833674233129561132557080801202748683062072689572844915076375945,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  24439346 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  24439346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"9.clkmgr_frequency.22862057636356786445336477925714184158535322495044199879693129331039195806273","seed":22862057636356786445336477925714184158535322495044199879693129331039195806273,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  12325997 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  12325997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"10.clkmgr_frequency.1362451961659370259693873089592807767286937792762802168945945934231463955392","seed":1362451961659370259693873089592807767286937792762802168945945934231463955392,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7682600 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7682600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"10.clkmgr_stress_all_with_rand_reset.105534152849192484108904755150282597406411627067542902585565156837097675540563","seed":105534152849192484108904755150282597406411627067542902585565156837097675540563,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   8041544 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   8041544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"10.clkmgr_stress_all.65842217197254980997373603181372733728617584288818886703430017977039864457873","seed":65842217197254980997373603181372733728617584288818886703430017977039864457873,"line":207,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 658339514 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 658339514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"11.clkmgr_frequency.104856450634250222748625645572249252882256419835977084872855982216439620331321","seed":104856450634250222748625645572249252882256419835977084872855982216439620331321,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  16766374 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  16766374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"11.clkmgr_stress_all_with_rand_reset.32022254085683236083432435933522011491499294054250184703683393836635610305583","seed":32022254085683236083432435933522011491499294054250184703683393836635610305583,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  29150986 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  29150986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"11.clkmgr_stress_all.308950252924679727450365477341461581510794680766519785959482523907435172990","seed":308950252924679727450365477341461581510794680766519785959482523907435172990,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 128955543 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 128955543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"12.clkmgr_frequency.93998773350150885238890037861267809198406600899867656534207278967471073523729","seed":93998773350150885238890037861267809198406600899867656534207278967471073523729,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7591516 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7591516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"12.clkmgr_stress_all.46631936506171864346852088165180695091556713355808558454828292996897958148299","seed":46631936506171864346852088165180695091556713355808558454828292996897958148299,"line":144,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 129488013 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 129488013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"13.clkmgr_frequency.83089536580201186652241479139282939169511463023165171397844105829065302718887","seed":83089536580201186652241479139282939169511463023165171397844105829065302718887,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4362846 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4362846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"13.clkmgr_stress_all.36472966924149382131813325997881892884621239294054760193534517644815904149356","seed":36472966924149382131813325997881892884621239294054760193534517644815904149356,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  47315068 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  47315068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"14.clkmgr_frequency.42041678002344129102094111734939381487526329121494717615011791406165118347217","seed":42041678002344129102094111734939381487526329121494717615011791406165118347217,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7415100 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7415100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"14.clkmgr_stress_all.51639631500172487527456410034502842315069637277603783124677150747614722902858","seed":51639631500172487527456410034502842315069637277603783124677150747614722902858,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   5908167 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5908167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"15.clkmgr_frequency.26413908074668778749086273894078918260418723448405385654878881644156817326919","seed":26413908074668778749086273894078918260418723448405385654878881644156817326919,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  10877939 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  10877939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"15.clkmgr_stress_all_with_rand_reset.78021826591270972898690572202089902702114937186340459643898649735378236260188","seed":78021826591270972898690572202089902702114937186340459643898649735378236260188,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   5227390 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5227390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"15.clkmgr_stress_all.87720849299097228101855097302267348355382894482372661068545652331313370914351","seed":87720849299097228101855097302267348355382894482372661068545652331313370914351,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  17541934 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  17541934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"16.clkmgr_frequency.36922811041299027604757647853581814385694289613996909161266050384024935012744","seed":36922811041299027604757647853581814385694289613996909161266050384024935012744,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   8185862 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   8185862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"16.clkmgr_stress_all_with_rand_reset.75921056666795804329281218728012072641261066947508819525019500651758227610375","seed":75921056666795804329281218728012072641261066947508819525019500651758227610375,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  60013476 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  60013476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"17.clkmgr_frequency.79805945576992164844628618066927100595334236484753394915001750889868961287877","seed":79805945576992164844628618066927100595334236484753394915001750889868961287877,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5171106 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5171106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"17.clkmgr_stress_all_with_rand_reset.113725427181906394702950504798672377138645689797429220425879146974029863992872","seed":113725427181906394702950504798672377138645689797429220425879146974029863992872,"line":244,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2916357054 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 2916357054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"17.clkmgr_stress_all.31556496523115120468137386728632212052082896936256760511292496750482124648257","seed":31556496523115120468137386728632212052082896936256760511292496750482124648257,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   5482671 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5482671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"18.clkmgr_frequency.76914762471756350925830873432482439831407758679638774174538511626489002742558","seed":76914762471756350925830873432482439831407758679638774174538511626489002742558,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7425137 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7425137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"19.clkmgr_frequency.43998384448458651905838270200590295399274948877676927962398614227532800878373","seed":43998384448458651905838270200590295399274948877676927962398614227532800878373,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4544758 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4544758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"19.clkmgr_stress_all_with_rand_reset.24171618570686367804784948255722377362578339970627355544409114073388876980488","seed":24171618570686367804784948255722377362578339970627355544409114073388876980488,"line":140,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  37000610 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  37000610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"19.clkmgr_stress_all.2639332253760361816964496043398322987470395939201717930373987491342389180454","seed":2639332253760361816964496043398322987470395939201717930373987491342389180454,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  39563612 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  39563612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"20.clkmgr_frequency.32772705597955819745544625488950849418067542824301883148473163158010135690659","seed":32772705597955819745544625488950849418067542824301883148473163158010135690659,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4465396 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4465396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"20.clkmgr_stress_all_with_rand_reset.18592222054573652665301627282470094802183183589233566334160134912530292844679","seed":18592222054573652665301627282470094802183183589233566334160134912530292844679,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   6200867 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6200867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"20.clkmgr_stress_all.68280732416377402262792026524019989624782572793210299230335577443034688321651","seed":68280732416377402262792026524019989624782572793210299230335577443034688321651,"line":92,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  62449682 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  62449682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"21.clkmgr_frequency.6403813451630585586139489931700223860650229439003512136842086791144399497841","seed":6403813451630585586139489931700223860650229439003512136842086791144399497841,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7660359 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7660359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"21.clkmgr_stress_all_with_rand_reset.91900171565030513907624900517811252102834024640395872152869350619253875723836","seed":91900171565030513907624900517811252102834024640395872152869350619253875723836,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  55701371 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  55701371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"22.clkmgr_frequency.91771748302499493692144522120607483497753943388479469185276848674253457964408","seed":91771748302499493692144522120607483497753943388479469185276848674253457964408,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  18598921 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  18598921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"23.clkmgr_frequency.110211771601353194081549810900561105536012628559832225433150233322260887400977","seed":110211771601353194081549810900561105536012628559832225433150233322260887400977,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  21277227 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  21277227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"24.clkmgr_frequency.95235404991946615463633037279379291674388603108308605042100911660691449492760","seed":95235404991946615463633037279379291674388603108308605042100911660691449492760,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5174801 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5174801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"25.clkmgr_frequency.52183249440353174511631065425152898695943755626563623515783558938399051568554","seed":52183249440353174511631065425152898695943755626563623515783558938399051568554,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5504044 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5504044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"25.clkmgr_stress_all_with_rand_reset.11845931637804761926321401099006982489106091786870898935090969276064066187811","seed":11845931637804761926321401099006982489106091786870898935090969276064066187811,"line":165,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 112049976 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 112049976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"25.clkmgr_stress_all.47181950480014650324089835308951148076699836120465149297431739334874430527176","seed":47181950480014650324089835308951148076699836120465149297431739334874430527176,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1000724388 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 1000724388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"26.clkmgr_frequency.43103951679548195855288165026901106267934548162672733876809404264078483043690","seed":43103951679548195855288165026901106267934548162672733876809404264078483043690,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5942670 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5942670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"26.clkmgr_stress_all.103121472685424552946708677661304153029263418064565962547095576365767114521075","seed":103121472685424552946708677661304153029263418064565962547095576365767114521075,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   9515874 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   9515874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"27.clkmgr_frequency.25643636417011182598798920206411751412119334886946331363918302383111986074677","seed":25643636417011182598798920206411751412119334886946331363918302383111986074677,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  13468673 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  13468673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"27.clkmgr_stress_all_with_rand_reset.60638785039520627347619805533672690475665791738007372719343634850746123470640","seed":60638785039520627347619805533672690475665791738007372719343634850746123470640,"line":153,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 173739926 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 173739926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"27.clkmgr_stress_all.111932606190936594671202419366972762877632127420357320408991766388107092601233","seed":111932606190936594671202419366972762877632127420357320408991766388107092601233,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   5532465 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5532465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"28.clkmgr_frequency.32523893519890559629406842377395997565402124675407826762086840706983656285282","seed":32523893519890559629406842377395997565402124675407826762086840706983656285282,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/28.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5541342 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5541342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"29.clkmgr_frequency.107771468552387948423294476779720028389591162158923318350534045585517921314724","seed":107771468552387948423294476779720028389591162158923318350534045585517921314724,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  14188493 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  14188493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"29.clkmgr_stress_all_with_rand_reset.25585375487148598093488958101301893909075107414756535032394200090599932345953","seed":25585375487148598093488958101301893909075107414756535032394200090599932345953,"line":137,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  47234257 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  47234257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"29.clkmgr_stress_all.114723593733112305124661761327500835953300007676628807170640452548345384653472","seed":114723593733112305124661761327500835953300007676628807170640452548345384653472,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   4723922 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4723922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"30.clkmgr_frequency.56855196200740136076754231606880278891037728170710745429951363950211774781014","seed":56855196200740136076754231606880278891037728170710745429951363950211774781014,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7173745 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7173745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"31.clkmgr_frequency.61516468154255028829519692819404423989726270526245792615616329117309747322072","seed":61516468154255028829519692819404423989726270526245792615616329117309747322072,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4995899 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4995899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"31.clkmgr_stress_all.101694642550398824667789180137781527482201895514525546572807187592773633564175","seed":101694642550398824667789180137781527482201895514525546572807187592773633564175,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 240531927 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 240531927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"32.clkmgr_frequency.58675504893712969919597322398553682036954095348604396247700928961453369410917","seed":58675504893712969919597322398553682036954095348604396247700928961453369410917,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  10421878 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  10421878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"32.clkmgr_stress_all.18713010705106446774028546273619772365100425375891963297963304779098459779718","seed":18713010705106446774028546273619772365100425375891963297963304779098459779718,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  18008605 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  18008605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"33.clkmgr_frequency.9129246260556760488100834027863969204188324892757387407476168001958807880227","seed":9129246260556760488100834027863969204188324892757387407476168001958807880227,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7223938 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7223938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"33.clkmgr_stress_all.93771328196494243788307737053142945481919797885409286856864848724943990306465","seed":93771328196494243788307737053142945481919797885409286856864848724943990306465,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  13868501 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  13868501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"34.clkmgr_frequency.64544161173632975042293053470550409693682124646911316500558623367217862302379","seed":64544161173632975042293053470550409693682124646911316500558623367217862302379,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  11172754 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  11172754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"34.clkmgr_stress_all_with_rand_reset.101350492020417430434400047253651949242728724970068904292426003297007783524214","seed":101350492020417430434400047253651949242728724970068904292426003297007783524214,"line":163,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 168281025 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 168281025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"35.clkmgr_frequency.14306214825079554189521145831172913600784864552255032477285604631009459661309","seed":14306214825079554189521145831172913600784864552255032477285604631009459661309,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5753563 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5753563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"35.clkmgr_stress_all_with_rand_reset.52186300103876618872289159480886661663370864507252926071632929446133778737709","seed":52186300103876618872289159480886661663370864507252926071632929446133778737709,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  45788690 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  45788690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"35.clkmgr_stress_all.26257977320771445123005084551864084948388246602524176412143937161485759780169","seed":26257977320771445123005084551864084948388246602524176412143937161485759780169,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  12716209 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  12716209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"36.clkmgr_frequency.5585570246308536285410074195680489505427097479080863811236406985859389354391","seed":5585570246308536285410074195680489505427097479080863811236406985859389354391,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  27902493 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  27902493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"36.clkmgr_stress_all_with_rand_reset.43916003071861725250276101764151178561064735548342931553559853447608361199832","seed":43916003071861725250276101764151178561064735548342931553559853447608361199832,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  50080284 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  50080284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"36.clkmgr_stress_all.24407705333601753126256452992835416996878511245649097268940046468443163310898","seed":24407705333601753126256452992835416996878511245649097268940046468443163310898,"line":127,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 130067214 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 130067214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"37.clkmgr_frequency.27156010459939605711707128751459531242245592165618969735836805668299588555682","seed":27156010459939605711707128751459531242245592165618969735836805668299588555682,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7650847 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7650847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"37.clkmgr_stress_all.1124519562362949163666119024265482638161789674915435055555890755180207854201","seed":1124519562362949163666119024265482638161789674915435055555890755180207854201,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   5898240 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5898240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"38.clkmgr_frequency.111367280266309264790643641440922494326174549161693207937446619399063347752251","seed":111367280266309264790643641440922494326174549161693207937446619399063347752251,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  69183214 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  69183214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"38.clkmgr_stress_all_with_rand_reset.107684074933862016804099336190737819252929149728636028320886596502743366614651","seed":107684074933862016804099336190737819252929149728636028320886596502743366614651,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   5380665 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5380665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"39.clkmgr_frequency.64998292860018898226700350290949797813636812793462294949665217644034203030459","seed":64998292860018898226700350290949797813636812793462294949665217644034203030459,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  12541639 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  12541639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"39.clkmgr_stress_all_with_rand_reset.58346098885823132204457799486930411272445776901097989096371981184595932120391","seed":58346098885823132204457799486930411272445776901097989096371981184595932120391,"line":227,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 356732781 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 356732781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"40.clkmgr_frequency.25826811742472708466488760839479431345412558630597732022825488070072432352478","seed":25826811742472708466488760839479431345412558630597732022825488070072432352478,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5184190 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5184190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"41.clkmgr_frequency.11219867640095183045885857741546094980682182614013157149074789941154657550840","seed":11219867640095183045885857741546094980682182614013157149074789941154657550840,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6564705 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6564705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"41.clkmgr_stress_all_with_rand_reset.110607017214380627470928404265268714269343874539558044074421788087662858312342","seed":110607017214380627470928404265268714269343874539558044074421788087662858312342,"line":123,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  30264456 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  30264456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"42.clkmgr_frequency.27913793656906341342944530879244107015129844655334480168535698846511171195004","seed":27913793656906341342944530879244107015129844655334480168535698846511171195004,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6218286 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6218286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"42.clkmgr_stress_all.25792187004930242830947698302419634730009997746474627947292064344041184028857","seed":25792187004930242830947698302419634730009997746474627947292064344041184028857,"line":144,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  85626121 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  85626121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"43.clkmgr_frequency.58152539156607141260983419444014438380315753601449617360928740126043192949191","seed":58152539156607141260983419444014438380315753601449617360928740126043192949191,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   8947660 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8947660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"43.clkmgr_stress_all_with_rand_reset.92694658320208767864160835675581767880351686071211463448927053293604221547093","seed":92694658320208767864160835675581767880351686071211463448927053293604221547093,"line":97,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 227436792 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 227436792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"44.clkmgr_frequency.91418929637479671864729042767197306351448471320757214700899052176368113501113","seed":91418929637479671864729042767197306351448471320757214700899052176368113501113,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5850585 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5850585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"44.clkmgr_stress_all_with_rand_reset.85998067461841783103819683404718747397298758042359120349484329991315864961482","seed":85998067461841783103819683404718747397298758042359120349484329991315864961482,"line":114,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  80939924 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  80939924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"45.clkmgr_frequency.35551143100000839767406047259396246618717665312012210961527770445425711368599","seed":35551143100000839767406047259396246618717665312012210961527770445425711368599,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4506806 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4506806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"46.clkmgr_frequency.43283286271835635040018942277826024533261458396468951234245021942776648523727","seed":43283286271835635040018942277826024533261458396468951234245021942776648523727,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  11448990 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  11448990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"47.clkmgr_frequency.89777248446682467345139173551770058830674678383121294889352378165455691443986","seed":89777248446682467345139173551770058830674678383121294889352378165455691443986,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4545866 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4545866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"47.clkmgr_stress_all_with_rand_reset.70068569422782666885398423008799866749648999114973698706817277891728354120971","seed":70068569422782666885398423008799866749648999114973698706817277891728354120971,"line":146,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  51191060 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  51191060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"47.clkmgr_stress_all.60399730733344578337779146599609953452813068448255632285055221865479695444212","seed":60399730733344578337779146599609953452813068448255632285055221865479695444212,"line":96,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 212359386 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 212359386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"48.clkmgr_frequency.16186146873637473123288718877331293101280768107652987201164485802442176103788","seed":16186146873637473123288718877331293101280768107652987201164485802442176103788,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  21392930 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  21392930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"48.clkmgr_stress_all_with_rand_reset.63820614952648069501407149120759103677084722766608058153024469593443087979734","seed":63820614952648069501407149120759103677084722766608058153024469593443087979734,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  29684153 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  29684153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"49.clkmgr_frequency.16370719775982612372618183007896003485476869166319199966850886859394040648738","seed":16370719775982612372618183007896003485476869166319199966850886859394040648738,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  14425639 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  14425639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"49.clkmgr_stress_all_with_rand_reset.49813678755731063304909361633643650838201238443779853389122271617448377806647","seed":49813678755731063304909361633643650838201238443779853389122271617448377806647,"line":90,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 100150264 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 100150264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*":[{"name":"clkmgr_frequency_timeout","qual_name":"0.clkmgr_frequency_timeout.92932884277116035194773492810319807982555458959006496604284199220673493533442","seed":92932884277116035194773492810319807982555458959006496604284199220673493533442,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2714546 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2714546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"0.clkmgr_stress_all_with_rand_reset.107134202257283109027360327047236611334247716700516983698907370424254357036648","seed":107134202257283109027360327047236611334247716700516983698907370424254357036648,"line":92,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  68631786 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  68631786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"1.clkmgr_frequency_timeout.48176975170773602936819151037519656307601330559324074055837085376881037534864","seed":48176975170773602936819151037519656307601330559324074055837085376881037534864,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2097917 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2097917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"2.clkmgr_frequency_timeout.110836630406296316536076609860902893362180078745239352979357759266702516074820","seed":110836630406296316536076609860902893362180078745239352979357759266702516074820,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3281987 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3281987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"3.clkmgr_frequency_timeout.106219821311851502930532214383616850270588181869935742876537949413296175896537","seed":106219821311851502930532214383616850270588181869935742876537949413296175896537,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5242945 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5242945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"3.clkmgr_stress_all.87711986042518716256998166358334874083608190563025239183122689270196688266960","seed":87711986042518716256998166358334874083608190563025239183122689270196688266960,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 114607508 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 114607508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"4.clkmgr_frequency_timeout.91319867011837319205026129770511649124097081632453147015900162340335104439487","seed":91319867011837319205026129770511649124097081632453147015900162340335104439487,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2546211 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2546211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"4.clkmgr_stress_all_with_rand_reset.2288181857444519015261648298822583658115945607308404261817736358520919639915","seed":2288181857444519015261648298822583658115945607308404261817736358520919639915,"line":99,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  35239227 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  35239227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"5.clkmgr_frequency_timeout.27711329632479016166058229592836506350133391648803278939947062964631185367882","seed":27711329632479016166058229592836506350133391648803278939947062964631185367882,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3019139 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3019139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"6.clkmgr_frequency_timeout.40877047346333423970256155049128552156648773281653347245101447095015846666520","seed":40877047346333423970256155049128552156648773281653347245101447095015846666520,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5272974 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5272974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"6.clkmgr_stress_all_with_rand_reset.36748721993079173152996400568834906870258287764244517234570716894909795341887","seed":36748721993079173152996400568834906870258287764244517234570716894909795341887,"line":131,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  45955310 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  45955310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"7.clkmgr_frequency_timeout.16551676851563514813398098937703040184207431225509688338533435975308575503762","seed":16551676851563514813398098937703040184207431225509688338533435975308575503762,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3279922 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3279922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"7.clkmgr_stress_all_with_rand_reset.47669240302201565763927481749359556532557662955205377436478310294596248174970","seed":47669240302201565763927481749359556532557662955205377436478310294596248174970,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   6625892 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6625892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"8.clkmgr_frequency_timeout.82796044310244723382837752022039308979434918228316278155851648562438596288987","seed":82796044310244723382837752022039308979434918228316278155851648562438596288987,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4216036 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4216036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"9.clkmgr_frequency_timeout.86475917816612682031832944016567040218852719610083109091217712951088260965781","seed":86475917816612682031832944016567040218852719610083109091217712951088260965781,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4991481 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4991481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"9.clkmgr_stress_all_with_rand_reset.63415072765648906954404044402729973548651113725157476908567456967775402785113","seed":63415072765648906954404044402729973548651113725157476908567456967775402785113,"line":124,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1806434778 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 1806434778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"9.clkmgr_stress_all.28390134598219674775427205254863857628793648804224551485907609924248468483512","seed":28390134598219674775427205254863857628793648804224551485907609924248468483512,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   6507500 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6507500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"10.clkmgr_frequency_timeout.46762088148514150876491268576437353768589101072655668879261469259032295081318","seed":46762088148514150876491268576437353768589101072655668879261469259032295081318,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5480274 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5480274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"11.clkmgr_frequency_timeout.89608203809490355993241869924135554219945536410502008887028122664823694784506","seed":89608203809490355993241869924135554219945536410502008887028122664823694784506,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   8330756 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8330756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"12.clkmgr_frequency_timeout.55058709435311510586108040906343360435761943839279129883790127766007535807762","seed":55058709435311510586108040906343360435761943839279129883790127766007535807762,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6233863 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6233863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"12.clkmgr_stress_all_with_rand_reset.38205595531538846539349938368406657117412622946831761257447211305516814977052","seed":38205595531538846539349938368406657117412622946831761257447211305516814977052,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   6265018 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6265018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"13.clkmgr_frequency_timeout.81892557867590697580281219146932192497469851505082368438300436672638418832292","seed":81892557867590697580281219146932192497469851505082368438300436672638418832292,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2539608 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2539608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"13.clkmgr_stress_all_with_rand_reset.86201254185257243465256151087319297443878545253218238362474731658427416225731","seed":86201254185257243465256151087319297443878545253218238362474731658427416225731,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 212742072 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 212742072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"14.clkmgr_frequency_timeout.44057808651082556167937686303625911926305619186588886586141880355937842399211","seed":44057808651082556167937686303625911926305619186588886586141880355937842399211,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3417945 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3417945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"14.clkmgr_stress_all_with_rand_reset.55361969710662502003325070810558988541829586759330224320335187147032510750942","seed":55361969710662502003325070810558988541829586759330224320335187147032510750942,"line":121,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  50454817 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  50454817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"15.clkmgr_frequency_timeout.53131811943542979321466035305381968414484463569149405120288789355110713088429","seed":53131811943542979321466035305381968414484463569149405120288789355110713088429,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4131732 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4131732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"16.clkmgr_frequency_timeout.25619478738975111094170184319573614174080053255549299089850701089461991033615","seed":25619478738975111094170184319573614174080053255549299089850701089461991033615,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6592665 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6592665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"16.clkmgr_stress_all.16109670203448726945045922509390890653667478327685668239530871344807684853463","seed":16109670203448726945045922509390890653667478327685668239530871344807684853463,"line":117,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  76467621 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  76467621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"17.clkmgr_frequency_timeout.46750249946664302518092110154069663605887803863672296234905616605520041307657","seed":46750249946664302518092110154069663605887803863672296234905616605520041307657,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3861869 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3861869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"18.clkmgr_frequency_timeout.41571500898579066931825910401025310596798345698216049515876276399050426292498","seed":41571500898579066931825910401025310596798345698216049515876276399050426292498,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5213003 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5213003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"18.clkmgr_stress_all_with_rand_reset.34501059452389049077964824729384928087745890196590142422252868431331203121039","seed":34501059452389049077964824729384928087745890196590142422252868431331203121039,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 115030729 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 115030729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"19.clkmgr_frequency_timeout.73025209365884809548522152390381684499985527692843883490378070939027518780526","seed":73025209365884809548522152390381684499985527692843883490378070939027518780526,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5138728 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5138728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"20.clkmgr_frequency_timeout.78158977423127023365698143430774757795246372908243723703350194932232747335423","seed":78158977423127023365698143430774757795246372908243723703350194932232747335423,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @  12376628 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  12376628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"21.clkmgr_frequency_timeout.89153806601183209708450986433802624167188025658394499071160509209372540279090","seed":89153806601183209708450986433802624167188025658394499071160509209372540279090,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2846041 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2846041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"21.clkmgr_stress_all.41451590663962063264290267517119290454122033869118306990798126089923690918596","seed":41451590663962063264290267517119290454122033869118306990798126089923690918596,"line":150,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 395594120 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 395594120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"22.clkmgr_frequency_timeout.82018702307921469689747876960963183691844674893427788328030421106730490051108","seed":82018702307921469689747876960963183691844674893427788328030421106730490051108,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2394292 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2394292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"22.clkmgr_stress_all_with_rand_reset.10799787029103902596922635300544138739484826078423395967814167855202528234176","seed":10799787029103902596922635300544138739484826078423395967814167855202528234176,"line":86,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  34501068 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  34501068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"22.clkmgr_stress_all.87814644252821316241536757392712561572283343661082795848586913617789624636151","seed":87814644252821316241536757392712561572283343661082795848586913617789624636151,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   5686234 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5686234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"23.clkmgr_frequency_timeout.2680998372675915416226542924104122951251113381090920859814000451747254838239","seed":2680998372675915416226542924104122951251113381090920859814000451747254838239,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2975798 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2975798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"23.clkmgr_stress_all_with_rand_reset.46692217661807096304706467799220902271002716521660765273296120459703912979910","seed":46692217661807096304706467799220902271002716521660765273296120459703912979910,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  17164877 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  17164877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"23.clkmgr_stress_all.72200084718133845142466954235299227662179071863292517808680201737631503796959","seed":72200084718133845142466954235299227662179071863292517808680201737631503796959,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  18204653 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  18204653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"24.clkmgr_frequency_timeout.92913896597674640864946459786261195462964254968449354435691249021925913472022","seed":92913896597674640864946459786261195462964254968449354435691249021925913472022,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6637933 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6637933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"24.clkmgr_stress_all_with_rand_reset.112213242108154474376227822930829100732301948267810809608520359037682307569816","seed":112213242108154474376227822930829100732301948267810809608520359037682307569816,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   3320652 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3320652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"24.clkmgr_stress_all.2247298062602331180981461166051310284920925695041153935862854495009627845123","seed":2247298062602331180981461166051310284920925695041153935862854495009627845123,"line":145,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 282001124 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 282001124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"25.clkmgr_frequency_timeout.15555126609556649701833097953054755299441451116114383855091496232700655889901","seed":15555126609556649701833097953054755299441451116114383855091496232700655889901,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2535670 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2535670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"26.clkmgr_frequency_timeout.113648795545600088375084743395755663057910638964647171401693555564290155188632","seed":113648795545600088375084743395755663057910638964647171401693555564290155188632,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6102649 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6102649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"26.clkmgr_stress_all_with_rand_reset.35071893886214279507369995334335823161476947849269160610174136035037704248402","seed":35071893886214279507369995334335823161476947849269160610174136035037704248402,"line":145,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  85127038 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  85127038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"27.clkmgr_frequency_timeout.77269968318795932233397542675285454145608301286590678479179304501512173114500","seed":77269968318795932233397542675285454145608301286590678479179304501512173114500,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3250612 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3250612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"28.clkmgr_frequency_timeout.73426802811899305915884865029008015298082404801057038435483745881936705818694","seed":73426802811899305915884865029008015298082404801057038435483745881936705818694,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/28.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3708285 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3708285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"28.clkmgr_stress_all_with_rand_reset.19055146984049886669661679653920775796145239886149239283537471175793101412767","seed":19055146984049886669661679653920775796145239886149239283537471175793101412767,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/28.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   7432417 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7432417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"29.clkmgr_frequency_timeout.110323845523881546677648244144883888358453864965654722017833014260126062853788","seed":110323845523881546677648244144883888358453864965654722017833014260126062853788,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   1552805 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   1552805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"30.clkmgr_stress_all_with_rand_reset.17982456397664056898887820640868628371949327468130730320541192935610716885018","seed":17982456397664056898887820640868628371949327468130730320541192935610716885018,"line":179,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 978777743 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 978777743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"30.clkmgr_stress_all.32393054526983069467349725241387721918393584800266910881242884799477222775253","seed":32393054526983069467349725241387721918393584800266910881242884799477222775253,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   6136141 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6136141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"31.clkmgr_frequency_timeout.111775002407600838932480556771999512731154935956226305877012060575509511600580","seed":111775002407600838932480556771999512731154935956226305877012060575509511600580,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3628950 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3628950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"31.clkmgr_stress_all_with_rand_reset.49402066039767596115213493518795550035088054714561893848871727539892155845851","seed":49402066039767596115213493518795550035088054714561893848871727539892155845851,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  12286281 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  12286281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"32.clkmgr_frequency_timeout.50184465321841951655910758768296361711848476120109540380026606486164008203255","seed":50184465321841951655910758768296361711848476120109540380026606486164008203255,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   8748787 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   8748787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"32.clkmgr_stress_all_with_rand_reset.69082384978649233998223517055600494122462947799909837241341822183112722187075","seed":69082384978649233998223517055600494122462947799909837241341822183112722187075,"line":85,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  55953666 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  55953666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"33.clkmgr_stress_all_with_rand_reset.30464428423792502319969180005000603049476703647029341754609839829712973369883","seed":30464428423792502319969180005000603049476703647029341754609839829712973369883,"line":119,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 149713760 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 149713760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"34.clkmgr_frequency_timeout.59344440083277821113187410478271795233504416398893990508502617032099538621224","seed":59344440083277821113187410478271795233504416398893990508502617032099538621224,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5117443 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5117443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"34.clkmgr_stress_all.79879019096522392850410595184107155843327608527868774723314867209849494398221","seed":79879019096522392850410595184107155843327608527868774723314867209849494398221,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   4525222 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4525222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"35.clkmgr_frequency_timeout.21234203354733481037966872767961764822102644866310629444176371092313566938037","seed":21234203354733481037966872767961764822102644866310629444176371092313566938037,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6024419 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6024419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"36.clkmgr_frequency_timeout.36012331049064484088550822643294066299426460868100350569961082765699631157825","seed":36012331049064484088550822643294066299426460868100350569961082765699631157825,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3421371 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3421371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"37.clkmgr_frequency_timeout.3488916570739817724421972922135685086936204322807340160085548769630081054329","seed":3488916570739817724421972922135685086936204322807340160085548769630081054329,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6829779 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6829779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"37.clkmgr_stress_all_with_rand_reset.19874917070457459874993920318785998111984302455485684825219662247664889070315","seed":19874917070457459874993920318785998111984302455485684825219662247664889070315,"line":185,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  42999916 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  42999916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"38.clkmgr_frequency_timeout.85957636450563577355406824365427350552622886792724045064064478792186005272371","seed":85957636450563577355406824365427350552622886792724045064064478792186005272371,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5366781 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5366781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"38.clkmgr_stress_all.2610871077785256299145688415953281297104301151285546546985222190926941681921","seed":2610871077785256299145688415953281297104301151285546546985222190926941681921,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  12938928 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  12938928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"39.clkmgr_frequency_timeout.115428147872131017838618414171743070350573646877941451141676315400101174840817","seed":115428147872131017838618414171743070350573646877941451141676315400101174840817,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5461267 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5461267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"39.clkmgr_stress_all.46578433786054441742893654235258696952829509352962699791165206229215991778431","seed":46578433786054441742893654235258696952829509352962699791165206229215991778431,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  19520447 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  19520447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"40.clkmgr_frequency_timeout.96647776181105486902054053050645003342184871627139533135788164856862246522241","seed":96647776181105486902054053050645003342184871627139533135788164856862246522241,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2497882 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2497882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"40.clkmgr_stress_all_with_rand_reset.25479053124837689626309140818399069785542954677193389738836054585842337766457","seed":25479053124837689626309140818399069785542954677193389738836054585842337766457,"line":124,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 139916277 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 139916277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"40.clkmgr_stress_all.109600349325559904656227972531718872513723771909940776310215610975819207504509","seed":109600349325559904656227972531718872513723771909940776310215610975819207504509,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   6212794 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6212794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"41.clkmgr_frequency_timeout.14546844612639113624781621258948449809064452262253274319007856357904034303899","seed":14546844612639113624781621258948449809064452262253274319007856357904034303899,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   7576299 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7576299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"41.clkmgr_stress_all.81644736229646754458996500623222243924337217233694499954566045835081430048290","seed":81644736229646754458996500623222243924337217233694499954566045835081430048290,"line":122,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 153534704 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 153534704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"42.clkmgr_frequency_timeout.41660390825345843760889455253099344834093074595433733139767989416281436750639","seed":41660390825345843760889455253099344834093074595433733139767989416281436750639,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5884437 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5884437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"42.clkmgr_stress_all_with_rand_reset.70272231180459127397880247658703211683232261711934203612971009267480324561260","seed":70272231180459127397880247658703211683232261711934203612971009267480324561260,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   2608819 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2608819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"43.clkmgr_frequency_timeout.109521001485880817092092149145288000648925845060646999490810084329792529182938","seed":109521001485880817092092149145288000648925845060646999490810084329792529182938,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5279715 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5279715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"43.clkmgr_stress_all.995063299461518077469808353848061746936765988178275496618029575178088726012","seed":995063299461518077469808353848061746936765988178275496618029575178088726012,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   6391629 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6391629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"44.clkmgr_frequency_timeout.107133857638407682316872233054987367069895577888644538062185417355339729601819","seed":107133857638407682316872233054987367069895577888644538062185417355339729601819,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5863484 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5863484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"44.clkmgr_stress_all.10445896396225502090087747031900014575869348442577887617374351174399790888493","seed":10445896396225502090087747031900014575869348442577887617374351174399790888493,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   5034457 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5034457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"45.clkmgr_frequency_timeout.32231137901508215183060495477056859084635922696210703043321587500913308005470","seed":32231137901508215183060495477056859084635922696210703043321587500913308005470,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4094242 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4094242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"45.clkmgr_stress_all_with_rand_reset.50287449635274553796532332034006010736552943790343913836147388723199372121543","seed":50287449635274553796532332034006010736552943790343913836147388723199372121543,"line":91,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 110709616 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 110709616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"45.clkmgr_stress_all.32933563025515809693230753765947465681439006912113317403771476270895728758204","seed":32933563025515809693230753765947465681439006912113317403771476270895728758204,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  15084259 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  15084259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"46.clkmgr_frequency_timeout.15511355280367395074334275716355818534619299211768038846860711494455433200807","seed":15511355280367395074334275716355818534619299211768038846860711494455433200807,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   7599109 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7599109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"46.clkmgr_stress_all_with_rand_reset.47514088454811986648460875128353056747920830502659209471264467621681245945577","seed":47514088454811986648460875128353056747920830502659209471264467621681245945577,"line":151,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  63008439 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  63008439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"46.clkmgr_stress_all.77965891192817147155574064311131262048970577847731136996456550670460758262521","seed":77965891192817147155574064311131262048970577847731136996456550670460758262521,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   3373847 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3373847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"47.clkmgr_frequency_timeout.31512029040799912039287078545256798034784634603059317652456525727588919196918","seed":31512029040799912039287078545256798034784634603059317652456525727588919196918,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @  12583104 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  12583104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"48.clkmgr_frequency_timeout.16062758490610984812113850766352951300517546781745064425835504544779981276778","seed":16062758490610984812113850766352951300517546781745064425835504544779981276778,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4666357 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4666357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"48.clkmgr_stress_all.39083727721392290836868857120234267201253295887857505463310010442178114862330","seed":39083727721392290836868857120234267201253295887857505463310010442178114862330,"line":122,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 127819474 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 127819474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"49.clkmgr_frequency_timeout.38988077622381463040394760023833641157888733881193433994760606833086855414716","seed":38988077622381463040394760023833641157888733881193433994760606833086855414716,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   9890414 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   9890414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en":[{"name":"clkmgr_regwen","qual_name":"0.clkmgr_regwen.89485608773363027296911082824635858333100432873950301046165717818961131524844","seed":89485608773363027296911082824635858333100432873950301046165717818961131524844,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   7402915 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 14 [0xe]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   7402915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"3.clkmgr_regwen.22998502740053596566802127484867471666392040412404794262073511113530023937110","seed":22998502740053596566802127484867471666392040412404794262073511113530023937110,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3983719 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 10 [0xa]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3983719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"9.clkmgr_regwen.36754530683751628104321727948552004560080677039179531823605829364098397530496","seed":36754530683751628104321727948552004560080677039179531823605829364098397530496,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4208808 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   4208808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"11.clkmgr_regwen.110298984761451388226007629123583972417488719117002913729600728479441439596070","seed":110298984761451388226007629123583972417488719117002913729600728479441439596070,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   9219057 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 3 [0x3]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   9219057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"14.clkmgr_regwen.83379810987451340703566278481268233083752179678286599591982091268537876639862","seed":83379810987451340703566278481268233083752179678286599591982091268537876639862,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   1631260 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 5 [0x5]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   1631260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"18.clkmgr_regwen.7596029007680818306827996696266526744908039594174630673200820542097840748501","seed":7596029007680818306827996696266526744908039594174630673200820542097840748501,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5638931 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (11 [0xb] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   5638931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"20.clkmgr_regwen.97166444639698524567645755008805913363419802117037222834200534540163398755142","seed":97166444639698524567645755008805913363419802117037222834200534540163398755142,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5320640 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 4 [0x4]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   5320640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"22.clkmgr_regwen.49056016337996163228214961662345471563823818864800883135480140924738225752207","seed":49056016337996163228214961662345471563823818864800883135480140924738225752207,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2883678 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 13 [0xd]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2883678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"23.clkmgr_regwen.70155070517596770655565203945012673624636851311220436870552937311728604457708","seed":70155070517596770655565203945012673624636851311220436870552937311728604457708,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  11903600 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 11 [0xb]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @  11903600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"24.clkmgr_regwen.48361589285172535597520420689789215405727908516342367382067034002230334244756","seed":48361589285172535597520420689789215405727908516342367382067034002230334244756,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  13325573 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @  13325573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"25.clkmgr_regwen.67767382092951420968631424672337014941078850902251481391954973538982754343547","seed":67767382092951420968631424672337014941078850902251481391954973538982754343547,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5147099 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 0 [0x0]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   5147099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"26.clkmgr_regwen.54255636187511757756628936346617694332571800975240951629168212943039251766377","seed":54255636187511757756628936346617694332571800975240951629168212943039251766377,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3194099 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 11 [0xb]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3194099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"27.clkmgr_regwen.93242393658400135261572588975024083346367008284829739696034476266566130002648","seed":93242393658400135261572588975024083346367008284829739696034476266566130002648,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4632078 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 8 [0x8]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   4632078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"29.clkmgr_regwen.105513936793766875103136974379094611374860694282644414186819323219251382537632","seed":105513936793766875103136974379094611374860694282644414186819323219251382537632,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  10644333 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @  10644333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"30.clkmgr_regwen.34714397163833557680720473714780260999447067204347174984480787977032678779410","seed":34714397163833557680720473714780260999447067204347174984480787977032678779410,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6437183 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   6437183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"34.clkmgr_regwen.21260779272920945651760051376580921002881136736031807281294808834055187134100","seed":21260779272920945651760051376580921002881136736031807281294808834055187134100,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  11401020 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @  11401020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"35.clkmgr_regwen.72466173140981376579591867870777607040866879299898322745511558705452484070871","seed":72466173140981376579591867870777607040866879299898322745511558705452484070871,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   1553063 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 5 [0x5]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   1553063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"36.clkmgr_regwen.92314029203677059178793580374225179506744033263619161608172195671699974933105","seed":92314029203677059178793580374225179506744033263619161608172195671699974933105,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  28201518 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @  28201518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"38.clkmgr_regwen.15431482229985190281015142745979444848229967494606739055403117519123534833413","seed":15431482229985190281015142745979444848229967494606739055403117519123534833413,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3876992 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 13 [0xd]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3876992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"40.clkmgr_regwen.8406184863734482885714565493400872765262823267398567066251711016329567476099","seed":8406184863734482885714565493400872765262823267398567066251711016329567476099,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   1776452 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 0 [0x0]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   1776452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"41.clkmgr_regwen.75910282326841529985837959237717274887388697774579306113762986252234610284057","seed":75910282326841529985837959237717274887388697774579306113762986252234610284057,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4178096 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   4178096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"42.clkmgr_regwen.89662929431720420459634908293918832619969933044337636463423537994778335306543","seed":89662929431720420459634908293918832619969933044337636463423537994778335306543,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3175713 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 5 [0x5]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3175713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"43.clkmgr_regwen.805131346187908830818334443528275652097791588980342055969972421624611527983","seed":805131346187908830818334443528275652097791588980342055969972421624611527983,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3872818 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3872818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"44.clkmgr_regwen.109140861429055490537407075739332644818067219665149095565226304732044163897067","seed":109140861429055490537407075739332644818067219665149095565226304732044163897067,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  15432962 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @  15432962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"45.clkmgr_regwen.8036787104417211462416742358839610679381811526538576228429274398944219542728","seed":8036787104417211462416742358839610679381811526538576228429274398944219542728,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3316849 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3316849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"46.clkmgr_regwen.58397266398392737207244682952358807412224432047547970713908896432629434946624","seed":58397266398392737207244682952358807412224432047547970713908896432629434946624,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2341055 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 11 [0xb]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2341055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"47.clkmgr_regwen.57540632520940406971390881352807383427976217947073471664115797877049399243692","seed":57540632520940406971390881352807383427976217947073471664115797877049399243692,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  14840811 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 13 [0xd]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @  14840811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.main_meas_ctrl_en":[{"name":"clkmgr_regwen","qual_name":"1.clkmgr_regwen.82198804538617550986188064961084392660414229525874594089870150364349178651802","seed":82198804538617550986188064961084392660414229525874594089870150364349178651802,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  15521581 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @  15521581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"32.clkmgr_regwen.114093174790309567008595293340134560552060709182421819354421946369528504983755","seed":114093174790309567008595293340134560552060709182421819354421946369528504983755,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  14391454 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (7 [0x7] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @  14391454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"49.clkmgr_regwen.18436637696796596241867382287594863161676429003754395337499569280067050469136","seed":18436637696796596241867382287594863161676429003754395337499569280067050469136,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3164358 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @   3164358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire":[{"name":"clkmgr_sec_cm","qual_name":"1.clkmgr_sec_cm.36194223964229374016662972523651587313057240685733232069091314643827308569729","seed":36194223964229374016662972523651587313057240685733232069091314643827308569729,"line":110,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_sec_cm/latest/run.log","log_context":["UVM_ERROR @  52975183 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire\n","UVM_INFO @  52975183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_sec_cm","qual_name":"2.clkmgr_sec_cm.71680308443557636591606950599248132501966024505099836983178601652329484399253","seed":71680308443557636591606950599248132501966024505099836983178601652329484399253,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_sec_cm/latest/run.log","log_context":["UVM_ERROR @   4157843 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire\n","UVM_INFO @   4157843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_sec_cm","qual_name":"4.clkmgr_sec_cm.67933496998458187219244802804811998858228932782205675739910009504919281926792","seed":67933496998458187219244802804811998858228932782205675739910009504919281926792,"line":259,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_sec_cm/latest/run.log","log_context":["UVM_ERROR @ 429283560 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire\n","UVM_INFO @ 429283560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed":[{"name":"clkmgr_regwen","qual_name":"2.clkmgr_regwen.107489836437231578887089759015254356856689468113380349285454723849267230005366","seed":107489836437231578887089759015254356856689468113380349285454723849267230005366,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3449804 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   3449804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"4.clkmgr_regwen.39482883480950499899403898988295920093249160440214000803359261346107541421396","seed":39482883480950499899403898988295920093249160440214000803359261346107541421396,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   7051141 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   7051141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"5.clkmgr_regwen.29550391797572733948134783161732526856711932174097241925491009233198314774101","seed":29550391797572733948134783161732526856711932174097241925491009233198314774101,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   7688827 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   7688827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"6.clkmgr_regwen.63827399872017310546201616254236729674253965239510729046748252688252742126882","seed":63827399872017310546201616254236729674253965239510729046748252688252742126882,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3095442 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   3095442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"7.clkmgr_regwen.50744525273457061820225261522669665725399092057381501851855961629332200251877","seed":50744525273457061820225261522669665725399092057381501851855961629332200251877,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   8687116 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   8687116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"8.clkmgr_regwen.19987735486808025546967642469465246452798664242139939967923698438546585438763","seed":19987735486808025546967642469465246452798664242139939967923698438546585438763,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2367937 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   2367937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"10.clkmgr_regwen.39474217655697130596742996635050979120266861538109498113449326332472689298945","seed":39474217655697130596742996635050979120266861538109498113449326332472689298945,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5578873 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   5578873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"12.clkmgr_regwen.86541827528524190457135478265031509783466808871508559964509261912621553394127","seed":86541827528524190457135478265031509783466808871508559964509261912621553394127,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4257706 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   4257706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"13.clkmgr_regwen.63525565997276850058735785568330640879782729683837911666384504747833893239502","seed":63525565997276850058735785568330640879782729683837911666384504747833893239502,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2604455 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   2604455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"15.clkmgr_regwen.46019142332316095123431160488768706536643938749952940482250446609360997010085","seed":46019142332316095123431160488768706536643938749952940482250446609360997010085,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3246864 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   3246864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"16.clkmgr_regwen.3353838391180739462381534765195542986714833599797016251167659507886913303945","seed":3353838391180739462381534765195542986714833599797016251167659507886913303945,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  42182272 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @  42182272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"17.clkmgr_regwen.113986776860585149517336264844568636127629194388871399847763976300101176780759","seed":113986776860585149517336264844568636127629194388871399847763976300101176780759,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6609978 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   6609978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"19.clkmgr_regwen.48803839916339370330682963377771241005774175405147484486439922085656771222687","seed":48803839916339370330682963377771241005774175405147484486439922085656771222687,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  14702852 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @  14702852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"21.clkmgr_regwen.67100144506037010146673345455703132250803393676777577237587758006911870322926","seed":67100144506037010146673345455703132250803393676777577237587758006911870322926,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2581269 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   2581269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"28.clkmgr_regwen.86377347111946787390129614815096912407560763248382033912186408741462202912261","seed":86377347111946787390129614815096912407560763248382033912186408741462202912261,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/28.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   8543577 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   8543577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"31.clkmgr_regwen.100293100174130643222439018223378408751065938891390330170531943386556038854570","seed":100293100174130643222439018223378408751065938891390330170531943386556038854570,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2726688 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   2726688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"33.clkmgr_regwen.10307702121959863206811233281267099259489448221107886207155697929443467640169","seed":10307702121959863206811233281267099259489448221107886207155697929443467640169,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2321971 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   2321971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"37.clkmgr_regwen.93560448445772447102869007511919510283699884006232551642143137569741602568856","seed":93560448445772447102869007511919510283699884006232551642143137569741602568856,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3304527 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   3304527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"39.clkmgr_regwen.48056986262162545663106260549167778351661250800431355536107179148018859358592","seed":48056986262162545663106260549167778351661250800431355536107179148018859358592,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   8971215 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   8971215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"48.clkmgr_regwen.110018932691982831592091109346856443272314046775371682473766972635318632137271","seed":110018932691982831592091109346856443272314046775371682473766972635318632137271,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5176395 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   5176395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: *":[{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"0.clkmgr_shadow_reg_errors_with_csr_rw.97182623106459279884830470902611388656253222446593504252616836540414847044751","seed":97182623106459279884830470902611388656253222446593504252616836540414847044751,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  35825821 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  35825821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"0.clkmgr_tl_intg_err.86632366808362576103429478229806836946186516345459377234596745369903238119029","seed":86632366808362576103429478229806836946186516345459377234596745369903238119029,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   2837622 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2837622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"0.clkmgr_csr_mem_rw_with_rand_reset.48402245804655915898080038033776361300012591693142184196620689767200882644907","seed":48402245804655915898080038033776361300012591693142184196620689767200882644907,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  11011705 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  11011705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"1.clkmgr_shadow_reg_errors_with_csr_rw.77838821008789055528698865183634511108430587531434110723704300920689814280347","seed":77838821008789055528698865183634511108430587531434110723704300920689814280347,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2893972 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2893972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"1.clkmgr_tl_intg_err.81268312305763790157966278917609700051199257791671789284941562861777751161851","seed":81268312305763790157966278917609700051199257791671789284941562861777751161851,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   3682349 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   3682349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"1.clkmgr_csr_mem_rw_with_rand_reset.63155427143728041289232310961181542591679734519582583081957806238854738140398","seed":63155427143728041289232310961181542591679734519582583081957806238854738140398,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   4755830 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   4755830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"2.clkmgr_shadow_reg_errors_with_csr_rw.23698407096363534595397755029317664050043823560579206327628242910891019554501","seed":23698407096363534595397755029317664050043823560579206327628242910891019554501,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2183667 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2183667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"2.clkmgr_tl_intg_err.75762576134276617604807182785692934105596383209944727737275047217930585257971","seed":75762576134276617604807182785692934105596383209944727737275047217930585257971,"line":85,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   8818484 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   8818484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"2.clkmgr_csr_mem_rw_with_rand_reset.65288339443363109162127758925664308749845299703673311310226388750163064815400","seed":65288339443363109162127758925664308749845299703673311310226388750163064815400,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   4268951 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   4268951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"3.clkmgr_tl_intg_err.1117116647642718998517400320744076188518252673417139830563652112082879841628","seed":1117116647642718998517400320744076188518252673417139830563652112082879841628,"line":111,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  21786528 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  21786528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"4.clkmgr_shadow_reg_errors_with_csr_rw.6816071105686130904919799765355784852197770049448415628904158498216253728791","seed":6816071105686130904919799765355784852197770049448415628904158498216253728791,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3057951 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   3057951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"4.clkmgr_csr_mem_rw_with_rand_reset.6877472392154661496328787890614065400657656092980602959270759377270559010568","seed":6877472392154661496328787890614065400657656092980602959270759377270559010568,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  10830546 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  10830546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"5.clkmgr_tl_intg_err.9214834024621531941457550331741907056792634070668668575954846939933636539188","seed":9214834024621531941457550331741907056792634070668668575954846939933636539188,"line":86,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   8753067 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   8753067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"5.clkmgr_csr_rw.3678195054334249134318367366941692455016663146542000237081780073902333935000","seed":3678195054334249134318367366941692455016663146542000237081780073902333935000,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   4496463 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   4496463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"6.clkmgr_shadow_reg_errors_with_csr_rw.73312094386898077446862164580491206288997232162574237239159996118445201116806","seed":73312094386898077446862164580491206288997232162574237239159996118445201116806,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2186145 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2186145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"6.clkmgr_tl_intg_err.86569688130431955653150092887975007629983508730550258634665587392975836773000","seed":86569688130431955653150092887975007629983508730550258634665587392975836773000,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   3514134 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   3514134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"6.clkmgr_csr_rw.47068585150580278738297699631774007947570103957074764577812781977721258657267","seed":47068585150580278738297699631774007947570103957074764577812781977721258657267,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2798860 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2798860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"7.clkmgr_tl_intg_err.108171413591390038472894286147454440301674756011710731083062654663977165386059","seed":108171413591390038472894286147454440301674756011710731083062654663977165386059,"line":93,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  31142277 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  31142277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"7.clkmgr_csr_rw.75376591199636101806576223860710007166941338741154540872481893686182392848192","seed":75376591199636101806576223860710007166941338741154540872481893686182392848192,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   5462344 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   5462344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"8.clkmgr_tl_intg_err.1634047944596056537215250082360446213297022331933175487473874519508834663513","seed":1634047944596056537215250082360446213297022331933175487473874519508834663513,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   9313032 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   9313032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"8.clkmgr_csr_rw.431186904870773678561597818874055945724955951783502722591862465375325255224","seed":431186904870773678561597818874055945724955951783502722591862465375325255224,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2438688 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2438688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"9.clkmgr_shadow_reg_errors_with_csr_rw.66172945614022790654419490020849189080252523081049101399650103627425623308883","seed":66172945614022790654419490020849189080252523081049101399650103627425623308883,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3788170 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   3788170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"10.clkmgr_csr_rw.56319219044547723368292727127061823523681173788075657158313801400063216836227","seed":56319219044547723368292727127061823523681173788075657158313801400063216836227,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2456058 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2456058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"12.clkmgr_shadow_reg_errors_with_csr_rw.51625106646167619604632572065786546125137275120380123958497055139851262112028","seed":51625106646167619604632572065786546125137275120380123958497055139851262112028,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  37087062 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  37087062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"12.clkmgr_tl_intg_err.86691573842205679263064416999399887217210870029610868462581954355106408891327","seed":86691573842205679263064416999399887217210870029610868462581954355106408891327,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  24324971 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  24324971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"12.clkmgr_csr_rw.75658697419258912869549583232089408300016992508149899801912553902729931890062","seed":75658697419258912869549583232089408300016992508149899801912553902729931890062,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   7907052 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   7907052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"12.clkmgr_csr_mem_rw_with_rand_reset.42306300235510209551462546445960979447549988833896704101415356719792411912460","seed":42306300235510209551462546445960979447549988833896704101415356719792411912460,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  10772362 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  10772362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"13.clkmgr_shadow_reg_errors_with_csr_rw.33125393771951672793058128421443729349854975788018868677491360784724551662849","seed":33125393771951672793058128421443729349854975788018868677491360784724551662849,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   7332272 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   7332272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"13.clkmgr_tl_intg_err.14015558799704687586302038918016526704244276569902792029895821913778834443363","seed":14015558799704687586302038918016526704244276569902792029895821913778834443363,"line":93,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  13235983 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  13235983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"14.clkmgr_csr_rw.79332298933769819218819554562139765155466743759879721919042232908332636871421","seed":79332298933769819218819554562139765155466743759879721919042232908332636871421,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2280576 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2280576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"15.clkmgr_tl_intg_err.55101832601199163541167440223122134876734828052089536178848864231740773943805","seed":55101832601199163541167440223122134876734828052089536178848864231740773943805,"line":86,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  18049227 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  18049227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"16.clkmgr_shadow_reg_errors_with_csr_rw.37157637512087495481133823239168637081607435750096461138634300954275130063010","seed":37157637512087495481133823239168637081607435750096461138634300954275130063010,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  11437827 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  11437827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"17.clkmgr_shadow_reg_errors_with_csr_rw.85542812453609018535056423763759388019380236139008462458640534892855250010255","seed":85542812453609018535056423763759388019380236139008462458640534892855250010255,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   4734162 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   4734162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"17.clkmgr_tl_intg_err.95349663856992927067957735079257319888421247164077901138256846056886291641311","seed":95349663856992927067957735079257319888421247164077901138256846056886291641311,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   8741163 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   8741163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"19.clkmgr_shadow_reg_errors_with_csr_rw.74910552080985227610048422919121861692683705813030492687324033930525782110048","seed":74910552080985227610048422919121861692683705813030492687324033930525782110048,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  15480621 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  15480621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"19.clkmgr_tl_intg_err.50983873787185551246127233289015613943857756707660793280262068780979362912409","seed":50983873787185551246127233289015613943857756707660793280262068780979362912409,"line":85,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   5643126 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   5643126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *":[{"name":"clkmgr_csr_bit_bash","qual_name":"0.clkmgr_csr_bit_bash.20873516031229841425499825855331222251781837303030058788441444908738777532509","seed":20873516031229841425499825855331222251781837303030058788441444908738777532509,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @   1942657 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @   1942657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_bit_bash","qual_name":"1.clkmgr_csr_bit_bash.3574311737015931715495763522113182246248917451410629757295187614482065050134","seed":3574311737015931715495763522113182246248917451410629757295187614482065050134,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @  32774355 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @  32774355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_bit_bash","qual_name":"2.clkmgr_csr_bit_bash.51211931398663542266777962570140174757825042559820547385167979886483144578917","seed":51211931398663542266777962570140174757825042559820547385167979886483144578917,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @  88460401 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @  88460401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_bit_bash","qual_name":"3.clkmgr_csr_bit_bash.20401256046313396553909122645823129878713162766056487741210337905586069514461","seed":20401256046313396553909122645823129878713162766056487741210337905586069514461,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @ 124945565 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @ 124945565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_bit_bash","qual_name":"4.clkmgr_csr_bit_bash.75646776734023879923240877147423895522265507781092175584537908477428555119614","seed":75646776734023879923240877147423895522265507781092175584537908477428555119614,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @ 623978768 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @ 623978768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *":[{"name":"clkmgr_csr_aliasing","qual_name":"0.clkmgr_csr_aliasing.76939428256830883118381007854436386218935637681698712776454328978744690622600","seed":76939428256830883118381007854436386218935637681698712776454328978744690622600,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_aliasing/latest/run.log","log_context":["UVM_ERROR @   6265275 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   6265275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"1.clkmgr_csr_rw.54580624661234726708848598204919229155001801143159159265620017822540804020219","seed":54580624661234726708848598204919229155001801143159159265620017822540804020219,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3284103 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   3284103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"2.clkmgr_csr_rw.106913752437538363614199393995574994450866821907126083336266282132206171439596","seed":106913752437538363614199393995574994450866821907126083336266282132206171439596,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   6681709 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   6681709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_aliasing","qual_name":"2.clkmgr_csr_aliasing.112333948040178114526012939912725814465459020376080729815324704698279275945394","seed":112333948040178114526012939912725814465459020376080729815324704698279275945394,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_csr_aliasing/latest/run.log","log_context":["UVM_ERROR @  18923665 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  18923665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"3.clkmgr_shadow_reg_errors_with_csr_rw.34056965697474011098725480120281974508854512524950651211968518268875010343055","seed":34056965697474011098725480120281974508854512524950651211968518268875010343055,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   8562136 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   8562136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"4.clkmgr_tl_intg_err.3242847666594428773021954971517588971529004396234726549626697883530133930753","seed":3242847666594428773021954971517588971529004396234726549626697883530133930753,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  12519155 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  12519155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"5.clkmgr_shadow_reg_errors_with_csr_rw.69676061889104550231295367027224599373916934104824190023350290121348722990106","seed":69676061889104550231295367027224599373916934104824190023350290121348722990106,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3608996 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   3608996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"7.clkmgr_shadow_reg_errors_with_csr_rw.79151962587957160610716935120933094193749928361829564198754060678833373264108","seed":79151962587957160610716935120933094193749928361829564198754060678833373264108,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  26562409 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  26562409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"7.clkmgr_csr_mem_rw_with_rand_reset.30324424081022436555079630513686369674309878369616318101660740231296538703518","seed":30324424081022436555079630513686369674309878369616318101660740231296538703518,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  20919070 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  20919070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"8.clkmgr_shadow_reg_errors_with_csr_rw.58504615476440958466919832255696458425241943466373972028093197761485782266750","seed":58504615476440958466919832255696458425241943466373972028093197761485782266750,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3557601 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   3557601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"9.clkmgr_tl_intg_err.266055130790815452435232888362802570129650988973055554735919866394474353117","seed":266055130790815452435232888362802570129650988973055554735919866394474353117,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   2458429 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   2458429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"9.clkmgr_csr_rw.20345609084915656942778320987770312935884734309671537024014181366335125758915","seed":20345609084915656942778320987770312935884734309671537024014181366335125758915,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2922003 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   2922003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"9.clkmgr_csr_mem_rw_with_rand_reset.12329002404004622585613355454745908435957377858834205905939921759841342019647","seed":12329002404004622585613355454745908435957377858834205905939921759841342019647,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  38429507 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  38429507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"10.clkmgr_shadow_reg_errors_with_csr_rw.541508630458019614060416831266607785459783152731715904527385751427231422522","seed":541508630458019614060416831266607785459783152731715904527385751427231422522,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  17195694 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  17195694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"10.clkmgr_tl_intg_err.17701173018128533868561460536551294594617038563083433655478726699971003491322","seed":17701173018128533868561460536551294594617038563083433655478726699971003491322,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   2827244 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   2827244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"10.clkmgr_csr_mem_rw_with_rand_reset.115181378334066872368821410909821546450871003893241266768237504872283755814134","seed":115181378334066872368821410909821546450871003893241266768237504872283755814134,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   2942568 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   2942568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"11.clkmgr_shadow_reg_errors_with_csr_rw.13346768269157422008311302488363058884764393383362487548805833955869415637463","seed":13346768269157422008311302488363058884764393383362487548805833955869415637463,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   8690630 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   8690630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"11.clkmgr_tl_intg_err.42048396255023047437325842413213729266935789646138944287450354109430291111018","seed":42048396255023047437325842413213729266935789646138944287450354109430291111018,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   7536519 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   7536519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"11.clkmgr_csr_rw.95380296377074553868450903064194152757056138721120755342521603177675280659981","seed":95380296377074553868450903064194152757056138721120755342521603177675280659981,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2664370 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   2664370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"11.clkmgr_csr_mem_rw_with_rand_reset.98592013473907625406349040821120822457188922643023574119966875554676486659433","seed":98592013473907625406349040821120822457188922643023574119966875554676486659433,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  37826226 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  37826226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"14.clkmgr_shadow_reg_errors_with_csr_rw.61120948029064599244873636116475937391613476800709302982699624237161962337052","seed":61120948029064599244873636116475937391613476800709302982699624237161962337052,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2499247 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   2499247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"14.clkmgr_tl_intg_err.111136888337476373809213609135508698384115544320996374240421652059758887511522","seed":111136888337476373809213609135508698384115544320996374240421652059758887511522,"line":85,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   4079902 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   4079902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"14.clkmgr_csr_mem_rw_with_rand_reset.28789834175019609238630505071320865611609733078014898366278390166744183461000","seed":28789834175019609238630505071320865611609733078014898366278390166744183461000,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  34996801 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  34996801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"15.clkmgr_shadow_reg_errors_with_csr_rw.11340751540525840462686751232795142211063010695606957718264564355978651860122","seed":11340751540525840462686751232795142211063010695606957718264564355978651860122,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  14661615 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  14661615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"15.clkmgr_csr_rw.45088305509897129626212798768425506187857522282615359577488745603014261961686","seed":45088305509897129626212798768425506187857522282615359577488745603014261961686,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   7232487 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   7232487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"16.clkmgr_tl_intg_err.47763596639759781156464015193574605738600662511569005107027678991008817762434","seed":47763596639759781156464015193574605738600662511569005107027678991008817762434,"line":98,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  25386852 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  25386852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"16.clkmgr_csr_rw.58891279032359735720196298160713469834471873880460917641514403969391878409505","seed":58891279032359735720196298160713469834471873880460917641514403969391878409505,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @  35730127 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  35730127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"16.clkmgr_csr_mem_rw_with_rand_reset.59383165975766667006351046951098997131072518751649391918705156464485073172092","seed":59383165975766667006351046951098997131072518751649391918705156464485073172092,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   6879867 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   6879867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"17.clkmgr_csr_rw.64722071779903063000810073383990478020142106192824841133103024154007051292523","seed":64722071779903063000810073383990478020142106192824841133103024154007051292523,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3460198 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   3460198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"18.clkmgr_shadow_reg_errors_with_csr_rw.33266789616816896757405820075290909186789330782210928969687001171088473228518","seed":33266789616816896757405820075290909186789330782210928969687001171088473228518,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   9585076 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   9585076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"18.clkmgr_tl_intg_err.91224901708037503259063873464494486000855741131561527580742312437883812044632","seed":91224901708037503259063873464494486000855741131561527580742312437883812044632,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   1909879 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   1909879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"19.clkmgr_csr_mem_rw_with_rand_reset.60684919682903470655909759685890287388793006644853628613189200771814357368878","seed":60684919682903470655909759685890287388793006644853628613189200771814357368878,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   2314947 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   2314947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch":[{"name":"clkmgr_same_csr_outstanding","qual_name":"0.clkmgr_same_csr_outstanding.68984641276168065667821012696866788341579070181881634642299196275133645262247","seed":68984641276168065667821012696866788341579070181881634642299196275133645262247,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   5853247 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (63700 [0xf8d4] vs 180673 [0x2c1c1]) addr 0x2ec7392c read out mismatch\n","UVM_INFO @   5853247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"1.clkmgr_same_csr_outstanding.58678748284669263639813597642020219126142189045980710664454768156271633319889","seed":58678748284669263639813597642020219126142189045980710664454768156271633319889,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   2583887 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x58acdf24 read out mismatch\n","UVM_INFO @   2583887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"2.clkmgr_same_csr_outstanding.26693176179490778594497801003081774390080719143130227110501102687762360997023","seed":26693176179490778594497801003081774390080719143130227110501102687762360997023,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   3082751 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x2732c024 read out mismatch\n","UVM_INFO @   3082751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"3.clkmgr_same_csr_outstanding.71617681360942133778934742408848451370229549526184036297425379744274385801301","seed":71617681360942133778934742408848451370229549526184036297425379744274385801301,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   3303056 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x5300a4a4 read out mismatch\n","UVM_INFO @   3303056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"4.clkmgr_same_csr_outstanding.28546241621261779559907111236685323944933673303476836910337589663436715304005","seed":28546241621261779559907111236685323944933673303476836910337589663436715304005,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   3106694 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xfbbefbe4 read out mismatch\n","UVM_INFO @   3106694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"5.clkmgr_same_csr_outstanding.51786295300067479280056362158834150930378513096158580079196340039419222941932","seed":51786295300067479280056362158834150930378513096158580079196340039419222941932,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  48010979 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x7c6f2f24 read out mismatch\n","UVM_INFO @  48010979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"6.clkmgr_same_csr_outstanding.21154523878120503168363391071514364458127418415904923773014686839580271912916","seed":21154523878120503168363391071514364458127418415904923773014686839580271912916,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  24744505 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (81496 [0x13e58] vs 60554 [0xec8a]) addr 0x3e2f4aac read out mismatch\n","UVM_INFO @  24744505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"7.clkmgr_same_csr_outstanding.31953261188107694215477633949224615340327211888342763197685678807455584932541","seed":31953261188107694215477633949224615340327211888342763197685678807455584932541,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   8601257 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x729850e4 read out mismatch\n","UVM_INFO @   8601257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"8.clkmgr_same_csr_outstanding.12808161406453188686693864035195550147006250579290246405304815197966782680452","seed":12808161406453188686693864035195550147006250579290246405304815197966782680452,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  17739772 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x744babe4 read out mismatch\n","UVM_INFO @  17739772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"9.clkmgr_same_csr_outstanding.16579208117148290205666774543728818091299114320564969452023808004059487999129","seed":16579208117148290205666774543728818091299114320564969452023808004059487999129,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  31705482 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xf3640de4 read out mismatch\n","UVM_INFO @  31705482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"10.clkmgr_same_csr_outstanding.91747186465510797756697648202444686366685440009855338131369520414190864085758","seed":91747186465510797756697648202444686366685440009855338131369520414190864085758,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   8104865 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xf29c9fe4 read out mismatch\n","UVM_INFO @   8104865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"11.clkmgr_same_csr_outstanding.14537836394260258824610259958580026338048375742210778612403132381664369756072","seed":14537836394260258824610259958580026338048375742210778612403132381664369756072,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   2730857 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xb5c880e4 read out mismatch\n","UVM_INFO @   2730857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"12.clkmgr_same_csr_outstanding.52996845436365593717806510179829322137513564728932178124785914635280686456112","seed":52996845436365593717806510179829322137513564728932178124785914635280686456112,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  18203556 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x782b84e4 read out mismatch\n","UVM_INFO @  18203556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"13.clkmgr_same_csr_outstanding.9225445201089605959573155390134006362942016577504734505064086400587159803845","seed":9225445201089605959573155390134006362942016577504734505064086400587159803845,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   6272011 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (69216 [0x10e60] vs 60554 [0xec8a]) addr 0x1f6bd974 read out mismatch\n","UVM_INFO @   6272011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"14.clkmgr_same_csr_outstanding.42554744689227060093808175547676379195310219619477985421976979789069515667606","seed":42554744689227060093808175547676379195310219619477985421976979789069515667606,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   8171122 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xf9ad0ca4 read out mismatch\n","UVM_INFO @   8171122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"15.clkmgr_same_csr_outstanding.50788577543732875482572969407632197117892062790882616632820479052538290667523","seed":50788577543732875482572969407632197117892062790882616632820479052538290667523,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  44208589 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x7ddc81e4 read out mismatch\n","UVM_INFO @  44208589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"16.clkmgr_same_csr_outstanding.83784152154906052196406085596084719825868669656873111628122121153809099814837","seed":83784152154906052196406085596084719825868669656873111628122121153809099814837,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  12997084 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (137969 [0x21af1] vs 194916 [0x2f964]) addr 0x45a61bac read out mismatch\n","UVM_INFO @  12997084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"17.clkmgr_same_csr_outstanding.29282526763243908706252223255659305307483616191986429436527319791155685488184","seed":29282526763243908706252223255659305307483616191986429436527319791155685488184,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   4958041 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x8470bda4 read out mismatch\n","UVM_INFO @   4958041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"18.clkmgr_same_csr_outstanding.74546618884346308842145426277701938762509959385823384497964690232476113184804","seed":74546618884346308842145426277701938762509959385823384497964690232476113184804,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  10248412 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xcdb517e4 read out mismatch\n","UVM_INFO @  10248412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"19.clkmgr_same_csr_outstanding.48652378128957963620933452799723638926515827618142366631119130066235998602999","seed":48652378128957963620933452799723638926515827618142366631119130066235998602999,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  14636003 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x6cf53a64 read out mismatch\n","UVM_INFO @  14636003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":586,"total":1205,"percent":48.63070539419087}