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---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"1.lc_ctrl_stress_all_with_rand_reset.66279473194266008064982903858647405005878683671690792043178902606320820059129","seed":66279473194266008064982903858647405005878683671690792043178902606320820059129,"line":9192,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1628424486 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1628424486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"2.lc_ctrl_stress_all_with_rand_reset.70280890430720751481753433004907498720618183473698148374131198195753490065324","seed":70280890430720751481753433004907498720618183473698148374131198195753490065324,"line":5233,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5769100029 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5769100029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"3.lc_ctrl_stress_all_with_rand_reset.72902720032754382744372837894783216679316476261656125090275409227362018500945","seed":72902720032754382744372837894783216679316476261656125090275409227362018500945,"line":1329,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5579360649 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5579360649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"6.lc_ctrl_stress_all_with_rand_reset.43316300568304641918334550350398398418899829181908551674664090777832173086008","seed":43316300568304641918334550350398398418899829181908551674664090777832173086008,"line":166,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 985693743 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 985693743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"12.lc_ctrl_stress_all_with_rand_reset.61025862887164596142332507184539258107143820517562644502587229449021676951659","seed":61025862887164596142332507184539258107143820517562644502587229449021676951659,"line":1059,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 14359231115 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 14359231115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"13.lc_ctrl_stress_all_with_rand_reset.18299208740274430804990815044548690168566634181575853654793671842016705732032","seed":18299208740274430804990815044548690168566634181575853654793671842016705732032,"line":6769,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 23257216073 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 23257216073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"15.lc_ctrl_stress_all_with_rand_reset.91687750994718624899351119349415463416844665277689182604137972603358157578256","seed":91687750994718624899351119349415463416844665277689182604137972603358157578256,"line":158,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 385158596 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 385158596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"16.lc_ctrl_stress_all_with_rand_reset.52754818825839620870680365034270464654870537827310586755718199137572929263197","seed":52754818825839620870680365034270464654870537827310586755718199137572929263197,"line":438,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1165596218 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1165596218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"17.lc_ctrl_stress_all_with_rand_reset.71527944316726429281436019718838809253361014307069212770151622925039710855753","seed":71527944316726429281436019718838809253361014307069212770151622925039710855753,"line":2208,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8721224106 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 8721224106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"20.lc_ctrl_stress_all_with_rand_reset.74990035475569255972475188690673113010041245201125529335118227115342486895536","seed":74990035475569255972475188690673113010041245201125529335118227115342486895536,"line":7523,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3657822826 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3657822826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"24.lc_ctrl_stress_all_with_rand_reset.34840803998470976285274929650145107724594696927287035761745730583238446411515","seed":34840803998470976285274929650145107724594696927287035761745730583238446411515,"line":6875,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1956164947 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1956164947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"27.lc_ctrl_stress_all_with_rand_reset.65755168768307241569063977927199173133204567723178257270491320575631332033754","seed":65755168768307241569063977927199173133204567723178257270491320575631332033754,"line":6593,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 994992187 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 994992187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"28.lc_ctrl_stress_all_with_rand_reset.1199946052718607387526072216219497354055090929551131308308216020776980280726","seed":1199946052718607387526072216219497354055090929551131308308216020776980280726,"line":2192,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2955300755 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2955300755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"31.lc_ctrl_stress_all_with_rand_reset.12175603449089377913961885336515543122841887763108598884582406484718097485532","seed":12175603449089377913961885336515543122841887763108598884582406484718097485532,"line":6979,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 17679164999 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 17679164999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"33.lc_ctrl_stress_all_with_rand_reset.62190881510953850386632095754056425788847947780418348236293430239606319233912","seed":62190881510953850386632095754056425788847947780418348236293430239606319233912,"line":256,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 987170900 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 987170900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"37.lc_ctrl_stress_all_with_rand_reset.70273437792417623212974859400723165754971426104066602612669585705009265726939","seed":70273437792417623212974859400723165754971426104066602612669585705009265726939,"line":3588,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6545521044 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 6545521044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"41.lc_ctrl_stress_all_with_rand_reset.68431965826897042094454196116704415335313830934222598986245217773438156595524","seed":68431965826897042094454196116704415335313830934222598986245217773438156595524,"line":5005,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 11386926887 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 11386926887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"42.lc_ctrl_stress_all_with_rand_reset.34494580482654132052474858964993466970920854365344452653227003148553628418227","seed":34494580482654132052474858964993466970920854365344452653227003148553628418227,"line":5916,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 23377057298 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 23377057298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"43.lc_ctrl_stress_all_with_rand_reset.79107686242043235096402291081466442141560363681342619317630672970552880772804","seed":79107686242043235096402291081466442141560363681342619317630672970552880772804,"line":167,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 10038357944 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 10038357944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"44.lc_ctrl_stress_all_with_rand_reset.30513830030842797419379226862335350396829280359218247190531050430776259225988","seed":30513830030842797419379226862335350396829280359218247190531050430776259225988,"line":2969,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5992861179 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5992861179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"45.lc_ctrl_stress_all_with_rand_reset.9477840811997762478157136523973509770921909537062308136000576113776428483225","seed":9477840811997762478157136523973509770921909537062308136000576113776428483225,"line":3630,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4328719809 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4328719809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"47.lc_ctrl_stress_all_with_rand_reset.38286255008103081253350088816914058897145588443361148583119582539301122105543","seed":38286255008103081253350088816914058897145588443361148583119582539301122105543,"line":3532,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2817835238 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2817835238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"48.lc_ctrl_stress_all_with_rand_reset.32561445445680015412265114258202973799124351081565998268343958217846331996747","seed":32561445445680015412265114258202973799124351081565998268343958217846331996747,"line":7849,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8008369458 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 8008369458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"8.lc_ctrl_stress_all_with_rand_reset.36235244438452189639993899334968693045382570697900681164794410208801833900771","seed":36235244438452189639993899334968693045382570697900681164794410208801833900771,"line":5291,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8732072682 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error\n","UVM_INFO @ 8732072682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"11.lc_ctrl_stress_all_with_rand_reset.41275597474759059631254174160404461381974513946587892280269814965337880407896","seed":41275597474759059631254174160404461381974513946587892280269814965337880407896,"line":15152,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 28662607259 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error\n","UVM_INFO @ 28662607259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (lc_ctrl_scoreboard.sv:248) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked*":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"10.lc_ctrl_stress_all_with_rand_reset.56699391676508780972247035984949222305669522747912457461379883937648078094799","seed":56699391676508780972247035984949222305669522747912457461379883937648078094799,"line":1706,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 935732143 ps: (lc_ctrl_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 105, LC_St DecLcStTestLocked6\n","UVM_INFO @ 935732143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":2008,"total":2035,"percent":98.67321867321867}