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code":[{"name":"otbn_alu_bignum_mod_err","qual_name":"0.otbn_alu_bignum_mod_err.5747298055671499537796169251540668849882379880021593493590839782318537773772","seed":5747298055671499537796169251540668849882379880021593493590839782318537773772,"line":null,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest/run.log","log_context":["\n","\n","[make]: pre_run\n","mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest\n","cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 5747298055671499537796169251540668849882379880021593493590839782318537773772 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest/otbn-binaries\n","/nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest\n","2026/03/28 05:02:13 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...\n","Opening zip \"/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)\": open(): No such file or directory\n","FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36\n"]},{"name":"otbn_multi","qual_name":"4.otbn_multi.2611816125439049135211282560837061579475179279309596899642122645117675036104","seed":2611816125439049135211282560837061579475179279309596899642122645117675036104,"line":null,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/4.otbn_multi/latest/run.log","log_context":["                   ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 122, in _gen_loop_head\n","    enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)\n","                             ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 67, in _pick_bodysize\n","    assert bodysize is not None\n","           ^^^^^^^^^^^^^^^^^^^^\n","AssertionError\n","ninja: build stopped: subcommand failed.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1\n"]}],"xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed":[{"name":"otbn_stack_addr_integ_chk","qual_name":"0.otbn_stack_addr_integ_chk.973928436515138994574194977862702545669651304327256695847300020813992476577","seed":973928436515138994574194977862702545669651304327256695847300020813992476577,"line":123,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log","log_context":["xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 17728262 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed \n","UVM_ERROR @  17728262 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A\n","UVM_INFO @  17728262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"otbn_escalate","qual_name":"37.otbn_escalate.58623448853416082687094538482225080530366906653736475643450119850189579788317","seed":58623448853416082687094538482225080530366906653736475643450119850189579788317,"line":116,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/37.otbn_escalate/latest/run.log","log_context":["xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 26887558 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed \n","UVM_ERROR @  26887558 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A\n","UVM_INFO @  26887558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"otbn_stress_all_with_rand_reset","qual_name":"2.otbn_stress_all_with_rand_reset.38984992753625286408873353985317194687987851917957343449544921023586016598984","seed":38984992753625286408873353985317194687987851917957343449544921023586016598984,"line":177,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1668325630 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1668325630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"4.otbn_stress_all_with_rand_reset.24198646691856932669923794525230694448880339344709956551740036306894850081372","seed":24198646691856932669923794525230694448880339344709956551740036306894850081372,"line":171,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 355179352 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 355179352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"7.otbn_stress_all_with_rand_reset.27289450906197502417429412030879346756904193709456129896991018017374406179601","seed":27289450906197502417429412030879346756904193709456129896991018017374406179601,"line":432,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1252760392 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1252760392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)":[{"name":"otbn_stress_all_with_rand_reset","qual_name":"3.otbn_stress_all_with_rand_reset.68455184895812086432598917019137593274604620061948076932680073536660556532291","seed":68455184895812086432598917019137593274604620061948076932680073536660556532291,"line":172,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 285630928 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)  \n","UVM_INFO @ 285630928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"9.otbn_stress_all_with_rand_reset.49879620958411295988447755844522389745404807814593894819338940885504151600664","seed":49879620958411295988447755844522389745404807814593894819338940885504151600664,"line":718,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 1553650292 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)  \n","UVM_INFO @ 1553650292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1850,"total":1867,"percent":99.08944831280128}