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[`114d1c4`](https://github.com/lowrisc/opentitan/tree/114d1c49baa0199187d94a8aef571ce286b15a72)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-03-27T17:03:20Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/spi_device_1r1w/data/spi_device_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"spi_device_flash_and_tpm":{"max_time":420.93,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.14,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"spi_device_csr_rw":{"max_time":1.96,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"spi_device_csr_bit_bash":{"max_time":20.22,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"spi_device_csr_aliasing":{"max_time":14.92,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"spi_device_csr_mem_rw_with_rand_reset":{"max_time":3.2,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"spi_device_csr_rw":{"max_time":1.96,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"spi_device_csr_aliasing":{"max_time":14.92,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"mem_walk":{"tests":{"spi_device_mem_walk":{"max_time":0.68,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"mem_partial_access":{"tests":{"spi_device_mem_partial_access":{"max_time":1.79,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0}},"passed":140,"total":140,"percent":100.0},"V2":{"testpoints":{"csb_read":{"tests":{"spi_device_csb_read":{"max_time":1.12,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"mem_parity":{"tests":{"spi_device_mem_parity":{"max_time":1.03,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"mem_cfg":{"tests":{"spi_device_ram_cfg":{"max_time":0.78,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"tpm_read":{"tests":{"spi_device_tpm_rw":{"max_time":6.86,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tpm_write":{"tests":{"spi_device_tpm_rw":{"max_time":6.86,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tpm_hw_reg":{"tests":{"spi_device_tpm_read_hw_reg":{"max_time":20.98,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"spi_device_tpm_sts_read":{"max_time":1.38,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"tpm_fully_random_case":{"tests":{"spi_device_tpm_all":{"max_time":39.52,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"pass_cmd_filtering":{"tests":{"spi_device_pass_cmd_filtering":{"max_time":22.06,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":290.91,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"pass_addr_translation":{"tests":{"spi_device_pass_addr_payload_swap":{"max_time":31.18,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":290.91,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"pass_payload_translation":{"tests":{"spi_device_pass_addr_payload_swap":{"max_time":31.18,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":290.91,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"cmd_info_slots":{"tests":{"spi_device_flash_all":{"max_time":290.91,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"cmd_read_status":{"tests":{"spi_device_intercept":{"max_time":28.96,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":290.91,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"cmd_read_jedec":{"tests":{"spi_device_intercept":{"max_time":28.96,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":290.91,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"cmd_read_sfdp":{"tests":{"spi_device_intercept":{"max_time":28.96,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":290.91,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"cmd_fast_read":{"tests":{"spi_device_intercept":{"max_time":28.96,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":290.91,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"cmd_read_pipeline":{"tests":{"spi_device_intercept":{"max_time":28.96,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":290.91,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"flash_cmd_upload":{"tests":{"spi_device_upload":{"max_time":29.04,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"mailbox_command":{"tests":{"spi_device_mailbox":{"max_time":84.79,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"mailbox_cross_outside_command":{"tests":{"spi_device_mailbox":{"max_time":84.79,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"mailbox_cross_inside_command":{"tests":{"spi_device_mailbox":{"max_time":84.79,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"cmd_read_buffer":{"tests":{"spi_device_flash_mode":{"max_time":47.5,"sim_time":0.0,"passed":49,"total":50,"percent":98.0},"spi_device_read_buffer_direct":{"max_time":25.98,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":99,"total":100,"percent":99.0},"cmd_dummy_cycle":{"tests":{"spi_device_mailbox":{"max_time":84.79,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":290.91,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"quad_spi":{"tests":{"spi_device_flash_all":{"max_time":290.91,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"dual_spi":{"tests":{"spi_device_flash_all":{"max_time":290.91,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"4b_3b_feature":{"tests":{"spi_device_cfg_cmd":{"max_time":26.21,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"write_enable_disable":{"tests":{"spi_device_cfg_cmd":{"max_time":26.21,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"TPM_with_flash_or_passthrough_mode":{"tests":{"spi_device_flash_and_tpm":{"max_time":420.93,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tpm_and_flash_trans_with_min_inactive_time":{"tests":{"spi_device_flash_and_tpm_min_idle":{"max_time":410.97,"sim_time":0.0,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0},"stress_all":{"tests":{"spi_device_stress_all":{"max_time":596.31,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"alert_test":{"tests":{"spi_device_alert_test":{"max_time":1.07,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"spi_device_intr_test":{"max_time":0.77,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"spi_device_tl_errors":{"max_time":4.36,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"spi_device_tl_errors":{"max_time":4.36,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.14,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"spi_device_csr_rw":{"max_time":1.96,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"spi_device_csr_aliasing":{"max_time":14.92,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":3.24,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.14,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"spi_device_csr_rw":{"max_time":1.96,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"spi_device_csr_aliasing":{"max_time":14.92,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":3.24,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":2138,"total":2161,"percent":98.9356779268857},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"spi_device_tl_intg_err":{"max_time":15.79,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"spi_device_sec_cm":{"max_time":1.46,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"spi_device_tl_intg_err":{"max_time":15.79,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0}},"passed":45,"total":45,"percent":100.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"spi_device_flash_mode_ignore_cmds":{"max_time":255.50000000000003,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"coverage":{"code":{"block":null,"line_statement":99.1,"branch":98.4,"condition_expression":96.56,"toggle":83.54,"fsm":89.36},"assertion":94.76,"functional":99.26},"cov_report_page":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])":[{"name":"spi_device_mem_parity","qual_name":"0.spi_device_mem_parity.90959265106549351275715450222456264218035810388831250307279297811603422812288","seed":90959265106549351275715450222456264218035810388831250307279297811603422812288,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   3524612 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[96])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3524612 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3524612 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[992])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"1.spi_device_mem_parity.6349143305575658914570348245302052997737004922743500698820529985168007737801","seed":6349143305575658914570348245302052997737004922743500698820529985168007737801,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   4360724 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[16])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4360724 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4360724 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[912])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"2.spi_device_mem_parity.41359894619284852933114704492878962601673575920456710597677740529585570641253","seed":41359894619284852933114704492878962601673575920456710597677740529585570641253,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/2.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   5417518 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[7])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   5417518 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   5417518 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[903])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"3.spi_device_mem_parity.52458210429497616350716703001806145230326716876327994613340637284113072525767","seed":52458210429497616350716703001806145230326716876327994613340637284113072525767,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/3.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @    981803 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[16])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    981803 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    981803 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[912])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"4.spi_device_mem_parity.98588636981805391736451489086590062041114278949855863961200485487654579515054","seed":98588636981805391736451489086590062041114278949855863961200485487654579515054,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/4.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   8810957 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[109])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   8810957 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   8810957 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1005])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"5.spi_device_mem_parity.114373445652166415829944288695736097092289975473608694910641554012806644463886","seed":114373445652166415829944288695736097092289975473608694910641554012806644463886,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/5.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   1208293 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[81])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1208293 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1208293 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[977])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"6.spi_device_mem_parity.45904390315610481154633994729613183274548462865410732082603156836802598080441","seed":45904390315610481154633994729613183274548462865410732082603156836802598080441,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/6.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @  23671128 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[82])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @  23671128 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @  23671128 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[978])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"7.spi_device_mem_parity.61349044489479389760628119858964106747362228359569152404949482040082174074211","seed":61349044489479389760628119858964106747362228359569152404949482040082174074211,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/7.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   5376755 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[18])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   5376755 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   5376755 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[914])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"8.spi_device_mem_parity.53984597135301179783651462643716092224071181235105837620520380798253475061276","seed":53984597135301179783651462643716092224071181235105837620520380798253475061276,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/8.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   6608416 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   6608416 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   6608416 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[897])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"9.spi_device_mem_parity.40508394120841477016449682888252938831516276553492705143635511128706538862711","seed":40508394120841477016449682888252938831516276553492705143635511128706538862711,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/9.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @  11163691 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[24])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @  11163691 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @  11163691 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[920])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"10.spi_device_mem_parity.96618837212896469601131078338945226897618085361471407144069655973745064809077","seed":96618837212896469601131078338945226897618085361471407144069655973745064809077,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/10.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   3109727 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[49])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3109727 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3109727 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[945])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"11.spi_device_mem_parity.71081556082279029549793739259716348490046592754849147738679850199164123296171","seed":71081556082279029549793739259716348490046592754849147738679850199164123296171,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/11.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   1918534 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[103])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1918534 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1918534 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[999])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"12.spi_device_mem_parity.81384240591640243449755810529644732052028787650518003517615624220262624574182","seed":81384240591640243449755810529644732052028787650518003517615624220262624574182,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/12.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @  12369608 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[106])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @  12369608 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @  12369608 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1002])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"13.spi_device_mem_parity.14159324825045667558875935677926193426231896867065702101474874431890558141494","seed":14159324825045667558875935677926193426231896867065702101474874431890558141494,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/13.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   1657254 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[58])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1657254 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1657254 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[954])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"14.spi_device_mem_parity.45496101533794286530344164314057840751393505839113772086082668468787103994909","seed":45496101533794286530344164314057840751393505839113772086082668468787103994909,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/14.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   1013178 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[56])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1013178 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1013178 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[952])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"15.spi_device_mem_parity.101761801482631612908792926034432649478228834332063108056651501415892313022515","seed":101761801482631612908792926034432649478228834332063108056651501415892313022515,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/15.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   9136631 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[7])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   9136631 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   9136631 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[903])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"16.spi_device_mem_parity.56752040590710445601033713982266152881792331153429143208103283769233961386637","seed":56752040590710445601033713982266152881792331153429143208103283769233961386637,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/16.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   4241366 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[78])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4241366 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4241366 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[974])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"17.spi_device_mem_parity.105022635988492289709727861034685860392547671944828359856597338699079360643119","seed":105022635988492289709727861034685860392547671944828359856597338699079360643119,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/17.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   5023662 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[41])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   5023662 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   5023662 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[937])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"18.spi_device_mem_parity.39237651640999951046481326578557507277236414294209411331921549540025675964060","seed":39237651640999951046481326578557507277236414294209411331921549540025675964060,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/18.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   6046603 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[86])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   6046603 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   6046603 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[982])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"19.spi_device_mem_parity.65127702554435379692827820663564921526008807281867615883979662413595253610561","seed":65127702554435379692827820663564921526008807281867615883979662413595253610561,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/19.spi_device_mem_parity/latest/run.log","log_context":["UVM_ERROR @   3735832 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[29])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3735832 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3735832 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[925])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]}],"UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])":[{"name":"spi_device_ram_cfg","qual_name":"0.spi_device_ram_cfg.94115172827604865580211101947997880917312999449770719088587762512271258088772","seed":94115172827604865580211101947997880917312999449770719088587762512271258088772,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log","log_context":["UVM_ERROR @   5686099 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xdf0a29 [110111110000101000101001] vs 0x0 [0]) \n","UVM_ERROR @   5742099 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x82b1f7 [100000101011000111110111] vs 0x0 [0]) \n","UVM_ERROR @   5774099 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6c2a07 [11011000010101000000111] vs 0x0 [0]) \n","UVM_ERROR @   5822099 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xaabacd [101010101011101011001101] vs 0x0 [0]) \n","UVM_ERROR @   5870099 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa4674f [101001000110011101001111] vs 0x0 [0]) \n"]}],"UVM_ERROR (spi_device_scoreboard.sv:2815) [scoreboard] Check failed |(intr_trigger_pending & interrupt_mask) == * (* [*] vs * [*])":[{"name":"spi_device_flash_mode","qual_name":"20.spi_device_flash_mode.84795194866678472082642972975215546630859798678867752542035556689732331131938","seed":84795194866678472082642972975215546630859798678867752542035556689732331131938,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode/latest/run.log","log_context":["UVM_ERROR @ 1405475226 ps: (spi_device_scoreboard.sv:2815) [uvm_test_top.env.scoreboard] Check failed |(intr_trigger_pending & interrupt_mask) == 0 (1 [0x1] vs 0 [0x0]) \n","UVM_INFO @ 1405475226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp *":[{"name":"spi_device_flash_and_tpm_min_idle","qual_name":"28.spi_device_flash_and_tpm_min_idle.47750087003381344069754340495361084136146088269691239935177642263602531445899","seed":47750087003381344069754340495361084136146088269691239935177642263602531445899,"line":91,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest/run.log","log_context":["UVM_ERROR @ 776929384 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (10363904 [0x9e2400] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0x9e2400 != exp 0x0\n","tl_ul_fuzzy_flash_status_q[i] = 0x9454ba\n","tl_ul_fuzzy_flash_status_q[i] = 0x5d826c\n","tl_ul_fuzzy_flash_status_q[i] = 0x5584e8\n","UVM_INFO @ 947413823 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 2/10\n"]}]}},"passed":2373,"total":2396,"percent":99.04006677796328}