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(csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: *":[{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"0.clkmgr_shadow_reg_errors_with_csr_rw.41913757902072614428260685371925214242224614516421404335195287497090834301399","seed":41913757902072614428260685371925214242224614516421404335195287497090834301399,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   4741007 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   4741007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"0.clkmgr_tl_intg_err.62108879613636301603200538208948405713179824957288761609655677562749675804202","seed":62108879613636301603200538208948405713179824957288761609655677562749675804202,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   2779556 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2779556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"0.clkmgr_csr_mem_rw_with_rand_reset.69425234405070769985681798145208416742824553942757405618099995930382828743532","seed":69425234405070769985681798145208416742824553942757405618099995930382828743532,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   6142546 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   6142546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"1.clkmgr_csr_rw.90776182212387668732192438238460282884878082305057283896385756780791431223543","seed":90776182212387668732192438238460282884878082305057283896385756780791431223543,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2823368 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2823368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"2.clkmgr_tl_intg_err.8298069506867302445254544029537259023968100699681108688510767576671153540641","seed":8298069506867302445254544029537259023968100699681108688510767576671153540641,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   4724908 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   4724908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"3.clkmgr_shadow_reg_errors_with_csr_rw.54275984890467626020606367546961295321682965337142215409226238933493195125796","seed":54275984890467626020606367546961295321682965337142215409226238933493195125796,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  14320826 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  14320826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"3.clkmgr_tl_intg_err.69266415734941477740636021108393908478114891409030859018689698869198594835262","seed":69266415734941477740636021108393908478114891409030859018689698869198594835262,"line":86,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   9395463 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   9395463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"3.clkmgr_csr_rw.78916893063779763117959501037308286098453301783621533087271372833826444007500","seed":78916893063779763117959501037308286098453301783621533087271372833826444007500,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @  35385032 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  35385032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"4.clkmgr_tl_intg_err.61414231678954521488210183041833184199213060842193738106418222945408988307059","seed":61414231678954521488210183041833184199213060842193738106418222945408988307059,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  19490747 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  19490747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"4.clkmgr_csr_mem_rw_with_rand_reset.75248391938104197016143573588865206260884825561918650942755085110559809859035","seed":75248391938104197016143573588865206260884825561918650942755085110559809859035,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  14893148 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  14893148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"5.clkmgr_shadow_reg_errors_with_csr_rw.103528451780579740807718334095591361531527809509513635208580855924999967731510","seed":103528451780579740807718334095591361531527809509513635208580855924999967731510,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   4542097 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   4542097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"5.clkmgr_csr_rw.72707880880590777381341202815807744552526119907978948092608047474366981359926","seed":72707880880590777381341202815807744552526119907978948092608047474366981359926,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2895461 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2895461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"5.clkmgr_csr_mem_rw_with_rand_reset.27012691397131810477038291981434499254862505941949458490821352956468099511186","seed":27012691397131810477038291981434499254862505941949458490821352956468099511186,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   3447673 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   3447673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"6.clkmgr_shadow_reg_errors_with_csr_rw.86417937911233518062149381956240861434073677664097530246742166625890466610733","seed":86417937911233518062149381956240861434073677664097530246742166625890466610733,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   7343709 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   7343709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"6.clkmgr_tl_intg_err.23469760520399810742380392553309800201020405784885465020032615855422835383155","seed":23469760520399810742380392553309800201020405784885465020032615855422835383155,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   8788077 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   8788077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"7.clkmgr_shadow_reg_errors_with_csr_rw.56948474662980197620004028270028928565066888401914009953852119881091182283533","seed":56948474662980197620004028270028928565066888401914009953852119881091182283533,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   7917695 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   7917695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"8.clkmgr_shadow_reg_errors_with_csr_rw.11482164025673543410201695561511691074117562047934685914261748734493013000924","seed":11482164025673543410201695561511691074117562047934685914261748734493013000924,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  17781944 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  17781944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"8.clkmgr_tl_intg_err.40701531232723869907697135166134993905759410700355512098396582161802537210950","seed":40701531232723869907697135166134993905759410700355512098396582161802537210950,"line":94,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  27040206 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  27040206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"8.clkmgr_csr_mem_rw_with_rand_reset.46430294986921497194258711547691860787935025644535263644106029774110151428018","seed":46430294986921497194258711547691860787935025644535263644106029774110151428018,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  14308272 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  14308272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"9.clkmgr_tl_intg_err.99635430660391163009485717086856100234440678556811735823731407974160062500558","seed":99635430660391163009485717086856100234440678556811735823731407974160062500558,"line":86,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  92605585 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  92605585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"9.clkmgr_csr_mem_rw_with_rand_reset.32237739986925554737812140740152227162806159486829830000065318185002781211392","seed":32237739986925554737812140740152227162806159486829830000065318185002781211392,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  23929426 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  23929426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"10.clkmgr_shadow_reg_errors_with_csr_rw.66780983592065058455872190428429885771284614581389766030662602642598673586014","seed":66780983592065058455872190428429885771284614581389766030662602642598673586014,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  40769516 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  40769516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"10.clkmgr_csr_mem_rw_with_rand_reset.88650669812537423498119338972710420635202382023125984059694101327071166138620","seed":88650669812537423498119338972710420635202382023125984059694101327071166138620,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  60034792 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  60034792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"11.clkmgr_tl_intg_err.81289976513775796886411688385575903448359470886830761592997215666959987641131","seed":81289976513775796886411688385575903448359470886830761592997215666959987641131,"line":89,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  28585105 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  28585105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"12.clkmgr_shadow_reg_errors_with_csr_rw.74483772484028709512570868108355703308707847968196662711039209001071912496490","seed":74483772484028709512570868108355703308707847968196662711039209001071912496490,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   4432783 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   4432783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"12.clkmgr_csr_rw.10063788853340038761849060369431563353334628255789057351161059886276704724367","seed":10063788853340038761849060369431563353334628255789057351161059886276704724367,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2756670 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2756670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"12.clkmgr_csr_mem_rw_with_rand_reset.63291930227161300941735671604775295090282202348471192115928481213503566535202","seed":63291930227161300941735671604775295090282202348471192115928481213503566535202,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  12512675 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  12512675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"13.clkmgr_shadow_reg_errors_with_csr_rw.75562885237235124510011605547206240044487002393510320472030848810957455350911","seed":75562885237235124510011605547206240044487002393510320472030848810957455350911,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  24754137 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  24754137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"14.clkmgr_tl_intg_err.8005799220873506593560070992552395002876207220634745505767481640809819267038","seed":8005799220873506593560070992552395002876207220634745505767481640809819267038,"line":90,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  18833253 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  18833253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"14.clkmgr_csr_rw.30164726865488346696722571260757964946491977889463215417042597225908702271084","seed":30164726865488346696722571260757964946491977889463215417042597225908702271084,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3604178 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   3604178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"15.clkmgr_tl_intg_err.2887994787230726818870210977253869193504731096972875713861031790179147641246","seed":2887994787230726818870210977253869193504731096972875713861031790179147641246,"line":85,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   9497478 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   9497478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"15.clkmgr_csr_mem_rw_with_rand_reset.86593345533275402954093980629082764470811766573932308471106263608876857432793","seed":86593345533275402954093980629082764470811766573932308471106263608876857432793,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   4942920 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   4942920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"16.clkmgr_shadow_reg_errors_with_csr_rw.89774682401278692374907176685127530033604309144302839965448467558626439590980","seed":89774682401278692374907176685127530033604309144302839965448467558626439590980,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   5827424 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   5827424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"16.clkmgr_tl_intg_err.18940264399762889332400514373753782790073756615600243997499993417024726297319","seed":18940264399762889332400514373753782790073756615600243997499993417024726297319,"line":101,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  14352195 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  14352195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"17.clkmgr_shadow_reg_errors_with_csr_rw.17096860233067395682720456247318335198051079806226024210103696547133554491992","seed":17096860233067395682720456247318335198051079806226024210103696547133554491992,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  10356902 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  10356902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"17.clkmgr_tl_intg_err.3690925673216159856156946643778018136249022459172530773499248411406899385883","seed":3690925673216159856156946643778018136249022459172530773499248411406899385883,"line":98,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  16047941 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  16047941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"17.clkmgr_csr_mem_rw_with_rand_reset.58799547175514175205430410056713423212451176256110900901428254037620250165546","seed":58799547175514175205430410056713423212451176256110900901428254037620250165546,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   6406683 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   6406683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"18.clkmgr_csr_rw.68445729895642440815332818517251981365723828040321697670560225611002389897456","seed":68445729895642440815332818517251981365723828040321697670560225611002389897456,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3047842 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   3047842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"19.clkmgr_csr_mem_rw_with_rand_reset.23071212985870107603470843270193171772311876910898036612111166063712090346395","seed":23071212985870107603470843270193171772311876910898036612111166063712090346395,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  13667063 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  13667063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *":[{"name":"clkmgr_csr_bit_bash","qual_name":"0.clkmgr_csr_bit_bash.72053922609975871753778524855940589631788201080730716897697235460809402086184","seed":72053922609975871753778524855940589631788201080730716897697235460809402086184,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @  36939803 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @  36939803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_bit_bash","qual_name":"1.clkmgr_csr_bit_bash.91716770845471101083796574299672565979403071759689302957840430291917015141222","seed":91716770845471101083796574299672565979403071759689302957840430291917015141222,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @ 126622130 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @ 126622130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_bit_bash","qual_name":"2.clkmgr_csr_bit_bash.96105139148606826848166782552236721538047268310922904819035840476038558552662","seed":96105139148606826848166782552236721538047268310922904819035840476038558552662,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @ 169945221 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @ 169945221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_bit_bash","qual_name":"3.clkmgr_csr_bit_bash.57662199148368099498725435747262855114278438307870923212616804447517428212540","seed":57662199148368099498725435747262855114278438307870923212616804447517428212540,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @  86102643 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @  86102643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_bit_bash","qual_name":"4.clkmgr_csr_bit_bash.94172147034507729234335041213690744062163427116637165728923425731674319605565","seed":94172147034507729234335041213690744062163427116637165728923425731674319605565,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @  35377010 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @  35377010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch":[{"name":"clkmgr_same_csr_outstanding","qual_name":"0.clkmgr_same_csr_outstanding.7412526796275225743014317698576273059742678472967577535691283114026909857356","seed":7412526796275225743014317698576273059742678472967577535691283114026909857356,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   8965674 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xf4dcde64 read out mismatch\n","UVM_INFO @   8965674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"1.clkmgr_same_csr_outstanding.78598676400245926038332957790192026850044841136893435412636942747977070149556","seed":78598676400245926038332957790192026850044841136893435412636942747977070149556,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  61318478 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x73e06364 read out mismatch\n","UVM_INFO @  61318478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"2.clkmgr_same_csr_outstanding.69092789515728570524986284360874557152225963071081478427644488094961823365946","seed":69092789515728570524986284360874557152225963071081478427644488094961823365946,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   9959233 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xbe74ace4 read out mismatch\n","UVM_INFO @   9959233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"3.clkmgr_same_csr_outstanding.32036830008165772464910340279715859500486780687841225913645252638308160302552","seed":32036830008165772464910340279715859500486780687841225913645252638308160302552,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   4592537 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xaeeec1a4 read out mismatch\n","UVM_INFO @   4592537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"4.clkmgr_same_csr_outstanding.11140718910353680325784784243231054767258935427219206753015066834876456386844","seed":11140718910353680325784784243231054767258935427219206753015066834876456386844,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  56899374 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xd914fca4 read out mismatch\n","UVM_INFO @  56899374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"5.clkmgr_same_csr_outstanding.62074978152394320678102704433742140853170304755228591527384445508738721945015","seed":62074978152394320678102704433742140853170304755228591527384445508738721945015,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   4624822 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x82fe3b24 read out mismatch\n","UVM_INFO @   4624822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"6.clkmgr_same_csr_outstanding.97713541313203547183903026408928568986532625359209823092678342836570333925991","seed":97713541313203547183903026408928568986532625359209823092678342836570333925991,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  13130785 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x22d1fc64 read out mismatch\n","UVM_INFO @  13130785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"7.clkmgr_same_csr_outstanding.115284222381641801666702627158067894811209958922624425470332058361795477478670","seed":115284222381641801666702627158067894811209958922624425470332058361795477478670,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   3840316 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xdfbfd3e4 read out mismatch\n","UVM_INFO @   3840316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"8.clkmgr_same_csr_outstanding.26018856965833389730878997215399727818593943963478170608938840108476389668765","seed":26018856965833389730878997215399727818593943963478170608938840108476389668765,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  16531587 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x3e9998e4 read out mismatch\n","UVM_INFO @  16531587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"9.clkmgr_same_csr_outstanding.33335267201597543330039262191813864141193468920456495093685154539919131433793","seed":33335267201597543330039262191813864141193468920456495093685154539919131433793,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  14945470 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xb9713124 read out mismatch\n","UVM_INFO @  14945470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"10.clkmgr_same_csr_outstanding.75847464200363327233743695596749218378604859058931998127554944493828330899788","seed":75847464200363327233743695596749218378604859058931998127554944493828330899788,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   8172826 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x53958c64 read out mismatch\n","UVM_INFO @   8172826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"11.clkmgr_same_csr_outstanding.108102379823790329089056978192657836805470349207558880687021687922442274048591","seed":108102379823790329089056978192657836805470349207558880687021687922442274048591,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  37615274 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x5966baa4 read out mismatch\n","UVM_INFO @  37615274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"12.clkmgr_same_csr_outstanding.38503147955285715790449316130199944732195748505765515742753886918594541810364","seed":38503147955285715790449316130199944732195748505765515742753886918594541810364,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   3773312 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xad3e01e4 read out mismatch\n","UVM_INFO @   3773312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"13.clkmgr_same_csr_outstanding.21634290107610949099147859377407211461449480867708555461768019347469253755092","seed":21634290107610949099147859377407211461449480867708555461768019347469253755092,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   3024993 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x2a418b24 read out mismatch\n","UVM_INFO @   3024993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"14.clkmgr_same_csr_outstanding.55390115356693485354201191142212552966760804599616677389157826090843592846554","seed":55390115356693485354201191142212552966760804599616677389157826090843592846554,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  13360423 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x608e7e24 read out mismatch\n","UVM_INFO @  13360423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"15.clkmgr_same_csr_outstanding.75333241348374197293621164642824550724007763068142114725774035210444532275475","seed":75333241348374197293621164642824550724007763068142114725774035210444532275475,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   6143131 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x6f41b9e4 read out mismatch\n","UVM_INFO @   6143131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"16.clkmgr_same_csr_outstanding.62627285050464222245431412083230385157820850261086611582163419719200678230021","seed":62627285050464222245431412083230385157820850261086611582163419719200678230021,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  11059479 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xbfd04da4 read out mismatch\n","UVM_INFO @  11059479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"17.clkmgr_same_csr_outstanding.17642503461167670870093245859351994970469733263179371856781335089414969072298","seed":17642503461167670870093245859351994970469733263179371856781335089414969072298,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   4575914 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x1a2c8064 read out mismatch\n","UVM_INFO @   4575914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"18.clkmgr_same_csr_outstanding.8965985867781228691985380546125256186375035911856947399947472137685865237990","seed":8965985867781228691985380546125256186375035911856947399947472137685865237990,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   4938773 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xa8d817a4 read out mismatch\n","UVM_INFO @   4938773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"19.clkmgr_same_csr_outstanding.84641676266845706217651739349582655394665292712703978199923554291930050552914","seed":84641676266845706217651739349582655394665292712703978199923554291930050552914,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   6044404 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x771a08a4 read out mismatch\n","UVM_INFO @   6044404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *":[{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"1.clkmgr_shadow_reg_errors_with_csr_rw.100595927093936565913245932816142789043120610821513798668902468050291901123887","seed":100595927093936565913245932816142789043120610821513798668902468050291901123887,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   9843327 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   9843327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"1.clkmgr_tl_intg_err.9931834353871381063320268540134766021775147829634619397340970290306652138241","seed":9931834353871381063320268540134766021775147829634619397340970290306652138241,"line":105,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @ 113325966 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @ 113325966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_aliasing","qual_name":"1.clkmgr_csr_aliasing.6522602195865478804008543265359335069561639686458571928485732190380482275540","seed":6522602195865478804008543265359335069561639686458571928485732190380482275540,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_csr_aliasing/latest/run.log","log_context":["UVM_ERROR @   3991115 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   3991115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"2.clkmgr_shadow_reg_errors_with_csr_rw.60942901299840335644182282195540702603167969798513046166111401737229844058608","seed":60942901299840335644182282195540702603167969798513046166111401737229844058608,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3605441 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   3605441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_aliasing","qual_name":"2.clkmgr_csr_aliasing.97621103741155479437346628478326064419596587487498118074749514965820774762905","seed":97621103741155479437346628478326064419596587487498118074749514965820774762905,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_csr_aliasing/latest/run.log","log_context":["UVM_ERROR @   6046461 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   6046461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"2.clkmgr_csr_mem_rw_with_rand_reset.72180852702607984861397186786159669842394112327138645830709044568958962819706","seed":72180852702607984861397186786159669842394112327138645830709044568958962819706,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   3169941 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   3169941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_aliasing","qual_name":"3.clkmgr_csr_aliasing.107256194682480076812917146527468208332421097758827610120075225783300624275304","seed":107256194682480076812917146527468208332421097758827610120075225783300624275304,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_csr_aliasing/latest/run.log","log_context":["UVM_ERROR @  10589773 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  10589773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"4.clkmgr_shadow_reg_errors_with_csr_rw.48992616875871909203050492723573421937707643842459426453895635456237182153901","seed":48992616875871909203050492723573421937707643842459426453895635456237182153901,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2750215 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   2750215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"4.clkmgr_csr_rw.108248514123728927942170414621906033568836375422127648418122771863093578126075","seed":108248514123728927942170414621906033568836375422127648418122771863093578126075,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   7220878 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   7220878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_aliasing","qual_name":"4.clkmgr_csr_aliasing.73405122990842278136188139330357235692282049034257128951396240289877499216939","seed":73405122990842278136188139330357235692282049034257128951396240289877499216939,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_csr_aliasing/latest/run.log","log_context":["UVM_ERROR @  23375326 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  23375326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"5.clkmgr_tl_intg_err.43759035967184338194884982040014485959885165239125899388427370417316360333174","seed":43759035967184338194884982040014485959885165239125899388427370417316360333174,"line":91,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  13026977 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  13026977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"6.clkmgr_csr_rw.51172645926508966125669560914805703904064087654833452293180853669954523316306","seed":51172645926508966125669560914805703904064087654833452293180853669954523316306,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   1391753 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   1391753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"6.clkmgr_csr_mem_rw_with_rand_reset.34267987081520691381057974872647063908663591288603424136585230977078775736384","seed":34267987081520691381057974872647063908663591288603424136585230977078775736384,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  60981835 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  60981835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"7.clkmgr_tl_intg_err.15547009452539514233417288403283333518611217513197012244155770981859818289808","seed":15547009452539514233417288403283333518611217513197012244155770981859818289808,"line":85,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  22002727 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  22002727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"7.clkmgr_csr_rw.49379907387899708009987572405962722065897814924366941405275267341220546345595","seed":49379907387899708009987572405962722065897814924366941405275267341220546345595,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   1756948 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   1756948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"7.clkmgr_csr_mem_rw_with_rand_reset.37194483188570796372108421512472893991142839964866671189234251962568067078918","seed":37194483188570796372108421512472893991142839964866671189234251962568067078918,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  26197598 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  26197598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"8.clkmgr_csr_rw.38715661419714415540694925381267140979651507372399901913807699933110400789090","seed":38715661419714415540694925381267140979651507372399901913807699933110400789090,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @  26873520 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  26873520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"9.clkmgr_shadow_reg_errors_with_csr_rw.102268523354763403856662966845246448705639124347443300326460272295012162272408","seed":102268523354763403856662966845246448705639124347443300326460272295012162272408,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2276773 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   2276773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"9.clkmgr_csr_rw.86305389646292354823759937591572237123926535254065961065773217121155780092520","seed":86305389646292354823759937591572237123926535254065961065773217121155780092520,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @  13756926 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  13756926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"10.clkmgr_tl_intg_err.66852923398446124882464268774982887524211307010624231254132177441255338192602","seed":66852923398446124882464268774982887524211307010624231254132177441255338192602,"line":85,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  13336206 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  13336206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"11.clkmgr_shadow_reg_errors_with_csr_rw.60906477415222762916477974494642373007386237281526929177313239912607078049216","seed":60906477415222762916477974494642373007386237281526929177313239912607078049216,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   5327478 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   5327478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"11.clkmgr_csr_mem_rw_with_rand_reset.30643822230150722675808880023471514229211231602697899012161480956849222861907","seed":30643822230150722675808880023471514229211231602697899012161480956849222861907,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   6842035 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   6842035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"12.clkmgr_tl_intg_err.16033060058043749581401162608238862327264771063457754871717048707381060680553","seed":16033060058043749581401162608238862327264771063457754871717048707381060680553,"line":85,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   9999637 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   9999637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"13.clkmgr_tl_intg_err.112416867938398886153864230329654010321213928581233248386040446508126224536589","seed":112416867938398886153864230329654010321213928581233248386040446508126224536589,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   2141638 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   2141638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"14.clkmgr_shadow_reg_errors_with_csr_rw.110776067297559249755964101954037364906398422425044855135836171123146102146471","seed":110776067297559249755964101954037364906398422425044855135836171123146102146471,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   6309665 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   6309665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"15.clkmgr_shadow_reg_errors_with_csr_rw.12034288644245460820761427014644308978590479004934653040336508553712660922138","seed":12034288644245460820761427014644308978590479004934653040336508553712660922138,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  21402455 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  21402455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"15.clkmgr_csr_rw.54482652205824034140261361797549439784614298675155776943387110460696213810215","seed":54482652205824034140261361797549439784614298675155776943387110460696213810215,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   4816151 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   4816151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"16.clkmgr_csr_rw.67523072663633733459055867237910885390567881134730278670771938117380730756390","seed":67523072663633733459055867237910885390567881134730278670771938117380730756390,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @  20104851 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  20104851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"17.clkmgr_csr_rw.23816378680226375402763775338464400685806636468691315354841624911124119697134","seed":23816378680226375402763775338464400685806636468691315354841624911124119697134,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   5556937 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   5556937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"18.clkmgr_shadow_reg_errors_with_csr_rw.68378593979365999185313824495454469162349029847674492964684854151444557383271","seed":68378593979365999185313824495454469162349029847674492964684854151444557383271,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   6383520 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   6383520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"18.clkmgr_tl_intg_err.1964611305507724641495446114035396416648947582972802266089114629546894303072","seed":1964611305507724641495446114035396416648947582972802266089114629546894303072,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   8094015 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   8094015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"18.clkmgr_csr_mem_rw_with_rand_reset.94108405636357068376154951065289724584156743201231098597023461645799528674794","seed":94108405636357068376154951065289724584156743201231098597023461645799528674794,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  10307940 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  10307940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"19.clkmgr_shadow_reg_errors_with_csr_rw.3908942448773391617188822366493132689663284139635931155143824299646199499388","seed":3908942448773391617188822366493132689663284139635931155143824299646199499388,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   5250023 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   5250023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"19.clkmgr_tl_intg_err.100379496771661467304919751859620528860592707065177996049648129228037138334063","seed":100379496771661467304919751859620528860592707065177996049648129228037138334063,"line":83,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   5638883 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   5638883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*":[{"name":"clkmgr_frequency","qual_name":"0.clkmgr_frequency.58043360112389079902563742398575524620974963456902678619757503055768543305559","seed":58043360112389079902563742398575524620974963456902678619757503055768543305559,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  11701686 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  11701686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"0.clkmgr_stress_all_with_rand_reset.87051315591977005959289102573319184527886741808404148360784588765743452480447","seed":87051315591977005959289102573319184527886741808404148360784588765743452480447,"line":102,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 174346617 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 174346617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"1.clkmgr_frequency.28470502682153512743327578276381195469414695665581994913184444392743697571732","seed":28470502682153512743327578276381195469414695665581994913184444392743697571732,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6564993 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6564993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"1.clkmgr_stress_all.11742578808654286192497775034417720812179191867152049354864275075181061322220","seed":11742578808654286192497775034417720812179191867152049354864275075181061322220,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  81168813 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  81168813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"2.clkmgr_frequency.3355749371521075100526809140045531402854071444232853435165239928227836554385","seed":3355749371521075100526809140045531402854071444232853435165239928227836554385,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   9292575 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   9292575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"3.clkmgr_frequency.7682632965489457372792763055989093585017783045375302884923346202523046752204","seed":7682632965489457372792763055989093585017783045375302884923346202523046752204,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6411705 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6411705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"4.clkmgr_frequency.83617330590568042330338943971093344503083696891246152894337293230258981354979","seed":83617330590568042330338943971093344503083696891246152894337293230258981354979,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5121399 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5121399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"4.clkmgr_stress_all_with_rand_reset.75886271636860381292877741993688026311913307731480514724377318393139711927626","seed":75886271636860381292877741993688026311913307731480514724377318393139711927626,"line":134,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 431284424 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 431284424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"4.clkmgr_stress_all.78576799654226225993188345547515747906027033064451575043775937692967546510344","seed":78576799654226225993188345547515747906027033064451575043775937692967546510344,"line":144,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  57039650 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  57039650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"5.clkmgr_frequency.92094299222101206607223339589311750474182356533644966396521951898098104195650","seed":92094299222101206607223339589311750474182356533644966396521951898098104195650,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5600148 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5600148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"5.clkmgr_stress_all_with_rand_reset.38755286312397772072331470209406913833396792921879130662552899786354432062237","seed":38755286312397772072331470209406913833396792921879130662552899786354432062237,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   6653254 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6653254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"6.clkmgr_frequency.47167722738907729336359680359266214277072001071339012118029825376083475306237","seed":47167722738907729336359680359266214277072001071339012118029825376083475306237,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  17439879 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  17439879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"6.clkmgr_stress_all_with_rand_reset.34687852525599832883095485573286563737553409479372489327482462739384526122667","seed":34687852525599832883095485573286563737553409479372489327482462739384526122667,"line":175,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  52310675 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  52310675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"7.clkmgr_frequency.103651422222133348480756617710311944980329569558320788372867938398419498504833","seed":103651422222133348480756617710311944980329569558320788372867938398419498504833,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   8991165 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   8991165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"7.clkmgr_stress_all_with_rand_reset.34414517856202216115836348069230958445620530847585496958769930817291861392584","seed":34414517856202216115836348069230958445620530847585496958769930817291861392584,"line":170,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 158257584 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 158257584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"7.clkmgr_stress_all.105797031668373907234341392612730359930591991665180108136845050795992224978009","seed":105797031668373907234341392612730359930591991665180108136845050795992224978009,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  11857691 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  11857691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"8.clkmgr_frequency.4207247140662692697940601010894661306140828126403471289642158795906257741039","seed":4207247140662692697940601010894661306140828126403471289642158795906257741039,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4117024 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4117024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"8.clkmgr_stress_all.93442762590560519232530765021472407139952649191607855320115641918285412878895","seed":93442762590560519232530765021472407139952649191607855320115641918285412878895,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  14004797 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  14004797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"9.clkmgr_frequency.16065935970473723041931173051999571128215105958729669291742096028688965128890","seed":16065935970473723041931173051999571128215105958729669291742096028688965128890,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  35196686 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  35196686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"9.clkmgr_stress_all_with_rand_reset.21121551745887990705497470040224798214828807319707358631295345051999643433530","seed":21121551745887990705497470040224798214828807319707358631295345051999643433530,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  12682911 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  12682911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"10.clkmgr_frequency.80344281794213343880242456439089635945874182010423121598119661192947038063637","seed":80344281794213343880242456439089635945874182010423121598119661192947038063637,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  20278866 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  20278866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"10.clkmgr_stress_all_with_rand_reset.96769821477335833490531872440764727142330145714405777290342995290267990369911","seed":96769821477335833490531872440764727142330145714405777290342995290267990369911,"line":96,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 778349794 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 778349794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"11.clkmgr_stress_all_with_rand_reset.21554483488283304081572882688984021103665297198147866792894509053565632430853","seed":21554483488283304081572882688984021103665297198147866792894509053565632430853,"line":205,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1721153240 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 1721153240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"11.clkmgr_stress_all.99968345005650173229231282969990493198271499676999224432951228593713284720158","seed":99968345005650173229231282969990493198271499676999224432951228593713284720158,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  86704028 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  86704028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"12.clkmgr_frequency.96345537510470860939946695910003204189378656533482205778300468717733544471697","seed":96345537510470860939946695910003204189378656533482205778300468717733544471697,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  17713638 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  17713638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"12.clkmgr_stress_all_with_rand_reset.46899341471458301195479077085751102284820165517992407334532620368935828065448","seed":46899341471458301195479077085751102284820165517992407334532620368935828065448,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  87568190 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  87568190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"13.clkmgr_frequency.77471690880862294964045419143209951603084053596834307335903865022530723994049","seed":77471690880862294964045419143209951603084053596834307335903865022530723994049,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7152636 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7152636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"14.clkmgr_frequency.50702926576634733881011268946589140854648990217279061189909616629361568789277","seed":50702926576634733881011268946589140854648990217279061189909616629361568789277,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  11657960 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  11657960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"14.clkmgr_stress_all_with_rand_reset.5737642882610084709104284616141218728219913154072914264678866823035094370681","seed":5737642882610084709104284616141218728219913154072914264678866823035094370681,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  12909403 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  12909403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"14.clkmgr_stress_all.59133147509460027118820057898829506070893539814748757791480731751800841312604","seed":59133147509460027118820057898829506070893539814748757791480731751800841312604,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  55390544 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  55390544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"15.clkmgr_frequency.24443127799828598034106692741410870932754379320378427757785661729841129376740","seed":24443127799828598034106692741410870932754379320378427757785661729841129376740,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  19765870 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  19765870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"15.clkmgr_stress_all_with_rand_reset.79784828113827713336903198713969412107427463213229317913384627608803160399063","seed":79784828113827713336903198713969412107427463213229317913384627608803160399063,"line":90,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  19379983 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  19379983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"16.clkmgr_frequency.37898078084189999868047332688203131352822981906864778952321159615348368197449","seed":37898078084189999868047332688203131352822981906864778952321159615348368197449,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4828344 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4828344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"16.clkmgr_stress_all.99138304731428368623816269620261185737558304190899726608708275385792172316597","seed":99138304731428368623816269620261185737558304190899726608708275385792172316597,"line":118,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  45670525 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  45670525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"17.clkmgr_frequency.108409957190521920771994681102136198091834530684797005860159172569745126007548","seed":108409957190521920771994681102136198091834530684797005860159172569745126007548,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  14900736 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  14900736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"17.clkmgr_stress_all_with_rand_reset.69539501827566371900366425728691185896296901066667462931279357298715520521191","seed":69539501827566371900366425728691185896296901066667462931279357298715520521191,"line":130,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 370636161 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 370636161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"17.clkmgr_stress_all.14870972422381566970855688650291169777498482370832279007729364137927313530445","seed":14870972422381566970855688650291169777498482370832279007729364137927313530445,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   7095037 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7095037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"18.clkmgr_frequency.33252819370326476354638475090474355776976459047717783917785629421894827708854","seed":33252819370326476354638475090474355776976459047717783917785629421894827708854,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   8376183 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8376183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"19.clkmgr_frequency.11345320494807027055548231216825556815146395058907176000960110930115231274153","seed":11345320494807027055548231216825556815146395058907176000960110930115231274153,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7345203 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7345203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"20.clkmgr_frequency.55914564435871710171437725127345289243811574147691521635760219913981490570747","seed":55914564435871710171437725127345289243811574147691521635760219913981490570747,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5053103 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5053103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"20.clkmgr_stress_all.86058145798316125457500306640419677650377583008806455241702481930900286673877","seed":86058145798316125457500306640419677650377583008806455241702481930900286673877,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   9481666 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   9481666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"21.clkmgr_frequency.95611603939887881591910826563319177276024422457892240564637805624242486743314","seed":95611603939887881591910826563319177276024422457892240564637805624242486743314,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   9532477 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   9532477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"22.clkmgr_frequency.21211732617989152299174841920234733375126147537360218321578873736834148431529","seed":21211732617989152299174841920234733375126147537360218321578873736834148431529,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  21580740 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  21580740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"22.clkmgr_stress_all_with_rand_reset.71739835543253728240009007419691364518310085065893065233889172744263553810824","seed":71739835543253728240009007419691364518310085065893065233889172744263553810824,"line":107,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 134621215 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 134621215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"23.clkmgr_frequency.49914770389772419551930304119398960029584120492926680990922305257999199767096","seed":49914770389772419551930304119398960029584120492926680990922305257999199767096,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  11797621 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  11797621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"23.clkmgr_stress_all_with_rand_reset.69985385947404314535164748022317537561377608201940115642816257300128784653618","seed":69985385947404314535164748022317537561377608201940115642816257300128784653618,"line":106,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 120835244 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 120835244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"24.clkmgr_frequency.87227886564039264202884862088454165131478754797626861337246526686060944403523","seed":87227886564039264202884862088454165131478754797626861337246526686060944403523,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  11661607 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  11661607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"24.clkmgr_stress_all.45703784350092693137833111048564375061748737045282113685992979163865604304762","seed":45703784350092693137833111048564375061748737045282113685992979163865604304762,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  31605756 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  31605756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"25.clkmgr_frequency.23897273927055366593722152054803264905817272594710356264884729507062513085615","seed":23897273927055366593722152054803264905817272594710356264884729507062513085615,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   8796833 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   8796833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"25.clkmgr_stress_all.31725588541483650529592681474649350861663752300550770238388570593140235908127","seed":31725588541483650529592681474649350861663752300550770238388570593140235908127,"line":88,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  56067468 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  56067468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"26.clkmgr_frequency.64891743308326864730358675042648508730432160897950519086991104778710962423512","seed":64891743308326864730358675042648508730432160897950519086991104778710962423512,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   8974324 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   8974324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"26.clkmgr_stress_all_with_rand_reset.91865957939762467069882045480927092598011996546101014426739582248669201608990","seed":91865957939762467069882045480927092598011996546101014426739582248669201608990,"line":87,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1786051792 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 1786051792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"27.clkmgr_frequency.29490370256251424927507859100451577460688979510614661732338033706465901187868","seed":29490370256251424927507859100451577460688979510614661732338033706465901187868,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  11480142 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  11480142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"28.clkmgr_frequency.42543720494249332209146676288745292097964760158369519293708144353850702064275","seed":42543720494249332209146676288745292097964760158369519293708144353850702064275,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/28.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  12281281 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  12281281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"29.clkmgr_frequency.100921063654363007446060375360202074761343952000887409619563510537940688613203","seed":100921063654363007446060375360202074761343952000887409619563510537940688613203,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   9607556 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   9607556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"30.clkmgr_frequency.21920261082858612508500468527738944019011109544031314858538288783451353437797","seed":21920261082858612508500468527738944019011109544031314858538288783451353437797,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   9785832 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   9785832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"31.clkmgr_frequency.86857298274322885431183867402092265859727802894356420352160928531738476827487","seed":86857298274322885431183867402092265859727802894356420352160928531738476827487,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6521710 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6521710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"32.clkmgr_frequency.62087958357032585561742400255723274083181873873408966889107656044879948395853","seed":62087958357032585561742400255723274083181873873408966889107656044879948395853,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  12358805 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  12358805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"33.clkmgr_frequency.58562442107241228148307363725132809693985218611405027010477503194992281365300","seed":58562442107241228148307363725132809693985218611405027010477503194992281365300,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6790044 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6790044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"33.clkmgr_stress_all_with_rand_reset.14475182920507603069506907333283959001847459707026002442115242251109458273114","seed":14475182920507603069506907333283959001847459707026002442115242251109458273114,"line":86,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 306033144 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 306033144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"34.clkmgr_frequency.37212586552156240465716685276621095156644425377430866362584955314302819901600","seed":37212586552156240465716685276621095156644425377430866362584955314302819901600,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4471790 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4471790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"34.clkmgr_stress_all_with_rand_reset.14418460246228072049732752905783879508139145567213173022408296006171889331978","seed":14418460246228072049732752905783879508139145567213173022408296006171889331978,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  19860772 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  19860772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"35.clkmgr_frequency.79569931915287002082834507859292570097836756762005608099043670207158256739957","seed":79569931915287002082834507859292570097836756762005608099043670207158256739957,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7933442 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7933442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"35.clkmgr_stress_all_with_rand_reset.23454781212554423976389689580953264127430538313189611625447078302629497872450","seed":23454781212554423976389689580953264127430538313189611625447078302629497872450,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  17915893 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  17915893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"36.clkmgr_frequency.68451420888282305826976742508499564440127325865440490844013028579192985944626","seed":68451420888282305826976742508499564440127325865440490844013028579192985944626,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7472454 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7472454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"37.clkmgr_frequency.56229730925088897405162188850213627486905258767472714716434041970596279835557","seed":56229730925088897405162188850213627486905258767472714716434041970596279835557,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  20662601 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  20662601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"37.clkmgr_stress_all.110582348393063163258881492502752356523607327355568573299161038998675522528773","seed":110582348393063163258881492502752356523607327355568573299161038998675522528773,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   7467528 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7467528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"38.clkmgr_frequency.37232118157811317425481710761486992971014396401241981423046816634142235923081","seed":37232118157811317425481710761486992971014396401241981423046816634142235923081,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  13560584 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  13560584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"38.clkmgr_stress_all_with_rand_reset.109452065331470709121091059443250237922714603868352139310861570325453346043035","seed":109452065331470709121091059443250237922714603868352139310861570325453346043035,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  62430441 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  62430441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"39.clkmgr_frequency.26976502752179471167499453019777209910565238044582002327457740647081820407401","seed":26976502752179471167499453019777209910565238044582002327457740647081820407401,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   8856250 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   8856250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"39.clkmgr_stress_all.40647768160607243814231583576263992710936182730073271636897738005234821912346","seed":40647768160607243814231583576263992710936182730073271636897738005234821912346,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 105315630 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 105315630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"40.clkmgr_frequency.89546343943716300636223433376818219421489256806372491938628458810090592183840","seed":89546343943716300636223433376818219421489256806372491938628458810090592183840,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4507483 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4507483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"40.clkmgr_stress_all_with_rand_reset.64293580855506178121326246765742233189622660898709440849739753282366364010751","seed":64293580855506178121326246765742233189622660898709440849739753282366364010751,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   9536222 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   9536222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"41.clkmgr_frequency.83487495881094576374675047053393726347632495685751415964175904179727177377936","seed":83487495881094576374675047053393726347632495685751415964175904179727177377936,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   9763584 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   9763584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"41.clkmgr_stress_all_with_rand_reset.37015421786958304772610160404660904639670726462918992420590873498264532882110","seed":37015421786958304772610160404660904639670726462918992420590873498264532882110,"line":112,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 405922446 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 405922446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"41.clkmgr_stress_all.67239514955116157379855253251947385804097007467258430244715291531324064133237","seed":67239514955116157379855253251947385804097007467258430244715291531324064133237,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  33598433 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  33598433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"42.clkmgr_frequency.58825602105190530115929212109847860864894012453775702400828950934517794369252","seed":58825602105190530115929212109847860864894012453775702400828950934517794369252,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6397623 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6397623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"42.clkmgr_stress_all.60416990802416220931976645641577233025222723525843957584939920148941871299864","seed":60416990802416220931976645641577233025222723525843957584939920148941871299864,"line":136,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  73444322 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  73444322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"43.clkmgr_frequency.84792204746640405827682181725799612897209873969729109650978065762601560627627","seed":84792204746640405827682181725799612897209873969729109650978065762601560627627,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   9046124 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   9046124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"43.clkmgr_stress_all.94250230080040371022529931864137549413541794055409500659136445847908876495796","seed":94250230080040371022529931864137549413541794055409500659136445847908876495796,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   7928296 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7928296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"44.clkmgr_frequency.73794410572620349212510109786659918186091007621234139321557477434646567606419","seed":73794410572620349212510109786659918186091007621234139321557477434646567606419,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   9994362 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   9994362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"44.clkmgr_stress_all_with_rand_reset.88404676608994642293292562131345408117428334452997751811805367083915314735146","seed":88404676608994642293292562131345408117428334452997751811805367083915314735146,"line":182,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 773698825 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 773698825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"45.clkmgr_frequency.4947504847425058147689062707904023655827987790773269577146256435386252584252","seed":4947504847425058147689062707904023655827987790773269577146256435386252584252,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  12530788 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  12530788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"45.clkmgr_stress_all_with_rand_reset.89084394428353910114946376371364238259395009775141285206691292526617474807641","seed":89084394428353910114946376371364238259395009775141285206691292526617474807641,"line":148,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1083563503 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 1083563503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"46.clkmgr_frequency.27980913896244689740660402038195410348396783300852203995989102583218763502694","seed":27980913896244689740660402038195410348396783300852203995989102583218763502694,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  13459334 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  13459334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"46.clkmgr_stress_all_with_rand_reset.13564171291048971478965091407994200105314782415005253351113185885277571299813","seed":13564171291048971478965091407994200105314782415005253351113185885277571299813,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  13477190 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  13477190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"47.clkmgr_frequency.1263678143960495328714836097133776767184548406968879694604960770176183891148","seed":1263678143960495328714836097133776767184548406968879694604960770176183891148,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6411554 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6411554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"47.clkmgr_stress_all.79873971727206217905451457111948665072690772947413338355847344514141899121067","seed":79873971727206217905451457111948665072690772947413338355847344514141899121067,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  21183610 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  21183610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"48.clkmgr_frequency.84938961451087371143985144208717522287473244568756532841318486628980797698902","seed":84938961451087371143985144208717522287473244568756532841318486628980797698902,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4052899 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4052899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"48.clkmgr_stress_all_with_rand_reset.56163096051391579444919167697431062093319530403864701254776755018746103295346","seed":56163096051391579444919167697431062093319530403864701254776755018746103295346,"line":133,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 339643451 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 339643451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"49.clkmgr_frequency.77052867351210468520275078712243006574985549335087081807748423917506291090162","seed":77052867351210468520275078712243006574985549335087081807748423917506291090162,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6266253 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6266253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*":[{"name":"clkmgr_frequency_timeout","qual_name":"0.clkmgr_frequency_timeout.43959270594847948533954449453029855226815873687296885182892582935491123824760","seed":43959270594847948533954449453029855226815873687296885182892582935491123824760,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6563979 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6563979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"0.clkmgr_stress_all.16179312685176157035199752174498622395526390774319777437649059438571809163564","seed":16179312685176157035199752174498622395526390774319777437649059438571809163564,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   3062947 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3062947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"1.clkmgr_frequency_timeout.53864495099245938508434673746437496236402415463500156772943504443396484036801","seed":53864495099245938508434673746437496236402415463500156772943504443396484036801,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   8923732 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8923732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"1.clkmgr_stress_all_with_rand_reset.115668852567933140377639973740823727137312013230126038892746856374560924245275","seed":115668852567933140377639973740823727137312013230126038892746856374560924245275,"line":207,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 134484167 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 134484167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"2.clkmgr_frequency_timeout.88168762761173507598707745815717764424506400935374039377903074723066980571232","seed":88168762761173507598707745815717764424506400935374039377903074723066980571232,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   8300131 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   8300131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"2.clkmgr_stress_all_with_rand_reset.21074241266596564936867769978108844456701906687911232454140168570841445417768","seed":21074241266596564936867769978108844456701906687911232454140168570841445417768,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  10573240 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  10573240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"2.clkmgr_stress_all.50655011320324095945779588405478880370642756920065376276932560376591511964875","seed":50655011320324095945779588405478880370642756920065376276932560376591511964875,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   9722904 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   9722904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"3.clkmgr_frequency_timeout.99931659851237526513211849436541973988646871186260700412122833682861827548298","seed":99931659851237526513211849436541973988646871186260700412122833682861827548298,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3185147 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3185147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"3.clkmgr_stress_all_with_rand_reset.31997715827379121175698775345047998829834475401172062300491495344852230015848","seed":31997715827379121175698775345047998829834475401172062300491495344852230015848,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  26290546 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  26290546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"3.clkmgr_stress_all.85037051557272858391709287799816517879635769857150016777385843612898719730283","seed":85037051557272858391709287799816517879635769857150016777385843612898719730283,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   5848870 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5848870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"4.clkmgr_frequency_timeout.64667433895831155954970465101783702205315418359859838711811135068049951879353","seed":64667433895831155954970465101783702205315418359859838711811135068049951879353,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5561999 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5561999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"5.clkmgr_frequency_timeout.3279766769734518915158328604213596767518311003402859277979251958102150710585","seed":3279766769734518915158328604213596767518311003402859277979251958102150710585,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5764755 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5764755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"5.clkmgr_stress_all.69357231862745860297131771672464397394066596216623243848024854756551384910242","seed":69357231862745860297131771672464397394066596216623243848024854756551384910242,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   5291301 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5291301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"6.clkmgr_frequency_timeout.44288711617008086351024766555901549605769544705624140487918817041751514366452","seed":44288711617008086351024766555901549605769544705624140487918817041751514366452,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6516614 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6516614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"6.clkmgr_stress_all.112072718984855802032540129837756455550870804502167049755667595093467500129227","seed":112072718984855802032540129837756455550870804502167049755667595093467500129227,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  45416317 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  45416317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"7.clkmgr_frequency_timeout.38075913132274376523826324474108129719760731478822440525502583087995615052374","seed":38075913132274376523826324474108129719760731478822440525502583087995615052374,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3394625 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3394625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"8.clkmgr_frequency_timeout.24130307578608555145769025508143650872904540538541284678617062733913521267566","seed":24130307578608555145769025508143650872904540538541284678617062733913521267566,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2191287 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2191287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"8.clkmgr_stress_all_with_rand_reset.61994474456648261194000132133249336711478037978832817340148346805531283280286","seed":61994474456648261194000132133249336711478037978832817340148346805531283280286,"line":131,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 156326400 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 156326400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"9.clkmgr_frequency_timeout.49218058893200292773645250500546961539539555388013994396117167146608239126162","seed":49218058893200292773645250500546961539539555388013994396117167146608239126162,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4739617 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4739617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"10.clkmgr_frequency_timeout.63475442405539068035504790536825722704544945030474382687025163701410177091408","seed":63475442405539068035504790536825722704544945030474382687025163701410177091408,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4823510 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4823510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"10.clkmgr_stress_all.24609637951513339822546574040049541725438969299100115544768098093173456619845","seed":24609637951513339822546574040049541725438969299100115544768098093173456619845,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   4449182 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4449182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"11.clkmgr_frequency_timeout.101558511831034634035675084030128821080794324023138640969772814625026937574877","seed":101558511831034634035675084030128821080794324023138640969772814625026937574877,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2128526 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2128526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"12.clkmgr_frequency_timeout.20338579895861016488728648905481722172291682853477058351200459687077539765442","seed":20338579895861016488728648905481722172291682853477058351200459687077539765442,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3504239 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3504239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"12.clkmgr_stress_all.100396197983860723491813406852185732522898213079214497651432593011749204306289","seed":100396197983860723491813406852185732522898213079214497651432593011749204306289,"line":150,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 603415166 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 603415166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"13.clkmgr_frequency_timeout.39949912101041998965051969738205495659157133103301814961392835520074761370040","seed":39949912101041998965051969738205495659157133103301814961392835520074761370040,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2596928 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2596928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"13.clkmgr_stress_all_with_rand_reset.63372129480999530048879401949673845890431765618253701885984929686804021983402","seed":63372129480999530048879401949673845890431765618253701885984929686804021983402,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  10539156 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  10539156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"13.clkmgr_stress_all.62919749392567484775203391781876919359145400273239926856685129132656533616529","seed":62919749392567484775203391781876919359145400273239926856685129132656533616529,"line":141,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 230384019 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 230384019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"14.clkmgr_frequency_timeout.48395944501951906379676141137586388641809208758374660240525376082306168587244","seed":48395944501951906379676141137586388641809208758374660240525376082306168587244,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4057966 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4057966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"15.clkmgr_frequency_timeout.106602697083099020526186232720720539326944583514990595563638667821332256010312","seed":106602697083099020526186232720720539326944583514990595563638667821332256010312,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6346683 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6346683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"15.clkmgr_stress_all.90362920583798464517967376170761093061931432117511004186798523935327483488322","seed":90362920583798464517967376170761093061931432117511004186798523935327483488322,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  46674801 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  46674801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"16.clkmgr_frequency_timeout.43362908983663485276658537617089141417713750759731885066593867026681398679764","seed":43362908983663485276658537617089141417713750759731885066593867026681398679764,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2393402 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2393402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"16.clkmgr_stress_all_with_rand_reset.45769147998614810221236640091296587261227016527409359953355369001808929473108","seed":45769147998614810221236640091296587261227016527409359953355369001808929473108,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  14733271 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  14733271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"17.clkmgr_frequency_timeout.75960984463890791489655688990807528568154587081763459286439964905615235178131","seed":75960984463890791489655688990807528568154587081763459286439964905615235178131,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2455071 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2455071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"18.clkmgr_frequency_timeout.79403304515037226068314323703278916082471726156203016727804708484857150083496","seed":79403304515037226068314323703278916082471726156203016727804708484857150083496,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4596411 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4596411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"18.clkmgr_stress_all_with_rand_reset.107201126995819158513346736837761715748218434540294143408388137826756794160435","seed":107201126995819158513346736837761715748218434540294143408388137826756794160435,"line":90,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 574607728 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 574607728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"18.clkmgr_stress_all.36675995671819186515742819564770213405814301210172321395832037569760088550341","seed":36675995671819186515742819564770213405814301210172321395832037569760088550341,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  12455030 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  12455030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"19.clkmgr_frequency_timeout.74457339434349755455111210883981589598338135289089494166471660065561603326621","seed":74457339434349755455111210883981589598338135289089494166471660065561603326621,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2348154 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2348154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"19.clkmgr_stress_all_with_rand_reset.80555115385952038704743365646975986028545631097331637415426664129849865221505","seed":80555115385952038704743365646975986028545631097331637415426664129849865221505,"line":85,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  23982280 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  23982280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"19.clkmgr_stress_all.102864288265892628114559486551046248076019007938332387920708257772957447701854","seed":102864288265892628114559486551046248076019007938332387920708257772957447701854,"line":81,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  59356074 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  59356074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"20.clkmgr_frequency_timeout.52170663846280771427993370630587763084046982525462827070202579342518825956482","seed":52170663846280771427993370630587763084046982525462827070202579342518825956482,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4799035 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4799035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"20.clkmgr_stress_all_with_rand_reset.2113671657936813933120860273249264420443786923412295004363128893432277904600","seed":2113671657936813933120860273249264420443786923412295004363128893432277904600,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   4717076 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4717076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"21.clkmgr_frequency_timeout.31362751451454865862049163346383386475923842208154514608482165559651140476513","seed":31362751451454865862049163346383386475923842208154514608482165559651140476513,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3711289 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3711289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"21.clkmgr_stress_all_with_rand_reset.87352837437143613670009783822018357924084008265701724519106552777679374274489","seed":87352837437143613670009783822018357924084008265701724519106552777679374274489,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  20179153 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  20179153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"22.clkmgr_frequency_timeout.41656102879798865842512597194736969722761535718275958126594324697318682037809","seed":41656102879798865842512597194736969722761535718275958126594324697318682037809,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   8093590 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8093590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"22.clkmgr_stress_all.7232314936124314018615991825979877040580553205385781212235503885803394659887","seed":7232314936124314018615991825979877040580553205385781212235503885803394659887,"line":146,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  23344036 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  23344036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"23.clkmgr_frequency_timeout.96554803161234176712708532626021269669005802081664913597666273352385908031968","seed":96554803161234176712708532626021269669005802081664913597666273352385908031968,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4939490 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4939490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"24.clkmgr_frequency_timeout.16417932305302063793404136409717965887183763071216041693646800848163851785048","seed":16417932305302063793404136409717965887183763071216041693646800848163851785048,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3724229 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3724229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"24.clkmgr_stress_all_with_rand_reset.52500984059492445275997354698727920940338723181658233774694349476934154230033","seed":52500984059492445275997354698727920940338723181658233774694349476934154230033,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  38595055 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  38595055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"25.clkmgr_frequency_timeout.98172716255943950401414096918570729312220715818355028060005273946149773833111","seed":98172716255943950401414096918570729312220715818355028060005273946149773833111,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3930900 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3930900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"25.clkmgr_stress_all_with_rand_reset.108763749015750453511570819364783394740165957825294659745291047811079374798278","seed":108763749015750453511570819364783394740165957825294659745291047811079374798278,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  18326368 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  18326368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"26.clkmgr_frequency_timeout.46801371528089655646623842260771533217426389901058022464918057808468978992579","seed":46801371528089655646623842260771533217426389901058022464918057808468978992579,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4423645 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4423645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"26.clkmgr_stress_all.41213477647736821986818008142843204386388181892822824380397568110430789037287","seed":41213477647736821986818008142843204386388181892822824380397568110430789037287,"line":306,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 534064041 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 534064041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"27.clkmgr_frequency_timeout.88198523655094945681023645582039760612194162301523594938151796371691239486964","seed":88198523655094945681023645582039760612194162301523594938151796371691239486964,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2255711 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2255711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"27.clkmgr_stress_all_with_rand_reset.7851498639118851441630140610491146387027816991132352187140412373514143531547","seed":7851498639118851441630140610491146387027816991132352187140412373514143531547,"line":141,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 135704014 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 135704014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"27.clkmgr_stress_all.24673058709282603173074778871658050065032207261662667922542479765045435407698","seed":24673058709282603173074778871658050065032207261662667922542479765045435407698,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   7522793 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7522793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"28.clkmgr_frequency_timeout.63748846300695033016738763011417245230916029211478906544904348913994364535164","seed":63748846300695033016738763011417245230916029211478906544904348913994364535164,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/28.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5210484 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5210484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"28.clkmgr_stress_all_with_rand_reset.17037370561297170877089357441193620382652500267681379086391632759602073333866","seed":17037370561297170877089357441193620382652500267681379086391632759602073333866,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/28.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  19089900 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  19089900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"29.clkmgr_frequency_timeout.9280642069932052302087346944722327692021709258485806085311136321687561954893","seed":9280642069932052302087346944722327692021709258485806085311136321687561954893,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2677408 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2677408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"29.clkmgr_stress_all_with_rand_reset.5627456852286931816866459264177972399208511692071888178650050825157432411402","seed":5627456852286931816866459264177972399208511692071888178650050825157432411402,"line":85,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  13796738 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  13796738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"29.clkmgr_stress_all.9705044286489203232540368003052260252369785428992939456495590874200867620892","seed":9705044286489203232540368003052260252369785428992939456495590874200867620892,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   5292564 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5292564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"30.clkmgr_frequency_timeout.13750482764909564247494306982475171413675390726255873055398753315468651855719","seed":13750482764909564247494306982475171413675390726255873055398753315468651855719,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @  10076140 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  10076140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"30.clkmgr_stress_all_with_rand_reset.97091548880921393770429527986399067027822573737310922289563188703914079122476","seed":97091548880921393770429527986399067027822573737310922289563188703914079122476,"line":210,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 152928808 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 152928808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"30.clkmgr_stress_all.58174805654238361221614235563596298611241923971315571998037381583372431031241","seed":58174805654238361221614235563596298611241923971315571998037381583372431031241,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  15719854 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  15719854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"31.clkmgr_frequency_timeout.10779463484121639435061231600250353859462692300232506476786935340967169009946","seed":10779463484121639435061231600250353859462692300232506476786935340967169009946,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5433816 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5433816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"31.clkmgr_stress_all_with_rand_reset.38001896487032327067354808166384357905689760019609819055315733515227908789275","seed":38001896487032327067354808166384357905689760019609819055315733515227908789275,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   4836898 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4836898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"31.clkmgr_stress_all.70655576946937860373000712539683668478972611915987219996340272122639208587010","seed":70655576946937860373000712539683668478972611915987219996340272122639208587010,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  33339633 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  33339633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"32.clkmgr_frequency_timeout.50248698438028451798205082944562292596091985143937165477087824978571652537410","seed":50248698438028451798205082944562292596091985143937165477087824978571652537410,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4275566 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4275566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"32.clkmgr_stress_all_with_rand_reset.22583368691576926206912035185249172181425229049398907542342003713726552206021","seed":22583368691576926206912035185249172181425229049398907542342003713726552206021,"line":89,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  52363179 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  52363179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"32.clkmgr_stress_all.57814144353006460007002730496766772126300736719980192770751165705882567599141","seed":57814144353006460007002730496766772126300736719980192770751165705882567599141,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   7400919 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7400919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"33.clkmgr_frequency_timeout.41929886334582926086662004009363980942241775831426554440447587881996337979085","seed":41929886334582926086662004009363980942241775831426554440447587881996337979085,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4550752 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4550752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"33.clkmgr_stress_all.32121213569500579210195953786765178530760430678738573182078306128442667828095","seed":32121213569500579210195953786765178530760430678738573182078306128442667828095,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  17006989 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  17006989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"34.clkmgr_frequency_timeout.107638043422910506836203315475984245128769483854389137009141485597228629196932","seed":107638043422910506836203315475984245128769483854389137009141485597228629196932,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4389908 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4389908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"34.clkmgr_stress_all.99854787028477257644105773050522737548595163557814456116118025541699233463391","seed":99854787028477257644105773050522737548595163557814456116118025541699233463391,"line":142,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  39184190 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  39184190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"35.clkmgr_stress_all.68247492952921236750897416871309069212011103231893409346720790726090908330307","seed":68247492952921236750897416871309069212011103231893409346720790726090908330307,"line":106,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 136325019 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 136325019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"36.clkmgr_frequency_timeout.88214923033473174721025165451967749803129313974225877413159570383649817914829","seed":88214923033473174721025165451967749803129313974225877413159570383649817914829,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6182644 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6182644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"36.clkmgr_stress_all_with_rand_reset.103999712829750663559128910233853822241503504108561563770256305593719880369849","seed":103999712829750663559128910233853822241503504108561563770256305593719880369849,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 105928818 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 105928818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"36.clkmgr_stress_all.106244990934821335303220148335981473262240252064487855709622571823288481651082","seed":106244990934821335303220148335981473262240252064487855709622571823288481651082,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   5408942 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5408942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"37.clkmgr_frequency_timeout.53427323653730252438947780290850451366042986491484991485159687584152569171603","seed":53427323653730252438947780290850451366042986491484991485159687584152569171603,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6445701 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6445701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"37.clkmgr_stress_all_with_rand_reset.101014121236713872503823032787506453095486532240995814518675640058145385428076","seed":101014121236713872503823032787506453095486532240995814518675640058145385428076,"line":139,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  34196424 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  34196424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"38.clkmgr_frequency_timeout.44719974711528733566920734525977012520947103561001478161055314694527511962375","seed":44719974711528733566920734525977012520947103561001478161055314694527511962375,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3520930 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3520930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"38.clkmgr_stress_all.42829337221753850714296270472251893778460739649085213111575003518134959791862","seed":42829337221753850714296270472251893778460739649085213111575003518134959791862,"line":133,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 244317021 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 244317021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"39.clkmgr_frequency_timeout.31670601315600679867162919988560099504959207471437815548684065082711134989315","seed":31670601315600679867162919988560099504959207471437815548684065082711134989315,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2089213 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2089213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"39.clkmgr_stress_all_with_rand_reset.11788859899548391170014094322232070407203733293294535344808146852599005386064","seed":11788859899548391170014094322232070407203733293294535344808146852599005386064,"line":276,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 433224747 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 433224747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"40.clkmgr_frequency_timeout.49863282974327614967163170239886820413364430098607815954907327400733531486538","seed":49863282974327614967163170239886820413364430098607815954907327400733531486538,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3658175 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3658175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"40.clkmgr_stress_all.7684140786588424755657572944214606137635305561804479060554244040549954212177","seed":7684140786588424755657572944214606137635305561804479060554244040549954212177,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 140865917 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 140865917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"41.clkmgr_frequency_timeout.64420243481722306555225281680088418550279275332334276253619559953240261688909","seed":64420243481722306555225281680088418550279275332334276253619559953240261688909,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3720370 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3720370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"42.clkmgr_frequency_timeout.11177610398546288638948948287390246464600926675672304381807810875929566682375","seed":11177610398546288638948948287390246464600926675672304381807810875929566682375,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6086823 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6086823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"42.clkmgr_stress_all_with_rand_reset.50469123532080591362952265360901533542378405409150506887928499251682624553347","seed":50469123532080591362952265360901533542378405409150506887928499251682624553347,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   2691700 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2691700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"43.clkmgr_frequency_timeout.76096272531924715920939556439894350399125815673462702349980530883835974999767","seed":76096272531924715920939556439894350399125815673462702349980530883835974999767,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4736024 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4736024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"43.clkmgr_stress_all_with_rand_reset.83430089641714898663239473380226387978207551717161512326942553645070121303051","seed":83430089641714898663239473380226387978207551717161512326942553645070121303051,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  11438747 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  11438747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"44.clkmgr_frequency_timeout.85265243384747646014995988489041208249656394171110563669457982403097591813272","seed":85265243384747646014995988489041208249656394171110563669457982403097591813272,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @  14845670 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  14845670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"44.clkmgr_stress_all.48628763235135030476310842421706431401214995216904310444054902838513661227504","seed":48628763235135030476310842421706431401214995216904310444054902838513661227504,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   6642163 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6642163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"45.clkmgr_frequency_timeout.65890346060998143550975363567976489344964899588840245858252149102416481410750","seed":65890346060998143550975363567976489344964899588840245858252149102416481410750,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2614754 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2614754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"45.clkmgr_stress_all.104008383955980417739006182312328633299704540289891404159668723801264864386751","seed":104008383955980417739006182312328633299704540289891404159668723801264864386751,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   4641065 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4641065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"46.clkmgr_frequency_timeout.87972822706303652247072515199208933405771809232103893553429797269902803251788","seed":87972822706303652247072515199208933405771809232103893553429797269902803251788,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3761358 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3761358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"46.clkmgr_stress_all.64681253328478574103181431557102790383783775653280237588040453422310127356853","seed":64681253328478574103181431557102790383783775653280237588040453422310127356853,"line":106,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  53882145 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  53882145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"47.clkmgr_frequency_timeout.26797183039808454525577218897930830917165096336169387963430207398842534155583","seed":26797183039808454525577218897930830917165096336169387963430207398842534155583,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3571711 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3571711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"47.clkmgr_stress_all_with_rand_reset.94915668161132833320285480416314487474382350881457467577491764749105875227891","seed":94915668161132833320285480416314487474382350881457467577491764749105875227891,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   7733827 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7733827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"48.clkmgr_frequency_timeout.91274383109871931511131721815820431021484969402002204953959406162848598398755","seed":91274383109871931511131721815820431021484969402002204953959406162848598398755,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2700043 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2700043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"48.clkmgr_stress_all.20304825972253880780603445317397382834631395158741925145012939296746538034673","seed":20304825972253880780603445317397382834631395158741925145012939296746538034673,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   1574875 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   1574875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"49.clkmgr_frequency_timeout.13050768466875273734710585884758462295675655028855322770901394894404460738040","seed":13050768466875273734710585884758462295675655028855322770901394894404460738040,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   8894544 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8894544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"49.clkmgr_stress_all_with_rand_reset.60829124892289881637757784512351425186116157535356905064294221024154823479474","seed":60829124892289881637757784512351425186116157535356905064294221024154823479474,"line":151,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  94405494 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  94405494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"49.clkmgr_stress_all.94526774589415230472479065632589345495223486492847505746058936508750395887594","seed":94526774589415230472479065632589345495223486492847505746058936508750395887594,"line":126,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 156706539 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 156706539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.main_meas_ctrl_en":[{"name":"clkmgr_regwen","qual_name":"0.clkmgr_regwen.61669040697906923312315280845076588446745566797810549828123972223463548653258","seed":61669040697906923312315280845076588446745566797810549828123972223463548653258,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4561965 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @   4561965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"2.clkmgr_regwen.59944457165984187122473636599818808759396799126142391981201718124096462980332","seed":59944457165984187122473636599818808759396799126142391981201718124096462980332,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6564398 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @   6564398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"22.clkmgr_regwen.64696318408438774272841467377253248854494516739743073089503951940972606378053","seed":64696318408438774272841467377253248854494516739743073089503951940972606378053,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  22360717 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (13 [0xd] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @  22360717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"34.clkmgr_regwen.38970988872098621641246112611115778503893330614828900330878039384152486682019","seed":38970988872098621641246112611115778503893330614828900330878039384152486682019,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2867908 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @   2867908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en":[{"name":"clkmgr_regwen","qual_name":"1.clkmgr_regwen.90143293265855797278965506455498312650701542826671542139646592574420541736277","seed":90143293265855797278965506455498312650701542826671542139646592574420541736277,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   8367443 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   8367443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"3.clkmgr_regwen.82611986857468648942695412588081720869771291742289181948550813297726880716714","seed":82611986857468648942695412588081720869771291742289181948550813297726880716714,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   8695200 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   8695200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"4.clkmgr_regwen.54355752047758153889092651677398703191711580302067698473353490203261709936211","seed":54355752047758153889092651677398703191711580302067698473353490203261709936211,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3926413 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3926413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"5.clkmgr_regwen.19536959115896485939918542883503445994735620017281675064095635285364537422298","seed":19536959115896485939918542883503445994735620017281675064095635285364537422298,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3308101 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3308101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"8.clkmgr_regwen.40558244000356998813303042086092519959926080154731863443733944872276229305674","seed":40558244000356998813303042086092519959926080154731863443733944872276229305674,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   7071278 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (15 [0xf] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   7071278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"9.clkmgr_regwen.61648804538159131729248460349847482738547849922569972488299577320982684352227","seed":61648804538159131729248460349847482738547849922569972488299577320982684352227,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6193139 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   6193139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"10.clkmgr_regwen.35536623042692145873002148841901188285623135581174271126349461936292825693381","seed":35536623042692145873002148841901188285623135581174271126349461936292825693381,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4644049 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   4644049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"11.clkmgr_regwen.5163994619778466721408202888690858923150259641376524030478463931353792272184","seed":5163994619778466721408202888690858923150259641376524030478463931353792272184,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3249853 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3249853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"12.clkmgr_regwen.55412386575916954008471840856721094607131172307019423358895706746889177512844","seed":55412386575916954008471840856721094607131172307019423358895706746889177512844,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  12382458 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 3 [0x3]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @  12382458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"13.clkmgr_regwen.103481419542059756869816507844879801585977747395812557325190319806650569990379","seed":103481419542059756869816507844879801585977747395812557325190319806650569990379,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4792643 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 11 [0xb]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   4792643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"16.clkmgr_regwen.33174812792486022543989365116055845758607984551312421272416850085328439009040","seed":33174812792486022543989365116055845758607984551312421272416850085328439009040,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3710207 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 5 [0x5]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3710207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"23.clkmgr_regwen.102056550108250244345433276299286230782056702451187608541541859589048809910274","seed":102056550108250244345433276299286230782056702451187608541541859589048809910274,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3273618 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 3 [0x3]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3273618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"24.clkmgr_regwen.41490472745452961778208050376244349588452223133695255074879603428817972360478","seed":41490472745452961778208050376244349588452223133695255074879603428817972360478,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3067242 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 3 [0x3]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3067242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"27.clkmgr_regwen.41162821857473336602784613188528812841760519603477639093167837133863689178655","seed":41162821857473336602784613188528812841760519603477639093167837133863689178655,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2239531 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 11 [0xb]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2239531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"28.clkmgr_regwen.55587807103846756820393902025972477586039369788036117252259058127259195253792","seed":55587807103846756820393902025972477586039369788036117252259058127259195253792,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/28.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5755024 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 8 [0x8]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   5755024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"29.clkmgr_regwen.102909915343197793625318612419646101628601517412778355155097022924367511028988","seed":102909915343197793625318612419646101628601517412778355155097022924367511028988,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5455873 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   5455873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"31.clkmgr_regwen.96059545746240793790447840971417345612833128853826012223856090694149916678491","seed":96059545746240793790447840971417345612833128853826012223856090694149916678491,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   8153335 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 13 [0xd]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   8153335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"32.clkmgr_regwen.58560742007066029297082145584899458425088394047204453054060950577529413235772","seed":58560742007066029297082145584899458425088394047204453054060950577529413235772,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5687946 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 10 [0xa]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   5687946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"33.clkmgr_regwen.114330151738170731317329156609991656282747456017874250927187119268118358211778","seed":114330151738170731317329156609991656282747456017874250927187119268118358211778,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5312702 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 0 [0x0]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   5312702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"37.clkmgr_regwen.35112851699922362889827543120055770863048857216299610335146204633912170847399","seed":35112851699922362889827543120055770863048857216299610335146204633912170847399,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   1932310 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   1932310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"38.clkmgr_regwen.47154381172770441134689478403676860152791462393689280407711489606537949135962","seed":47154381172770441134689478403676860152791462393689280407711489606537949135962,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   7022228 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (10 [0xa] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   7022228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"41.clkmgr_regwen.81353471652792120606456472101854131993145623930148835288307081910486197849585","seed":81353471652792120606456472101854131993145623930148835288307081910486197849585,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   1840519 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   1840519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"43.clkmgr_regwen.28348098806853945081683230131940668706638929786010970725887069702040411734144","seed":28348098806853945081683230131940668706638929786010970725887069702040411734144,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  25514823 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (7 [0x7] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @  25514823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"44.clkmgr_regwen.72669955784437068816529050456985399505587700640289638872630926787880740809150","seed":72669955784437068816529050456985399505587700640289638872630926787880740809150,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6695950 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   6695950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"47.clkmgr_regwen.107889928545256102786839785558341509017868208482656236998591061974725983646636","seed":107889928545256102786839785558341509017868208482656236998591061974725983646636,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   7367149 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (12 [0xc] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   7367149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"48.clkmgr_regwen.22884169666035611183012668797259084843338727642452526478771910729942085674291","seed":22884169666035611183012668797259084843338727642452526478771910729942085674291,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  11641209 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @  11641209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"49.clkmgr_regwen.59960426646273964154001050601555213608969221680962175671202330637037476713325","seed":59960426646273964154001050601555213608969221680962175671202330637037476713325,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2413229 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2413229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire":[{"name":"clkmgr_sec_cm","qual_name":"1.clkmgr_sec_cm.104612584373932863121241261900794845576796365517092713496409924159107836732478","seed":104612584373932863121241261900794845576796365517092713496409924159107836732478,"line":140,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_sec_cm/latest/run.log","log_context":["UVM_ERROR @  77569038 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire\n","UVM_INFO @  77569038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_sec_cm","qual_name":"2.clkmgr_sec_cm.8008315196268720550427158509854232856898362483286529353578041945566504908880","seed":8008315196268720550427158509854232856898362483286529353578041945566504908880,"line":93,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_sec_cm/latest/run.log","log_context":["UVM_ERROR @  26075827 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire\n","UVM_INFO @  26075827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed":[{"name":"clkmgr_regwen","qual_name":"7.clkmgr_regwen.74706377034965186300857071041442009653753122779108399846755579987760971264727","seed":74706377034965186300857071041442009653753122779108399846755579987760971264727,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4428046 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   4428046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"14.clkmgr_regwen.5861140685602683901241555439239674251885718386598869181873602664701907327856","seed":5861140685602683901241555439239674251885718386598869181873602664701907327856,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4012378 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   4012378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"15.clkmgr_regwen.5099209480909194490125770486984813126412393454941941126627268885018937914078","seed":5099209480909194490125770486984813126412393454941941126627268885018937914078,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4323553 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   4323553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"17.clkmgr_regwen.5362346644726844632254453727049897751091766684083677699912087191102656629370","seed":5362346644726844632254453727049897751091766684083677699912087191102656629370,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3387262 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   3387262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"18.clkmgr_regwen.92775929874166132360249181386839895508720998307820963842598285986298533277492","seed":92775929874166132360249181386839895508720998307820963842598285986298533277492,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6754272 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   6754272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"19.clkmgr_regwen.67189033342123844615294801316543339013449979676741928135495452546195581118127","seed":67189033342123844615294801316543339013449979676741928135495452546195581118127,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  42260563 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @  42260563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"20.clkmgr_regwen.18516819951020359790170288628394583092276102698055382313911258581209569371644","seed":18516819951020359790170288628394583092276102698055382313911258581209569371644,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3989218 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   3989218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"21.clkmgr_regwen.41509702112960723843033267880621928005353007175606669187070017575525817033110","seed":41509702112960723843033267880621928005353007175606669187070017575525817033110,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3216460 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   3216460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"25.clkmgr_regwen.49819534837554233559383907520594307607961422205630249167695468556312487668189","seed":49819534837554233559383907520594307607961422205630249167695468556312487668189,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3355985 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   3355985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"26.clkmgr_regwen.53622360697660476243150027021352282881115282247802557362731896749673741703286","seed":53622360697660476243150027021352282881115282247802557362731896749673741703286,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2753827 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   2753827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"30.clkmgr_regwen.105471742363788763399031611445349013018634450162138027958847797648145887823501","seed":105471742363788763399031611445349013018634450162138027958847797648145887823501,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2934893 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   2934893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"35.clkmgr_regwen.1377394838052176443370375794354447260747695767330038486078660361751210682128","seed":1377394838052176443370375794354447260747695767330038486078660361751210682128,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3032588 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   3032588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"36.clkmgr_regwen.36954690924613512018321452987624283275097372630904541042263733897608489771623","seed":36954690924613512018321452987624283275097372630904541042263733897608489771623,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5063517 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   5063517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"39.clkmgr_regwen.99960517319023619624477206562977163440342227163958326166720000453501809291534","seed":99960517319023619624477206562977163440342227163958326166720000453501809291534,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3727252 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   3727252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"42.clkmgr_regwen.100187068497895617514912207354930071748285244177116054709741313072852630523600","seed":100187068497895617514912207354930071748285244177116054709741313072852630523600,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3955610 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   3955610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"46.clkmgr_regwen.56438112882939912319736030082882783917256472708274195170777639176991536123804","seed":56438112882939912319736030082882783917256472708274195170777639176991536123804,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6184935 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   6184935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":577,"total":1205,"percent":47.88381742738589}