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(edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.":[{"name":"edn_disable_auto_req_mode","qual_name":"12.edn_disable_auto_req_mode.61297052440394425741161517937887072156753185208422079962525014224475875030216","seed":61297052440394425741161517937887072156753185208422079962525014224475875030216,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/12.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 200971701 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00587902 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @ 200971701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"23.edn_disable_auto_req_mode.49101427428371902507961098221340607263673733357124825575787886245135203485641","seed":49101427428371902507961098221340607263673733357124825575787886245135203485641,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/23.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  49044505 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x001d3942 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  49044505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"edn_stress_all_with_rand_reset","qual_name":"17.edn_stress_all_with_rand_reset.49882458438773503789673544481233216120363460929043275823101533524685381931577","seed":49882458438773503789673544481233216120363460929043275823101533524685381931577,"line":165,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/17.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1080966409 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1080966409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"20.edn_stress_all_with_rand_reset.46888504437427043979846939698800648398355062393176454319140026257229737230877","seed":46888504437427043979846939698800648398355062393176454319140026257229737230877,"line":159,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/20.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1459314103 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1459314103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"25.edn_stress_all_with_rand_reset.33703916067536202142004372789613250620178023566411600295606746038615662543548","seed":33703916067536202142004372789613250620178023566411600295606746038615662543548,"line":202,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/25.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1667298244 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1667298244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"26.edn_stress_all_with_rand_reset.12428487842481235668293280597575106015582058316755323450193210074291729715037","seed":12428487842481235668293280597575106015582058316755323450193210074291729715037,"line":208,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/26.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1180175153 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1180175153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"40.edn_stress_all_with_rand_reset.36821309624336371398984413283471661149476608601513300203146371834400432595909","seed":36821309624336371398984413283471661149476608601513300203146371834400432595909,"line":216,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/40.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1432244305 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1432244305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"42.edn_stress_all_with_rand_reset.23082026687730443782121163597891593006433722744434043660664758805807285087812","seed":23082026687730443782121163597891593006433722744434043660664758805807285087812,"line":182,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/42.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1627408288 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1627408288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"edn_disable_auto_req_mode","qual_name":"17.edn_disable_auto_req_mode.98782122430024625534385294288918211807935877558850088653089036379994177072102","seed":98782122430024625534385294288918211807935877558850088653089036379994177072102,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/17.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"28.edn_disable_auto_req_mode.13793743037424855610539750476851831379190571110958047665200909788076593790970","seed":13793743037424855610539750476851831379190571110958047665200909788076593790970,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/28.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"29.edn_disable_auto_req_mode.2856379845031285235283099389376216906222889942469593881889144773607120460883","seed":2856379845031285235283099389376216906222889942469593881889144773607120460883,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/29.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"35.edn_disable_auto_req_mode.80574214926929872790396948580225882768241493576634595654945846673403446150170","seed":80574214926929872790396948580225882768241493576634595654945846673403446150170,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/35.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"43.edn_disable_auto_req_mode.110925465984227914526504371411801162936174868518944236736859571490046433254059","seed":110925465984227914526504371411801162936174868518944236736859571490046433254059,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/43.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"45.edn_disable_auto_req_mode.45463609232326949819069961777166693188281644005791486047342590332084842588607","seed":45463609232326949819069961777166693188281644005791486047342590332084842588607,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/45.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (edn_scoreboard.sv:318) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts":[{"name":"edn_stress_all_with_rand_reset","qual_name":"43.edn_stress_all_with_rand_reset.85184349355113082876544350069892081115457729755199966903385586935594627647489","seed":85184349355113082876544350069892081115457729755199966903385586935594627647489,"line":247,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/43.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1017390121 ps: (edn_scoreboard.sv:318) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (7 [0x7] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts\n","UVM_INFO @ 1017390121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":2485,"total":2500,"percent":99.4}