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(edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.":[{"name":"edn_disable_auto_req_mode","qual_name":"1.edn_disable_auto_req_mode.110086310930435364231108246304435909833700275443757817082263101505531572687409","seed":110086310930435364231108246304435909833700275443757817082263101505531572687409,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  13853434 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x002469c2 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  13853434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"6.edn_disable_auto_req_mode.92659167453863895121535457182942125949414551258691992547380482368292667070099","seed":92659167453863895121535457182942125949414551258691992547380482368292667070099,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  58268680 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x003b6602 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  58268680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"8.edn_disable_auto_req_mode.102067308406889811409986953108095298802954102180003070504017131364582819521827","seed":102067308406889811409986953108095298802954102180003070504017131364582819521827,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  58194499 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x005c69b2 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  58194499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"32.edn_disable_auto_req_mode.43588092934596027264369734416021611379276798761695163481284914988034379321709","seed":43588092934596027264369734416021611379276798761695163481284914988034379321709,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/32.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  70492199 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00465672 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  70492199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"edn_stress_all_with_rand_reset","qual_name":"3.edn_stress_all_with_rand_reset.113876996227436299815381279947495212475292724966767691169537917683397228192085","seed":113876996227436299815381279947495212475292724966767691169537917683397228192085,"line":153,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/3.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1731206271 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1731206271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"15.edn_stress_all_with_rand_reset.36071394482117123609593532342689133389659779385297327204690059439484294439685","seed":36071394482117123609593532342689133389659779385297327204690059439484294439685,"line":129,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 339213171 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 339213171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"18.edn_stress_all_with_rand_reset.108066092019691652489624060903526411940970353600858958825695745349802890339932","seed":108066092019691652489624060903526411940970353600858958825695745349802890339932,"line":213,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/18.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1455195710 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1455195710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"22.edn_stress_all_with_rand_reset.97217283394487877798534008596946619521310721698064752098486104649224191727408","seed":97217283394487877798534008596946619521310721698064752098486104649224191727408,"line":137,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/22.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 146963228 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 146963228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"31.edn_stress_all_with_rand_reset.37755611252836150596829812546618467529194535304214776855556865998484783349045","seed":37755611252836150596829812546618467529194535304214776855556865998484783349045,"line":337,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/31.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3930548898 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3930548898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"47.edn_stress_all_with_rand_reset.102034792353334083210288904694047193986609408881002940454418963297809026570344","seed":102034792353334083210288904694047193986609408881002940454418963297809026570344,"line":323,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/47.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4054398583 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4054398583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"edn_disable_auto_req_mode","qual_name":"15.edn_disable_auto_req_mode.57650320412438817307365725097028175823243701676675385380061637365723607061911","seed":57650320412438817307365725097028175823243701676675385380061637365723607061911,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"23.edn_disable_auto_req_mode.20935350356477803979555246236205786664822126253451398362534150030233918646274","seed":20935350356477803979555246236205786664822126253451398362534150030233918646274,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/23.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"24.edn_disable_auto_req_mode.66942854650803865596041219716464606509042973961536583767099145334207676369555","seed":66942854650803865596041219716464606509042973961536583767099145334207676369555,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/24.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"38.edn_disable_auto_req_mode.14032687699780990713944763677501913962426272878343167125649972590271557360242","seed":14032687699780990713944763677501913962426272878343167125649972590271557360242,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/38.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"40.edn_disable_auto_req_mode.109115839116184014672407953334152876436615214979902244378451829429217020074623","seed":109115839116184014672407953334152876436615214979902244378451829429217020074623,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/40.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"42.edn_disable_auto_req_mode.9670939247237124450238226610669739274770801607388176070844229534542003635646","seed":9670939247237124450238226610669739274770801607388176070844229534542003635646,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/42.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"46.edn_disable_auto_req_mode.4812586609580596964776322538096035326633631537107790803548942033472070039330","seed":4812586609580596964776322538096035326633631537107790803548942033472070039330,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/46.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"47.edn_disable_auto_req_mode.106538307942133038533814332202206852496754420712909578001550428175375236871061","seed":106538307942133038533814332202206852496754420712909578001550428175375236871061,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/47.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"48.edn_disable_auto_req_mode.110110789606500022657238819140733682269510224799003556825631855411083261224363","seed":110110789606500022657238819140733682269510224799003556825631855411083261224363,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/48.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":2481,"total":2500,"percent":99.24}