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(cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"keymgr_stress_all_with_rand_reset","qual_name":"3.keymgr_stress_all_with_rand_reset.39889677559869801092375334282771314326583995961170866303659937760051388133977","seed":39889677559869801092375334282771314326583995961170866303659937760051388133977,"line":115,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 297942520 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 297942520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"6.keymgr_stress_all_with_rand_reset.24910216773386493358402494305967108537989633899037140855776694683005487832399","seed":24910216773386493358402494305967108537989633899037140855776694683005487832399,"line":178,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 111203814 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 111203814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"7.keymgr_stress_all_with_rand_reset.15886765804257013799673951434646819964283459518004686687083421163234264804796","seed":15886765804257013799673951434646819964283459518004686687083421163234264804796,"line":163,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 113830459 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 113830459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"9.keymgr_stress_all_with_rand_reset.63396601000617891073633367515303117117627694258977516642824874787311191179952","seed":63396601000617891073633367515303117117627694258977516642824874787311191179952,"line":142,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/9.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 459559496 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 459559496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"11.keymgr_stress_all_with_rand_reset.102711074980300236282330896234874984574603827397870619573321407204568104698739","seed":102711074980300236282330896234874984574603827397870619573321407204568104698739,"line":532,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 889269366 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 889269366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"12.keymgr_stress_all_with_rand_reset.40493267750595102099601546953571625504322765571727684019315724484216219398753","seed":40493267750595102099601546953571625504322765571727684019315724484216219398753,"line":370,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/12.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 922313633 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 922313633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"13.keymgr_stress_all_with_rand_reset.4371336646343585473498406553067373477713111541697732333867404026747953062224","seed":4371336646343585473498406553067373477713111541697732333867404026747953062224,"line":259,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/13.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 139746423 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 139746423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"15.keymgr_stress_all_with_rand_reset.44496145226517623911422512448531118458316275306808692380063167432240381635515","seed":44496145226517623911422512448531118458316275306808692380063167432240381635515,"line":459,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/15.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 219176390 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 219176390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"16.keymgr_stress_all_with_rand_reset.32542227336226592473831368955500630201389230792981465218004704201849251422442","seed":32542227336226592473831368955500630201389230792981465218004704201849251422442,"line":1978,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/16.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5193555663 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5193555663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"17.keymgr_stress_all_with_rand_reset.59377251077685318204271727663508183203129053524099793617400832573514654913257","seed":59377251077685318204271727663508183203129053524099793617400832573514654913257,"line":560,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/17.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 312706646 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 312706646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"19.keymgr_stress_all_with_rand_reset.99135519035578034979264290262258086979631148507691551769617791395977557399661","seed":99135519035578034979264290262258086979631148507691551769617791395977557399661,"line":177,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/19.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 164333036 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 164333036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"21.keymgr_stress_all_with_rand_reset.104653226175090521181285527500977769522353858324882610451089094523677817036112","seed":104653226175090521181285527500977769522353858324882610451089094523677817036112,"line":209,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/21.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 478566663 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 478566663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"24.keymgr_stress_all_with_rand_reset.15889328307333546414466725887560220738009013256903465205918675928158570489834","seed":15889328307333546414466725887560220738009013256903465205918675928158570489834,"line":392,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/24.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 203734495 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 203734495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"26.keymgr_stress_all_with_rand_reset.19631455108705238313262052756392360774524793321702865200212177545563612068768","seed":19631455108705238313262052756392360774524793321702865200212177545563612068768,"line":1195,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/26.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1391236367 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1391236367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"28.keymgr_stress_all_with_rand_reset.96532597248021774838391442189800307275769541119626134680690170232605344847716","seed":96532597248021774838391442189800307275769541119626134680690170232605344847716,"line":508,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/28.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 772893434 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 772893434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"32.keymgr_stress_all_with_rand_reset.43428798274728127173222994849960708040766426462545231259112713534126171906906","seed":43428798274728127173222994849960708040766426462545231259112713534126171906906,"line":138,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/32.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 114713656 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 114713656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"35.keymgr_stress_all_with_rand_reset.63996996771523954514247925602306780254137422626859751761751629819960504861741","seed":63996996771523954514247925602306780254137422626859751761751629819960504861741,"line":533,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/35.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 595489204 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 595489204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"45.keymgr_stress_all_with_rand_reset.88073973668981085727206186134539768562515432747210241062508515798210910659745","seed":88073973668981085727206186134539768562515432747210241062508515798210910659745,"line":395,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/45.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 175407976 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 175407976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"47.keymgr_stress_all_with_rand_reset.23328149167424153383210513248705597813306153727528127533703934483638430446049","seed":23328149167424153383210513248705597813306153727528127533703934483638430446049,"line":1149,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/47.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1344977286 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1344977286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"49.keymgr_stress_all_with_rand_reset.63103775159067801278157291804525406633388734738453584229565898193806059851438","seed":63103775159067801278157291804525406633388734738453584229565898193806059851438,"line":1053,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/49.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 275376182 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 275376182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (keymgr_scoreboard.sv:1064) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation":[{"name":"keymgr_stress_all_with_rand_reset","qual_name":"18.keymgr_stress_all_with_rand_reset.47843893404491089883903805767525112414746763449473332985381758200387563155668","seed":47843893404491089883903805767525112414746763449473332985381758200387563155668,"line":250,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/18.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 220874607 ps: (keymgr_scoreboard.sv:1064) [uvm_test_top.env.scoreboard] Check failed act == exp (57264938237226565317967751560125513211119886832142080436353959212675742142986363846461891440567181140707993699235352445409371858535705870371801218784603568553315231885483008921951154949164441587480409731349765728515264364339500262538878068530013358331168895644673595993570358618722454893522797497406243081883897996444239340975235536206281861046640 [0xefa5e173ef4743c0191abd727c62a47f5171fa9c2fbb4dca9b8d334017b53cf2000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f50769802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170] vs 24459183406215967955315575033552373465006801300606064361815348050967505134549204251596154112212519721400651317425676031804882248876809096317396977314425661276925964050097902523244545133761586215192643387476201389150662753494686565683202914739529839769252931823799541239009130153412489514682588546441869548105605705045356911792470781722156399403376 [0x665bf502c52516881b1f375bc43c3c9a0000000000000000df066b812abbc3e7000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f50769802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170]) cdi_type: Attestation\n","\n"," HardwareRevisionSecret act: 0x69802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170, exp: 0x69802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170\n"," RomDigest act: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507, exp: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507\n"," HealthMeasurement act: 0x5cfbd765ce33f34e, exp: 0x5cfbd765ce33f34e\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*":[{"name":"keymgr_cfg_regwen","qual_name":"26.keymgr_cfg_regwen.23512273689890822404751126069568375181553580760158564445138140608801813411967","seed":23512273689890822404751126069568375181553580760158564445138140608801813411967,"line":110,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/26.keymgr_cfg_regwen/latest/run.log","log_context":["UVM_ERROR @  19600989 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @  19600989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all","qual_name":"35.keymgr_stress_all.76989430317788328584381671336026335338655516034621554828017717891318812889819","seed":76989430317788328584381671336026335338655516034621554828017717891318812889819,"line":151,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/35.keymgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 145475625 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @ 145475625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_cfg_regwen","qual_name":"43.keymgr_cfg_regwen.51157647072778317198596157029857402945689374764395510924612582161530636846583","seed":51157647072778317198596157029857402945689374764395510924612582161530636846583,"line":153,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/43.keymgr_cfg_regwen/latest/run.log","log_context":["UVM_ERROR @   5879515 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @   5879515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_cfg_regwen","qual_name":"44.keymgr_cfg_regwen.49190778600180330376329354338755063044990180902832375051823854739266997557260","seed":49190778600180330376329354338755063044990180902832375051823854739266997557260,"line":162,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/44.keymgr_cfg_regwen/latest/run.log","log_context":["UVM_ERROR @  92796573 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @  92796573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_*":[{"name":"keymgr_lc_disable","qual_name":"40.keymgr_lc_disable.70076381314669044184537847036051761034291200542558582556744066109950997232709","seed":70076381314669044184537847036051761034291200542558582556744066109950997232709,"line":396,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/40.keymgr_lc_disable/latest/run.log","log_context":["UVM_ERROR @ 167121212 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (1548753059 [0x5c5018a3] vs 1548753059 [0x5c5018a3]) reg name: keymgr_reg_block.sw_share1_output_6\n","UVM_INFO @ 167121212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StOwnerIntKey for Sealing Kmac":[{"name":"keymgr_lc_disable","qual_name":"42.keymgr_lc_disable.98045179015339080099699540049075241923366544525954464116780726636723873960607","seed":98045179015339080099699540049075241923366544525954464116780726636723873960607,"line":449,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/42.keymgr_lc_disable/latest/run.log","log_context":["UVM_ERROR @ 332615692 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (824445537317976385747138208263836671083420244854227412334104309440085390797653896475223000590475312108600588825560195374547966627945430690292537129829506 [0xfbdce4bb4c6935f0b10238623e7c1d136ac6341b1e3d5686e774606ee996e26357764cbfd1b8f8471c945c5f1dabc0c2e7e6f54943500dd4c4f93bd34520482] vs 824445537317976385747138208263836671083420244854227412334104309440085390797653896475223000590475312108600588825560195374547966627945430690292537129829506 [0xfbdce4bb4c6935f0b10238623e7c1d136ac6341b1e3d5686e774606ee996e26357764cbfd1b8f8471c945c5f1dabc0c2e7e6f54943500dd4c4f93bd34520482]) KMAC key at state StOwnerIntKey for Sealing Kmac\n","UVM_INFO @ 332615692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":2064,"total":2100,"percent":98.28571428571429}