{"block":{"name":"otbn","variant":null,"commit":"3ba6465de32edf4612bd1c0fa13f7e4cb5f4a7da","commit_short":"3ba6465","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/3ba6465de32edf4612bd1c0fa13f7e4cb5f4a7da","revision_info":"GitHub Revision: [`3ba6465`](https://github.com/lowrisc/opentitan/tree/3ba6465de32edf4612bd1c0fa13f7e4cb5f4a7da)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-04-03T17:01:04Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/otbn/dv/data/otbn_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"otbn_smoke":{"max_time":12.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"single_binary":{"tests":{"otbn_single":{"max_time":441.0,"sim_time":0.0,"passed":100,"total":100,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"csr_hw_reset":{"tests":{"otbn_csr_hw_reset":{"max_time":10.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"otbn_csr_rw":{"max_time":8.0,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"otbn_csr_bit_bash":{"max_time":11.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"otbn_csr_aliasing":{"max_time":9.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"otbn_csr_mem_rw_with_rand_reset":{"max_time":10.0,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"otbn_csr_rw":{"max_time":8.0,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"otbn_csr_aliasing":{"max_time":9.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"mem_walk":{"tests":{"otbn_mem_walk":{"max_time":120.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"mem_partial_access":{"tests":{"otbn_mem_partial_access":{"max_time":38.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0}},"passed":191,"total":191,"percent":100.0},"V2":{"testpoints":{"reset_recovery":{"tests":{"otbn_reset":{"max_time":43.0,"sim_time":0.0,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"multi_error":{"tests":{"otbn_multi_err":{"max_time":50.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"back_to_back":{"tests":{"otbn_multi":{"max_time":189.0,"sim_time":0.0,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"stress_all":{"tests":{"otbn_stress_all":{"max_time":112.0,"sim_time":0.0,"passed":9,"total":10,"percent":90.0}},"passed":9,"total":10,"percent":90.0},"lc_escalation":{"tests":{"otbn_escalate":{"max_time":43.0,"sim_time":0.0,"passed":60,"total":60,"percent":100.0}},"passed":60,"total":60,"percent":100.0},"zero_state_err_urnd":{"tests":{"otbn_zero_state_err_urnd":{"max_time":11.0,"sim_time":0.0,"passed":4,"total":5,"percent":80.0}},"passed":4,"total":5,"percent":80.0},"sw_errs_fatal_chk":{"tests":{"otbn_sw_errs_fatal_chk":{"max_time":23.0,"sim_time":0.0,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"alert_test":{"tests":{"otbn_alert_test":{"max_time":6.0,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"otbn_intr_test":{"max_time":9.0,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"otbn_tl_errors":{"max_time":11.0,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"otbn_tl_errors":{"max_time":11.0,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"otbn_csr_hw_reset":{"max_time":10.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"otbn_csr_rw":{"max_time":8.0,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"otbn_csr_aliasing":{"max_time":9.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"otbn_same_csr_outstanding":{"max_time":9.0,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"otbn_csr_hw_reset":{"max_time":10.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"otbn_csr_rw":{"max_time":8.0,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"otbn_csr_aliasing":{"max_time":9.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"otbn_same_csr_outstanding":{"max_time":9.0,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":344,"total":346,"percent":99.42196531791907},"V2S":{"testpoints":{"mem_integrity":{"tests":{"otbn_imem_err":{"max_time":11.0,"sim_time":0.0,"passed":10,"total":10,"percent":100.0},"otbn_dmem_err":{"max_time":16.0,"sim_time":0.0,"passed":15,"total":15,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"internal_integrity":{"tests":{"otbn_alu_bignum_mod_err":{"max_time":20.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"otbn_controller_ispr_rdata_err":{"max_time":9.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"otbn_mac_bignum_acc_err":{"max_time":33.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"otbn_urnd_err":{"max_time":8.0,"sim_time":0.0,"passed":2,"total":2,"percent":100.0}},"passed":17,"total":17,"percent":100.0},"illegal_bus_access":{"tests":{"otbn_illegal_mem_acc":{"max_time":9.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"otbn_mem_gnt_acc_err":{"tests":{"otbn_mem_gnt_acc_err":{"max_time":7.0,"sim_time":0.0,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"otbn_non_sec_partial_wipe":{"tests":{"otbn_partial_wipe":{"max_time":12.0,"sim_time":0.0,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_intg_err":{"tests":{"otbn_tl_intg_err":{"max_time":36.0,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"otbn_sec_cm":{"max_time":333.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"passthru_mem_tl_intg_err":{"tests":{"otbn_passthru_mem_tl_intg_err":{"max_time":92.0,"sim_time":0.0,"passed":17,"total":20,"percent":85.0}},"passed":17,"total":20,"percent":85.0},"prim_fsm_check":{"tests":{"otbn_sec_cm":{"max_time":333.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"prim_count_check":{"tests":{"otbn_sec_cm":{"max_time":333.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_mem_scramble":{"tests":{"otbn_smoke":{"max_time":12.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_data_mem_integrity":{"tests":{"otbn_dmem_err":{"max_time":16.0,"sim_time":0.0,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"sec_cm_instruction_mem_integrity":{"tests":{"otbn_imem_err":{"max_time":11.0,"sim_time":0.0,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"otbn_tl_intg_err":{"max_time":36.0,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_controller_fsm_global_esc":{"tests":{"otbn_escalate":{"max_time":43.0,"sim_time":0.0,"passed":60,"total":60,"percent":100.0}},"passed":60,"total":60,"percent":100.0},"sec_cm_controller_fsm_local_esc":{"tests":{"otbn_imem_err":{"max_time":11.0,"sim_time":0.0,"passed":10,"total":10,"percent":100.0},"otbn_dmem_err":{"max_time":16.0,"sim_time":0.0,"passed":15,"total":15,"percent":100.0},"otbn_zero_state_err_urnd":{"max_time":11.0,"sim_time":0.0,"passed":4,"total":5,"percent":80.0},"otbn_illegal_mem_acc":{"max_time":9.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"otbn_sec_cm":{"max_time":333.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":39,"total":40,"percent":97.5},"sec_cm_controller_fsm_sparse":{"tests":{"otbn_sec_cm":{"max_time":333.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_scramble_key_sideload":{"tests":{"otbn_single":{"max_time":441.0,"sim_time":0.0,"passed":100,"total":100,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"sec_cm_scramble_ctrl_fsm_local_esc":{"tests":{"otbn_imem_err":{"max_time":11.0,"sim_time":0.0,"passed":10,"total":10,"percent":100.0},"otbn_dmem_err":{"max_time":16.0,"sim_time":0.0,"passed":15,"total":15,"percent":100.0},"otbn_zero_state_err_urnd":{"max_time":11.0,"sim_time":0.0,"passed":4,"total":5,"percent":80.0},"otbn_illegal_mem_acc":{"max_time":9.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"otbn_sec_cm":{"max_time":333.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":39,"total":40,"percent":97.5},"sec_cm_scramble_ctrl_fsm_sparse":{"tests":{"otbn_sec_cm":{"max_time":333.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_start_stop_ctrl_fsm_global_esc":{"tests":{"otbn_escalate":{"max_time":43.0,"sim_time":0.0,"passed":60,"total":60,"percent":100.0}},"passed":60,"total":60,"percent":100.0},"sec_cm_start_stop_ctrl_fsm_local_esc":{"tests":{"otbn_imem_err":{"max_time":11.0,"sim_time":0.0,"passed":10,"total":10,"percent":100.0},"otbn_dmem_err":{"max_time":16.0,"sim_time":0.0,"passed":15,"total":15,"percent":100.0},"otbn_zero_state_err_urnd":{"max_time":11.0,"sim_time":0.0,"passed":4,"total":5,"percent":80.0},"otbn_illegal_mem_acc":{"max_time":9.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"otbn_sec_cm":{"max_time":333.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":39,"total":40,"percent":97.5},"sec_cm_start_stop_ctrl_fsm_sparse":{"tests":{"otbn_sec_cm":{"max_time":333.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_data_reg_sw_sca":{"tests":{"otbn_single":{"max_time":441.0,"sim_time":0.0,"passed":100,"total":100,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"sec_cm_ctrl_redun":{"tests":{"otbn_ctrl_redun":{"max_time":10.0,"sim_time":0.0,"passed":12,"total":12,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"sec_cm_pc_ctrl_flow_redun":{"tests":{"otbn_pc_ctrl_flow_redun":{"max_time":8.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_rnd_bus_consistency":{"tests":{"otbn_rnd_sec_cm":{"max_time":33.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_rnd_rng_digest":{"tests":{"otbn_rnd_sec_cm":{"max_time":33.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_rf_base_data_reg_sw_integrity":{"tests":{"otbn_rf_base_intg_err":{"max_time":14.0,"sim_time":0.0,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sec_cm_rf_base_data_reg_sw_glitch_detect":{"tests":{"otbn_sec_cm":{"max_time":333.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_stack_wr_ptr_ctr_redun":{"tests":{"otbn_sec_cm":{"max_time":333.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_rf_bignum_data_reg_sw_integrity":{"tests":{"otbn_rf_bignum_intg_err":{"max_time":11.0,"sim_time":0.0,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sec_cm_rf_bignum_data_reg_sw_glitch_detect":{"tests":{"otbn_sec_cm":{"max_time":333.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_loop_stack_ctr_redun":{"tests":{"otbn_sec_cm":{"max_time":333.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_loop_stack_addr_integrity":{"tests":{"otbn_stack_addr_integ_chk":{"max_time":18.0,"sim_time":0.0,"passed":4,"total":5,"percent":80.0}},"passed":4,"total":5,"percent":80.0},"sec_cm_call_stack_addr_integrity":{"tests":{"otbn_stack_addr_integ_chk":{"max_time":18.0,"sim_time":0.0,"passed":4,"total":5,"percent":80.0}},"passed":4,"total":5,"percent":80.0},"sec_cm_start_stop_ctrl_state_consistency":{"tests":{"otbn_sec_wipe_err":{"max_time":10.0,"sim_time":0.0,"passed":7,"total":7,"percent":100.0}},"passed":7,"total":7,"percent":100.0},"sec_cm_data_mem_sec_wipe":{"tests":{"otbn_single":{"max_time":441.0,"sim_time":0.0,"passed":100,"total":100,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"sec_cm_instruction_mem_sec_wipe":{"tests":{"otbn_single":{"max_time":441.0,"sim_time":0.0,"passed":100,"total":100,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"sec_cm_data_reg_sw_sec_wipe":{"tests":{"otbn_single":{"max_time":441.0,"sim_time":0.0,"passed":100,"total":100,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"sec_cm_write_mem_integrity":{"tests":{"otbn_multi":{"max_time":189.0,"sim_time":0.0,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sec_cm_ctrl_flow_count":{"tests":{"otbn_single":{"max_time":441.0,"sim_time":0.0,"passed":100,"total":100,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"sec_cm_ctrl_flow_sca":{"tests":{"otbn_single":{"max_time":441.0,"sim_time":0.0,"passed":100,"total":100,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"sec_cm_data_mem_sw_noaccess":{"tests":{"otbn_sw_no_acc":{"max_time":21.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_key_sideload":{"tests":{"otbn_single":{"max_time":441.0,"sim_time":0.0,"passed":100,"total":100,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"sec_cm_tlul_fifo_ctr_redun":{"tests":{"otbn_sec_cm":{"max_time":333.0,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0}},"passed":1311,"total":1319,"percent":99.39347990902199},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"otbn_stress_all_with_rand_reset":{"max_time":459.0,"sim_time":0.0,"passed":2,"total":10,"percent":20.0}},"passed":2,"total":10,"percent":20.0}},"passed":2,"total":10,"percent":20.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"otbn_smoke_vectorized":{"max_time":8.0,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"coverage":{"code":{"block":99.48,"line_statement":99.65,"branch":93.41,"condition_expression":null,"toggle":93.42,"fsm":100.0},"assertion":97.06,"functional":100.0},"cov_report_page":"/nightly/current_run/scratch/master/otbn-sim-xcelium/cov_report/index.html","failed_jobs":{"buckets":{"UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.":[{"name":"otbn_passthru_mem_tl_intg_err","qual_name":"4.otbn_passthru_mem_tl_intg_err.105806761424324737962731671140337517767026836007554098589979555499282297579481","seed":105806761424324737962731671140337517767026836007554098589979555499282297579481,"line":101,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/4.otbn_passthru_mem_tl_intg_err/latest/run.log","log_context":["UVM_FATAL @  62600624 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.\n","UVM_INFO @  62600624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"6.otbn_stress_all_with_rand_reset.108646086024987404565497672631415585058914628763021084176786915106693241873294","seed":108646086024987404565497672631415585058914628763021084176786915106693241873294,"line":247,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 233610836 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.\n","UVM_INFO @ 233610836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.":[{"name":"otbn_passthru_mem_tl_intg_err","qual_name":"14.otbn_passthru_mem_tl_intg_err.113852988706290962176810252563804764862105127143787868975825324159934351196401","seed":113852988706290962176810252563804764862105127143787868975825324159934351196401,"line":96,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/14.otbn_passthru_mem_tl_intg_err/latest/run.log","log_context":["UVM_FATAL @  18677297 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.\n","UVM_INFO @  18677297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_passthru_mem_tl_intg_err","qual_name":"17.otbn_passthru_mem_tl_intg_err.68575085251807364891165487105692901534130746002163994106127516984708291332328","seed":68575085251807364891165487105692901534130746002163994106127516984708291332328,"line":86,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/17.otbn_passthru_mem_tl_intg_err/latest/run.log","log_context":["UVM_FATAL @  19626791 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.\n","UVM_INFO @  19626791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"otbn_stress_all_with_rand_reset","qual_name":"0.otbn_stress_all_with_rand_reset.73589277758750790251858151610378178574130503377190757384055187477331040924471","seed":73589277758750790251858151610378178574130503377190757384055187477331040924471,"line":246,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 313745838 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 313745838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"1.otbn_stress_all_with_rand_reset.6592798173625774570703745254248642481211252120895141590462487160496179781012","seed":6592798173625774570703745254248642481211252120895141590462487160496179781012,"line":210,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 330738402 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 330738402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"2.otbn_stress_all_with_rand_reset.43861964812367104326112197535424594365710755890234683169512645817506676361845","seed":43861964812367104326112197535424594365710755890234683169512645817506676361845,"line":370,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6253820993 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 6253820993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"3.otbn_stress_all_with_rand_reset.69693736680319273503167568546666064577118965485433143534918101369284164586074","seed":69693736680319273503167568546666064577118965485433143534918101369284164586074,"line":159,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 755162730 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 755162730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"5.otbn_stress_all_with_rand_reset.18272274900298623107123028352058925968426212349370902462621591899783565281797","seed":18272274900298623107123028352058925968426212349370902462621591899783565281797,"line":154,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 129212307 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 129212307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"8.otbn_stress_all_with_rand_reset.45037581181712174443845128724091091746486642595319381406369876248583753684508","seed":45037581181712174443845128724091091746486642595319381406369876248583753684508,"line":700,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5787414535 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5787414535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed":[{"name":"otbn_stack_addr_integ_chk","qual_name":"0.otbn_stack_addr_integ_chk.70099458714084234828941764162152988262968042167383909587186626905432311247293","seed":70099458714084234828941764162152988262968042167383909587186626905432311247293,"line":130,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log","log_context":["xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 96871772 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed \n","xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 96871772 PS) Assertion tb.model_if.NoModelErrs has failed \n","UVM_ERROR @  96871772 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A\n","UVM_INFO @  96871772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"otbn_zero_state_err_urnd","qual_name":"1.otbn_zero_state_err_urnd.101194704821826927030937811512306896167904115483882148146204149529013421251160","seed":101194704821826927030937811512306896167904115483882148146204149529013421251160,"line":111,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_zero_state_err_urnd/latest/run.log","log_context":["xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 21750525 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed \n","UVM_ERROR @  21750525 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A\n","UVM_INFO @  21750525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)":[{"name":"otbn_stress_all_with_rand_reset","qual_name":"7.otbn_stress_all_with_rand_reset.101618565312214132048483835237070278413500989768889650680095886617417150126164","seed":101618565312214132048483835237070278413500989768889650680095886617417150126164,"line":278,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 6991030913 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)  \n","UVM_INFO @ 6991030913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job returned non-zero exit code":[{"name":"otbn_stress_all","qual_name":"9.otbn_stress_all.64717705649238738189782037993577218059961433583666073238678833417857592349209","seed":64717705649238738189782037993577218059961433583666073238678833417857592349209,"line":null,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/9.otbn_stress_all/latest/run.log","log_context":["                        ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 122, in _gen_loop_head\n","    enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)\n","                             ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 67, in _pick_bodysize\n","    assert bodysize is not None\n","           ^^^^^^^^^^^^^^^^^^^^\n","AssertionError\n","ninja: build stopped: subcommand failed.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1\n"]}]}},"passed":1849,"total":1867,"percent":99.03588644884842}