{"block":{"name":"rstmgr_cnsty_chk","variant":null,"commit":"3ba6465de32edf4612bd1c0fa13f7e4cb5f4a7da","commit_short":"3ba6465","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/3ba6465de32edf4612bd1c0fa13f7e4cb5f4a7da","revision_info":"GitHub Revision: [`3ba6465`](https://github.com/lowrisc/opentitan/tree/3ba6465de32edf4612bd1c0fa13f7e4cb5f4a7da)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-03T17:01:04Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_darjeeling/ip_autogen/rstmgr/dv/data/rstmgr_cnsty_chk_testplan.html","stages":{"unmapped":{"testpoints":{"Unmapped":{"tests":{"rstmgr_cnsty_chk_test":{"max_time":3.76,"sim_time":0.0,"passed":7,"total":10,"percent":70.0}},"passed":7,"total":10,"percent":70.0}},"passed":7,"total":10,"percent":70.0}},"coverage":{"code":{"block":null,"line_statement":98.41,"branch":98.31,"condition_expression":86.21,"toggle":100.0,"fsm":92.31},"assertion":100.0,"functional":null},"cov_report_page":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *))":[{"name":"rstmgr_cnsty_chk_test","qual_name":"5.rstmgr_cnsty_chk_test.77626042261780074722648189070892278543333930079312103884704118900191477482828","seed":77626042261780074722648189070892278543333930079312103884704118900191477482828,"line":175,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/5.rstmgr_cnsty_chk_test/latest/run.log","log_context":["UVM_ERROR @ 1941057526 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == 0))  \n","UVM_INFO @ 1960577526 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16\n","UVM_INFO @ 1980097526 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16\n","UVM_INFO @ 1999617526 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16\n","UVM_INFO @ 2019137526 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16\n"]},{"name":"rstmgr_cnsty_chk_test","qual_name":"8.rstmgr_cnsty_chk_test.52235995002338670667741349629887667180700415236951994253364081871217954137438","seed":52235995002338670667741349629887667180700415236951994253364081871217954137438,"line":175,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/8.rstmgr_cnsty_chk_test/latest/run.log","log_context":["UVM_ERROR @ 1877581420 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == 0))  \n","UVM_INFO @ 1896461420 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16\n","UVM_INFO @ 1915341420 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16\n","UVM_INFO @ 1934221420 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16\n","UVM_INFO @ 1953101420 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16\n"]},{"name":"rstmgr_cnsty_chk_test","qual_name":"9.rstmgr_cnsty_chk_test.51523389022794076232529876743902277288238044888790578304101534521785431767394","seed":51523389022794076232529876743902277288238044888790578304101534521785431767394,"line":175,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/9.rstmgr_cnsty_chk_test/latest/run.log","log_context":["UVM_ERROR @ 1925193151 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == 0))  \n","UVM_INFO @ 1944553151 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16\n","UVM_INFO @ 1963913151 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16\n","UVM_INFO @ 1983273151 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16\n","UVM_INFO @ 2002633151 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16\n"]}]}},"passed":7,"total":10,"percent":70.0}