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---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"2.rv_dm_delayed_resp_sba_tl_access.4413600458585104982927470888570041157030992568306816291273821871354444886386","seed":4413600458585104982927470888570041157030992568306816291273821871354444886386,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"2.rv_dm_bad_sba_tl_access.26464696346538669457660123853397018212621032074375161609118799720712559624933","seed":26464696346538669457660123853397018212621032074375161609118799720712559624933,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"2.rv_dm_autoincr_sba_tl_access.31198321729057063703890569820961193474069356822200902426681788635908824180668","seed":31198321729057063703890569820961193474069356822200902426681788635908824180668,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"3.rv_dm_sba_tl_access.19628893917134764695693097655600295951314948717717623989901159274474138677155","seed":19628893917134764695693097655600295951314948717717623989901159274474138677155,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"3.rv_dm_delayed_resp_sba_tl_access.94559703584165945271072267994150986006069209728783223791525674349994041864515","seed":94559703584165945271072267994150986006069209728783223791525674349994041864515,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"3.rv_dm_bad_sba_tl_access.35881552683171307811292794149540244606077583142924659633366969007671471093324","seed":35881552683171307811292794149540244606077583142924659633366969007671471093324,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"3.rv_dm_autoincr_sba_tl_access.96410459830549642192287445641784892016659577840418096728541775212437653904144","seed":96410459830549642192287445641784892016659577840418096728541775212437653904144,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"4.rv_dm_sba_tl_access.58459143503244481774790222384796351994826363122218379165523176260834814097310","seed":58459143503244481774790222384796351994826363122218379165523176260834814097310,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"4.rv_dm_delayed_resp_sba_tl_access.112974834609246364915164788217079111696236085913479541818513463970474955110077","seed":112974834609246364915164788217079111696236085913479541818513463970474955110077,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"4.rv_dm_bad_sba_tl_access.103134986888361905929861637806686723245442811705500327124549899714065551415369","seed":103134986888361905929861637806686723245442811705500327124549899714065551415369,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"4.rv_dm_autoincr_sba_tl_access.12249424436302319238537562297142605865631972450809858138421462593214827822432","seed":12249424436302319238537562297142605865631972450809858138421462593214827822432,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"5.rv_dm_sba_tl_access.1513055695409160051156160183369971368811049262463238335754646985217971652067","seed":1513055695409160051156160183369971368811049262463238335754646985217971652067,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"5.rv_dm_delayed_resp_sba_tl_access.105536973698512335919973559345417158695906873902389231422665602731481404400351","seed":105536973698512335919973559345417158695906873902389231422665602731481404400351,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"5.rv_dm_bad_sba_tl_access.104326656954757681152764252221650748481462208029739118368413206617078958669158","seed":104326656954757681152764252221650748481462208029739118368413206617078958669158,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"5.rv_dm_autoincr_sba_tl_access.73470110343364755734574972296036877034421063813201735691368682374954606137764","seed":73470110343364755734574972296036877034421063813201735691368682374954606137764,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"6.rv_dm_sba_tl_access.98813185754491164784976620615405293034513206576690842905382954653050464412171","seed":98813185754491164784976620615405293034513206576690842905382954653050464412171,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"6.rv_dm_delayed_resp_sba_tl_access.110388634667553436950775326926056527240265942026932832370817800557656315766323","seed":110388634667553436950775326926056527240265942026932832370817800557656315766323,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"6.rv_dm_bad_sba_tl_access.96166431739251075767824263660179023289035146614113019656571764515016274283876","seed":96166431739251075767824263660179023289035146614113019656571764515016274283876,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"6.rv_dm_autoincr_sba_tl_access.97428575946722863576214079591032864092684838016839859491951764631043837609480","seed":97428575946722863576214079591032864092684838016839859491951764631043837609480,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"6.rv_dm_stress_all.41405224276682146164932980699116196291188340062848070267420915884606415078533","seed":41405224276682146164932980699116196291188340062848070267420915884606415078533,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_stress_all/latest/run.log","log_context":["UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"7.rv_dm_sba_tl_access.41102337593031423314310947134078900251504885108887952679259403011361113857912","seed":41102337593031423314310947134078900251504885108887952679259403011361113857912,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"7.rv_dm_delayed_resp_sba_tl_access.47963736961181525349646225911529621279325133877200496917072353853990612539238","seed":47963736961181525349646225911529621279325133877200496917072353853990612539238,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"7.rv_dm_bad_sba_tl_access.87839893727052163531662794616786721728377340160036300398826229846466177696698","seed":87839893727052163531662794616786721728377340160036300398826229846466177696698,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"7.rv_dm_autoincr_sba_tl_access.28529146663998283116644232432081633153615985210931876778594504956729428364880","seed":28529146663998283116644232432081633153615985210931876778594504956729428364880,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"8.rv_dm_sba_tl_access.10198669519634319850848743407886473471039576831908542905398806778022730233419","seed":10198669519634319850848743407886473471039576831908542905398806778022730233419,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"8.rv_dm_delayed_resp_sba_tl_access.91429312657531883334757584562746696073845157221752529365285544012948052400514","seed":91429312657531883334757584562746696073845157221752529365285544012948052400514,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"8.rv_dm_bad_sba_tl_access.66839886362411292334810546203943046289484806450275015725130609360637433542435","seed":66839886362411292334810546203943046289484806450275015725130609360637433542435,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"8.rv_dm_autoincr_sba_tl_access.15599327311003884039409879317137482808048295588074782929832714493840863823737","seed":15599327311003884039409879317137482808048295588074782929832714493840863823737,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"9.rv_dm_sba_tl_access.2087099827649432477064542431849684081736578363889525363996478652456116878673","seed":2087099827649432477064542431849684081736578363889525363996478652456116878673,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"9.rv_dm_delayed_resp_sba_tl_access.61330524362617348998249376653645109517307916961278103308270360978344880056199","seed":61330524362617348998249376653645109517307916961278103308270360978344880056199,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"9.rv_dm_bad_sba_tl_access.77679445361575640698917561065098048373032269308546960417592436976757212793935","seed":77679445361575640698917561065098048373032269308546960417592436976757212793935,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"9.rv_dm_autoincr_sba_tl_access.14260540164133685575812526034247736074659017772876419216380446518375340250080","seed":14260540164133685575812526034247736074659017772876419216380446518375340250080,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"10.rv_dm_sba_tl_access.11836712920337185832554472849750364866806043426643601360049484597283929793508","seed":11836712920337185832554472849750364866806043426643601360049484597283929793508,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/10.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"10.rv_dm_delayed_resp_sba_tl_access.13083401820994178241852110407757466808648905913528257496062997630973529375916","seed":13083401820994178241852110407757466808648905913528257496062997630973529375916,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/10.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"10.rv_dm_bad_sba_tl_access.13232237487411417537139947890479696269790096095496548465081799279357237425360","seed":13232237487411417537139947890479696269790096095496548465081799279357237425360,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/10.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"10.rv_dm_autoincr_sba_tl_access.15359065019193042014249973243329964391608150254804796720197378661261661448043","seed":15359065019193042014249973243329964391608150254804796720197378661261661448043,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"11.rv_dm_sba_tl_access.43664082606675893500714435381319624197754410916049337628571783830650167184648","seed":43664082606675893500714435381319624197754410916049337628571783830650167184648,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"11.rv_dm_delayed_resp_sba_tl_access.31837663937783591331543401529075093998882428369606845545178517679442114420802","seed":31837663937783591331543401529075093998882428369606845545178517679442114420802,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/11.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"11.rv_dm_bad_sba_tl_access.86332953398914982105778144405208794370602805013912103716915197998371130922307","seed":86332953398914982105778144405208794370602805013912103716915197998371130922307,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/11.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"11.rv_dm_autoincr_sba_tl_access.59972690452272693235867883490822283956923274505676836560658484860341749721404","seed":59972690452272693235867883490822283956923274505676836560658484860341749721404,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"11.rv_dm_stress_all.14049338643450369258619081274171421519168125365580652197543990876751481114036","seed":14049338643450369258619081274171421519168125365580652197543990876751481114036,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/11.rv_dm_stress_all/latest/run.log","log_context":["UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"12.rv_dm_sba_tl_access.57979647185495904132522004254737869913021518273515350193322716259178871061141","seed":57979647185495904132522004254737869913021518273515350193322716259178871061141,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/12.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"12.rv_dm_delayed_resp_sba_tl_access.34826008973614737705818806045352074873928672161589138584523001579500719217667","seed":34826008973614737705818806045352074873928672161589138584523001579500719217667,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/12.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"12.rv_dm_bad_sba_tl_access.84487288787276455508642420588787708229118982563200914984336948046425240106071","seed":84487288787276455508642420588787708229118982563200914984336948046425240106071,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"12.rv_dm_autoincr_sba_tl_access.35773966437867571513585049338410296818970806548040476531622551582814175324999","seed":35773966437867571513585049338410296818970806548040476531622551582814175324999,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"13.rv_dm_sba_tl_access.74343252242853443020367628492813867453130572343142342158704084792998135356100","seed":74343252242853443020367628492813867453130572343142342158704084792998135356100,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/13.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"13.rv_dm_delayed_resp_sba_tl_access.38644012296414356626497425110558093535107303549941890701103014677229602807361","seed":38644012296414356626497425110558093535107303549941890701103014677229602807361,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/13.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"13.rv_dm_bad_sba_tl_access.94109007328138972625474887502501076372122329462977899738407580178300015485486","seed":94109007328138972625474887502501076372122329462977899738407580178300015485486,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/13.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"13.rv_dm_autoincr_sba_tl_access.52069461786155581639113435534215562582881215535216560940826162667614579157472","seed":52069461786155581639113435534215562582881215535216560940826162667614579157472,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"14.rv_dm_sba_tl_access.8203113164545266175356393675636784538230155097672961421475215247773196311999","seed":8203113164545266175356393675636784538230155097672961421475215247773196311999,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/14.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"14.rv_dm_delayed_resp_sba_tl_access.75558623023236548527131006689112064754558043144249161271419480309002009096454","seed":75558623023236548527131006689112064754558043144249161271419480309002009096454,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/14.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"14.rv_dm_bad_sba_tl_access.74960268984764835927990311182390893370673355606986522203913277349322336901610","seed":74960268984764835927990311182390893370673355606986522203913277349322336901610,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/14.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"14.rv_dm_autoincr_sba_tl_access.41388827886583134296004591100227655599994614172613984089137602895529997576182","seed":41388827886583134296004591100227655599994614172613984089137602895529997576182,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"15.rv_dm_sba_tl_access.20657445971888248444134506745306855276612908611676857481877585980327275530662","seed":20657445971888248444134506745306855276612908611676857481877585980327275530662,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/15.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"15.rv_dm_delayed_resp_sba_tl_access.62912438838556888080132290634784947886734575457065345376746946947979156854052","seed":62912438838556888080132290634784947886734575457065345376746946947979156854052,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/15.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"15.rv_dm_bad_sba_tl_access.115666936141803938601920840901220410648983505569236802240223888055112914192528","seed":115666936141803938601920840901220410648983505569236802240223888055112914192528,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"15.rv_dm_autoincr_sba_tl_access.93059998437210015155384737751420753752346112551426696628397639872611352636611","seed":93059998437210015155384737751420753752346112551426696628397639872611352636611,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"16.rv_dm_sba_tl_access.21241617783781487586593592413901742023026133698308733255956819025655183697260","seed":21241617783781487586593592413901742023026133698308733255956819025655183697260,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/16.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"16.rv_dm_delayed_resp_sba_tl_access.11235482809951674250285111174952737573832550644622197084109165130128479818711","seed":11235482809951674250285111174952737573832550644622197084109165130128479818711,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/16.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"16.rv_dm_bad_sba_tl_access.17304949402836325949608919631807735285607395400788867478165740653565413940419","seed":17304949402836325949608919631807735285607395400788867478165740653565413940419,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/16.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"16.rv_dm_autoincr_sba_tl_access.112801812150285630600765209877280162040755801444100498614127515045761657400920","seed":112801812150285630600765209877280162040755801444100498614127515045761657400920,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/16.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"17.rv_dm_sba_tl_access.105034989171154428218232441021160110628420156920739459366583908356505756790015","seed":105034989171154428218232441021160110628420156920739459366583908356505756790015,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/17.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"17.rv_dm_delayed_resp_sba_tl_access.31436523542289568607600326916088971833098103029762000798255647353665416856344","seed":31436523542289568607600326916088971833098103029762000798255647353665416856344,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/17.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"17.rv_dm_bad_sba_tl_access.94542106006369152978371785428936745517459965317640851576502212400597789125932","seed":94542106006369152978371785428936745517459965317640851576502212400597789125932,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/17.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"17.rv_dm_autoincr_sba_tl_access.75045702658133768640602911272890589270642440622573634307238178119674420360596","seed":75045702658133768640602911272890589270642440622573634307238178119674420360596,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"18.rv_dm_sba_tl_access.1036233697936725990158245261796348791713833675672453886138649256113723470094","seed":1036233697936725990158245261796348791713833675672453886138649256113723470094,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/18.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"18.rv_dm_delayed_resp_sba_tl_access.80923061590514720231944522883892837031196023966690436881903704566023377701312","seed":80923061590514720231944522883892837031196023966690436881903704566023377701312,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/18.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"18.rv_dm_bad_sba_tl_access.11529957832033480005995027960253791688886535162510822760990154304075352670498","seed":11529957832033480005995027960253791688886535162510822760990154304075352670498,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/18.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"18.rv_dm_autoincr_sba_tl_access.7169382773398414132026166406843434518905982624077630090870294515716800138078","seed":7169382773398414132026166406843434518905982624077630090870294515716800138078,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"19.rv_dm_sba_tl_access.33691406292610179031504669925059171585148557790109257549181081962772863601735","seed":33691406292610179031504669925059171585148557790109257549181081962772863601735,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/19.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"19.rv_dm_delayed_resp_sba_tl_access.96132585438232467216925792242848247734882978843590150582192531325311499098230","seed":96132585438232467216925792242848247734882978843590150582192531325311499098230,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/19.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"19.rv_dm_bad_sba_tl_access.18727892608742337800699359171693969191427708637425646199571195557055426870391","seed":18727892608742337800699359171693969191427708637425646199571195557055426870391,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/19.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"19.rv_dm_autoincr_sba_tl_access.15307149248855229017656630485232917985641870004809065649769741279962120393223","seed":15307149248855229017656630485232917985641870004809065649769741279962120393223,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/19.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"34.rv_dm_stress_all.82298492864002959434319593599667166191809238088667633299655546870345696115144","seed":82298492864002959434319593599667166191809238088667633299655546870345696115144,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/34.rv_dm_stress_all/latest/run.log","log_context":["UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"37.rv_dm_stress_all.25910118586926003909331795694437515567908740197966534191325306963609499044103","seed":25910118586926003909331795694437515567908740197966534191325306963609499044103,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/37.rv_dm_stress_all/latest/run.log","log_context":["UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"45.rv_dm_stress_all.27094335005998770551893783319840091554012312041751261258145332207249807425636","seed":27094335005998770551893783319840091554012312041751261258145332207249807425636,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/45.rv_dm_stress_all/latest/run.log","log_context":["UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == *'b* (* [*] vs * [*])":[{"name":"rv_dm_mem_tl_access_resuming","qual_name":"0.rv_dm_mem_tl_access_resuming.22642066834430818117515451791818694271839796115987284461303944278311922026157","seed":22642066834430818117515451791818694271839796115987284461303944278311922026157,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest/run.log","log_context":["UVM_ERROR @ 306402559 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 306402559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"0.rv_dm_stress_all.72202856646714764593698860266541460918945481955310392272685310725167704555963","seed":72202856646714764593698860266541460918945481955310392272685310725167704555963,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 345190468 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 345190468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_mem_tl_access_resuming","qual_name":"1.rv_dm_mem_tl_access_resuming.8313585643475648267726626487643699714620263261708560452337913369579999121244","seed":8313585643475648267726626487643699714620263261708560452337913369579999121244,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest/run.log","log_context":["UVM_ERROR @ 119230476 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 119230476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"1.rv_dm_stress_all_with_rand_reset.53398660585269808399696179310279782926084012495626991779384984140096643118270","seed":53398660585269808399696179310279782926084012495626991779384984140096643118270,"line":117,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1435821376 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1435821376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"5.rv_dm_stress_all_with_rand_reset.83730492666026264288339095523526815792374480543625820989683733607108573700539","seed":83730492666026264288339095523526815792374480543625820989683733607108573700539,"line":91,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1103962452 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1103962452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"8.rv_dm_stress_all_with_rand_reset.47458602063414489183229388195510181875551050420643612969951332889976612607457","seed":47458602063414489183229388195510181875551050420643612969951332889976612607457,"line":159,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4484520360 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 4484520360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"10.rv_dm_stress_all.21779715513152423012396685262606088035776019905155674857789478109449171126554","seed":21779715513152423012396685262606088035776019905155674857789478109449171126554,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/10.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 148559352 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 148559352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"17.rv_dm_stress_all.67617067117457492151996272245420757308024021946382482754972936332684913671529","seed":67617067117457492151996272245420757308024021946382482754972936332684913671529,"line":92,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/17.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 5282372592 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 5282372592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"25.rv_dm_stress_all.69540100886859208699173761751959403846281765215747243440713882994959501091697","seed":69540100886859208699173761751959403846281765215747243440713882994959501091697,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/25.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 260399009 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 260399009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"29.rv_dm_stress_all.5489507345385900502944808465679733920374278013714454841730360448910658047935","seed":5489507345385900502944808465679733920374278013714454841730360448910658047935,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/29.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 144519163 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 144519163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"43.rv_dm_stress_all.54270938558431955307474933131434952995616489594325069344880691805570284559789","seed":54270938558431955307474933131434952995616489594325069344880691805570284559789,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/43.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 5015005949 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 5015005949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"47.rv_dm_stress_all.68252556038356891478763953826375276435618395882143258694716902208754905647398","seed":68252556038356891478763953826375276435618395882143258694716902208754905647398,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/47.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 779265826 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 779265826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [*] vs * [*])":[{"name":"rv_dm_hart_unavail","qual_name":"0.rv_dm_hart_unavail.104534878176251888178059391896617623946017492287938393851776723076860792433166","seed":104534878176251888178059391896617623946017492287938393851776723076860792433166,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest/run.log","log_context":["UVM_ERROR @ 101289686 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 101289686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"0.rv_dm_stress_all_with_rand_reset.99080437608681831340564539101545993676166083369694975720699649268904344065493","seed":99080437608681831340564539101545993676166083369694975720699649268904344065493,"line":108,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1920749069 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1920749069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_hart_unavail","qual_name":"1.rv_dm_hart_unavail.6431210876050688519803085013781362114121341845222433155371909779506098921597","seed":6431210876050688519803085013781362114121341845222433155371909779506098921597,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_hart_unavail/latest/run.log","log_context":["UVM_ERROR @  85148874 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  85148874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"1.rv_dm_stress_all.78773136132655367330137355925421827871183676427244924380132045744778863499524","seed":78773136132655367330137355925421827871183676427244924380132045744778863499524,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 968770057 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 968770057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_hart_unavail","qual_name":"2.rv_dm_hart_unavail.97305300591950977434977196258406935704460019192242329986046418559941787966022","seed":97305300591950977434977196258406935704460019192242329986046418559941787966022,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_hart_unavail/latest/run.log","log_context":["UVM_ERROR @  57384891 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  57384891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_hart_unavail","qual_name":"3.rv_dm_hart_unavail.21492631500809022882803007415874511691246120177307932070645259263705512604893","seed":21492631500809022882803007415874511691246120177307932070645259263705512604893,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_hart_unavail/latest/run.log","log_context":["UVM_ERROR @  69788383 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  69788383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"3.rv_dm_stress_all_with_rand_reset.98823110939509690662207997761159223012231986185252832897856633090890477564719","seed":98823110939509690662207997761159223012231986185252832897856633090890477564719,"line":81,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 473175634 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 473175634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_hart_unavail","qual_name":"4.rv_dm_hart_unavail.115380399685112150872112969498454490350610307480105932604310580349176814993678","seed":115380399685112150872112969498454490350610307480105932604310580349176814993678,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_hart_unavail/latest/run.log","log_context":["UVM_ERROR @  61612800 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  61612800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"5.rv_dm_stress_all.62180107738883475309152537931703624996666674244174250126470277496080391077833","seed":62180107738883475309152537931703624996666674244174250126470277496080391077833,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @  89087249 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  89087249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"7.rv_dm_stress_all_with_rand_reset.42719619533569306150170214027045604560040423758734008473529708029493702020771","seed":42719619533569306150170214027045604560040423758734008473529708029493702020771,"line":81,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 310200121 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 310200121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"12.rv_dm_stress_all.21285415398304335173204870950362874992702406376446652678993123270981543997085","seed":21285415398304335173204870950362874992702406376446652678993123270981543997085,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/12.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 328686416 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 328686416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"13.rv_dm_stress_all.79414922263846543747513528474508376914685101571908373303065231209015924200689","seed":79414922263846543747513528474508376914685101571908373303065231209015924200689,"line":82,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/13.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 3089060053 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 3089060053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"24.rv_dm_stress_all.85167997674995938767197437685580670260277149868652117971594650669793350306901","seed":85167997674995938767197437685580670260277149868652117971594650669793350306901,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/24.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 533139726 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 533139726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"28.rv_dm_stress_all.90247065752419910064287258409946989349196803992076192110347272543274931411426","seed":90247065752419910064287258409946989349196803992076192110347272543274931411426,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/28.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 404494404 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 404494404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"32.rv_dm_stress_all.68293210081081898270600404284917311793617063792305811104577324550791263602996","seed":68293210081081898270600404284917311793617063792305811104577324550791263602996,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/32.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @  76334737 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  76334737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"33.rv_dm_stress_all.52730415782603186656599444888357541736793484103407894764711468464295925343365","seed":52730415782603186656599444888357541736793484103407894764711468464295925343365,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/33.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 517209228 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 517209228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"42.rv_dm_stress_all.106640262977874577845982145620390665589721475173252192270402931616580820753711","seed":106640262977874577845982145620390665589721475173252192270402931616580820753711,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/42.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 344632638 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 344632638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*])":[{"name":"rv_dm_jtag_dmi_debug_disabled","qual_name":"0.rv_dm_jtag_dmi_debug_disabled.109883910135642525159914326541183433530381899708745071657235572166877202912931","seed":109883910135642525159914326541183433530381899708745071657235572166877202912931,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log","log_context":["UVM_ERROR @ 109889992 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2856293545 [0xaa3f94a9] vs 0 [0x0]) \n","UVM_INFO @ 109889992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_jtag_dmi_debug_disabled","qual_name":"1.rv_dm_jtag_dmi_debug_disabled.28168036085585480169534174466322635079385871476129631762576038825375086187165","seed":28168036085585480169534174466322635079385871476129631762576038825375086187165,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest/run.log","log_context":["UVM_ERROR @ 356834902 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (356189916 [0x153b06dc] vs 0 [0x0]) \n","UVM_INFO @ 356834902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"3.rv_dm_stress_all.94230293165977480292796023985600946998185006469306334575867283871603574611352","seed":94230293165977480292796023985600946998185006469306334575867283871603574611352,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 566227769 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (499253017 [0x1dc1ff19] vs 0 [0x0]) \n","UVM_INFO @ 566227769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"4.rv_dm_stress_all.201867958923179532942698541132209604845762150336809316765352696266545328920","seed":201867958923179532942698541132209604845762150336809316765352696266545328920,"line":82,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 3193442903 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3811514390 [0xe32f1816] vs 0 [0x0]) \n","UVM_INFO @ 3193442903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"6.rv_dm_stress_all_with_rand_reset.110664105253824384734123636743691653746414656106211028431707177562076714356817","seed":110664105253824384734123636743691653746414656106211028431707177562076714356817,"line":107,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3039997445 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (4265239568 [0xfe3a6410] vs 0 [0x0]) \n","UVM_INFO @ 3039997445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"9.rv_dm_stress_all.104185929963594315892593164327283948350788064842331779430033965225619568117880","seed":104185929963594315892593164327283948350788064842331779430033965225619568117880,"line":82,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 7829065920 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3288039976 [0xc3fb8228] vs 0 [0x0]) \n","UVM_INFO @ 7829065920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"18.rv_dm_stress_all.105397391978194099490433160984745413821858000467128999702067041002868381072386","seed":105397391978194099490433160984745413821858000467128999702067041002868381072386,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/18.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 894624435 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (74257393 [0x46d13f1] vs 0 [0x0]) \n","UVM_INFO @ 894624435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"19.rv_dm_stress_all.43178039327198705955117153845290503052125921829678036481319931309547810646072","seed":43178039327198705955117153845290503052125921829678036481319931309547810646072,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/19.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 830342380 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1990983602 [0x76abffb2] vs 0 [0x0]) \n","UVM_INFO @ 830342380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"20.rv_dm_stress_all.46917697067595416175214712064205284378962612853611476736761442455047342292892","seed":46917697067595416175214712064205284378962612853611476736761442455047342292892,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/20.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 2662787318 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1654393120 [0x629c0920] vs 0 [0x0]) \n","UVM_INFO @ 2662787318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"22.rv_dm_stress_all.42771345469969497192352143733604826713658055123978996218678454286467219949590","seed":42771345469969497192352143733604826713658055123978996218678454286467219949590,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/22.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 4942823248 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3240525153 [0xc1267d61] vs 0 [0x0]) \n","UVM_INFO @ 4942823248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"26.rv_dm_stress_all.110504551160083975948384741085799611203221020115318114026593798241171552190382","seed":110504551160083975948384741085799611203221020115318114026593798241171552190382,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/26.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 435282764 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (745298921 [0x2c6c5be9] vs 0 [0x0]) \n","UVM_INFO @ 435282764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"27.rv_dm_stress_all.14248270839826911052050209968115732699986735947768230943233128728731820129037","seed":14248270839826911052050209968115732699986735947768230943233128728731820129037,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/27.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 453956320 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (512662025 [0x1e8e9a09] vs 0 [0x0]) \n","UVM_INFO @ 453956320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"38.rv_dm_stress_all.6803788602394511536145645822209163899320036809880943241378547742124528226271","seed":6803788602394511536145645822209163899320036809880943241378547742124528226271,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/38.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 630362431 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (967104005 [0x39a4d605] vs 0 [0x0]) \n","UVM_INFO @ 630362431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"39.rv_dm_stress_all.101862333162730962300957110560846803325929900741733467803876119933244495594383","seed":101862333162730962300957110560846803325929900741733467803876119933244495594383,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/39.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 232098681 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1944091784 [0x73e07c88] vs 0 [0x0]) \n","UVM_INFO @ 232098681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"46.rv_dm_stress_all.110232502993315836739371110094271874627172694755921660269901716050823674897567","seed":110232502993315836739371110094271874627172694755921660269901716050823674897567,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/46.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 532135686 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (4031407234 [0xf04a6482] vs 0 [0x0]) \n","UVM_INFO @ 532135686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"48.rv_dm_stress_all.19696616631138214507433834559969511697965818141141919449202729387530452431744","seed":19696616631138214507433834559969511697965818141141919449202729387530452431744,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/48.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 107015463 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2637018636 [0x9d2db60c] vs 0 [0x0]) \n","UVM_INFO @ 107015463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (cip_base_vseq.sv:1170) [rv_dm_common_vseq] Check failed (vseq_done)":[{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"2.rv_dm_stress_all_with_rand_reset.65212318555256890143517321796996369862344921973578817908329645670655063448635","seed":65212318555256890143517321796996369862344921973578817908329645670655063448635,"line":106,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 662060293 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)  \n","UVM_INFO @ 662060293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"4.rv_dm_stress_all_with_rand_reset.38120157758077455730144755215086055602585194811462633114524118293507913538020","seed":38120157758077455730144755215086055602585194811462633114524118293507913538020,"line":91,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 930081637 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)  \n","UVM_INFO @ 930081637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"9.rv_dm_stress_all_with_rand_reset.20382397885051841471252190621610984422767428004549139471588825835565583429157","seed":20382397885051841471252190621610984422767428004549139471588825835565583429157,"line":125,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 3665648668 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)  \n","UVM_INFO @ 3665648668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [*] vs * [*])":[{"name":"rv_dm_buffered_enable","qual_name":"3.rv_dm_buffered_enable.33243903396672857344062544586593642983374597202467639929585412557278077601375","seed":33243903396672857344062544586593642983374597202467639929585412557278077601375,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_buffered_enable/latest/run.log","log_context":["UVM_ERROR @ 108587718 ps: (rv_dm_buffered_enable_vseq.sv:164) [uvm_test_top.env.virtual_sequencer.rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 108587718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_buffered_enable","qual_name":"9.rv_dm_buffered_enable.11122974831167636092184943020267325971009884988591242546351662962275404841253","seed":11122974831167636092184943020267325971009884988591242546351662962275404841253,"line":88,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_buffered_enable/latest/run.log","log_context":["UVM_ERROR @ 220669184 ps: (rv_dm_buffered_enable_vseq.sv:164) [uvm_test_top.env.virtual_sequencer.rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 220669184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job timed out after * minutes":[{"name":"rv_dm_stress_all","qual_name":"14.rv_dm_stress_all.93029905100036054311450561879498502169598414496466546964097920511572573206607","seed":93029905100036054311450561879498502169598414496466546964097920511572573206607,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/14.rv_dm_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"rv_dm_stress_all","qual_name":"15.rv_dm_stress_all.29081977074054209473523156735720722300407824317983097999308249437368018859206","seed":29081977074054209473523156735720722300407824317983097999308249437368018859206,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/15.rv_dm_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"rv_dm_stress_all","qual_name":"16.rv_dm_stress_all.9618934543763348742837868543272166418553352646727494527613154605691314442632","seed":9618934543763348742837868543272166418553352646727494527613154605691314442632,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/16.rv_dm_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"rv_dm_stress_all","qual_name":"30.rv_dm_stress_all.49538831251459388453725086525616126157634330249232461324520499528889460733093","seed":49538831251459388453725086525616126157634330249232461324520499528889460733093,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/30.rv_dm_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"rv_dm_stress_all","qual_name":"35.rv_dm_stress_all.91118205456149029843006584041952666248177555934266531864794439926511072589867","seed":91118205456149029843006584041952666248177555934266531864794439926511072589867,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/35.rv_dm_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"rv_dm_stress_all","qual_name":"36.rv_dm_stress_all.105193740075690508397487428395264787464379361520797364361770826863415421111937","seed":105193740075690508397487428395264787464379361520797364361770826863415421111937,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/36.rv_dm_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"rv_dm_stress_all","qual_name":"41.rv_dm_stress_all.9593384695190421902260388693995772932459607298543597727449891592357545242407","seed":9593384695190421902260388693995772932459607298543597727449891592357545242407,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/41.rv_dm_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]}]}},"passed":511,"total":656,"percent":77.89634146341463}