{"block":{"name":"sram_ctrl","variant":"ret","commit":"3ba6465de32edf4612bd1c0fa13f7e4cb5f4a7da","commit_short":"3ba6465","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/3ba6465de32edf4612bd1c0fa13f7e4cb5f4a7da","revision_info":"GitHub Revision: [`3ba6465`](https://github.com/lowrisc/opentitan/tree/3ba6465de32edf4612bd1c0fa13f7e4cb5f4a7da)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-03T17:01:04Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sram_ctrl_ret/data/sram_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sram_ctrl_smoke":{"max_time":102.3,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":0.99,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"sram_ctrl_csr_rw":{"max_time":0.97,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"sram_ctrl_csr_bit_bash":{"max_time":1.81,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"sram_ctrl_csr_aliasing":{"max_time":0.95,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sram_ctrl_csr_mem_rw_with_rand_reset":{"max_time":10.01,"sim_time":0.0,"passed":16,"total":20,"percent":80.0}},"passed":16,"total":20,"percent":80.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sram_ctrl_csr_rw":{"max_time":0.97,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":0.95,"sim_time":0.0,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"mem_walk":{"tests":{"sram_ctrl_mem_walk":{"max_time":13.58,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"mem_partial_access":{"tests":{"sram_ctrl_mem_partial_access":{"max_time":6.95,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":226,"total":230,"percent":98.26086956521739},"V2":{"testpoints":{"multiple_keys":{"tests":{"sram_ctrl_multiple_keys":{"max_time":1296.99,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_pipeline":{"tests":{"sram_ctrl_stress_pipeline":{"max_time":385.53,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"bijection":{"tests":{"sram_ctrl_bijection":{"max_time":94.98,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"access_during_key_req":{"tests":{"sram_ctrl_access_during_key_req":{"max_time":1367.07,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"lc_escalation":{"tests":{"sram_ctrl_lc_escalation":{"max_time":10.52,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"executable":{"tests":{"sram_ctrl_executable":{"max_time":1407.25,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"partial_access":{"tests":{"sram_ctrl_partial_access":{"max_time":76.14,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"sram_ctrl_partial_access_b2b":{"max_time":542.86,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"max_throughput":{"tests":{"sram_ctrl_max_throughput":{"max_time":93.16,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"sram_ctrl_throughput_w_partial_write":{"max_time":94.44,"sim_time":0.0,"passed":50,"total":50,"percent":100.0},"sram_ctrl_throughput_w_readback":{"max_time":113.52,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":150,"total":150,"percent":100.0},"regwen":{"tests":{"sram_ctrl_regwen":{"max_time":1228.14,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"ram_cfg":{"tests":{"sram_ctrl_ram_cfg":{"max_time":1.18,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all":{"tests":{"sram_ctrl_stress_all":{"max_time":4043.7,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"alert_test":{"tests":{"sram_ctrl_alert_test":{"max_time":1.09,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sram_ctrl_tl_errors":{"max_time":3.64,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"sram_ctrl_tl_errors":{"max_time":3.64,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":0.99,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"sram_ctrl_csr_rw":{"max_time":0.97,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":0.95,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"sram_ctrl_same_csr_outstanding":{"max_time":1.04,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":0.99,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"sram_ctrl_csr_rw":{"max_time":0.97,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":0.95,"sim_time":0.0,"passed":5,"total":5,"percent":100.0},"sram_ctrl_same_csr_outstanding":{"max_time":1.04,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":890,"total":890,"percent":100.0},"V2S":{"testpoints":{"passthru_mem_tl_intg_err":{"tests":{"sram_ctrl_passthru_mem_tl_intg_err":{"max_time":4.24,"sim_time":0.0,"passed":19,"total":20,"percent":95.0}},"passed":19,"total":20,"percent":95.0},"tl_intg_err":{"tests":{"sram_ctrl_tl_intg_err":{"max_time":2.65,"sim_time":0.0,"passed":20,"total":20,"percent":100.0},"sram_ctrl_sec_cm":{"max_time":0.93,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":20,"total":25,"percent":80.0},"prim_count_check":{"tests":{"sram_ctrl_sec_cm":{"max_time":0.93,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"sec_cm_bus_integrity":{"tests":{"sram_ctrl_tl_intg_err":{"max_time":2.65,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_ctrl_config_regwen":{"tests":{"sram_ctrl_regwen":{"max_time":1228.14,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_readback_config_regwen":{"tests":{"sram_ctrl_regwen":{"max_time":1228.14,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_exec_config_regwen":{"tests":{"sram_ctrl_csr_rw":{"max_time":0.97,"sim_time":0.0,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_exec_config_mubi":{"tests":{"sram_ctrl_executable":{"max_time":1407.25,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_exec_intersig_mubi":{"tests":{"sram_ctrl_executable":{"max_time":1407.25,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_lc_hw_debug_en_intersig_mubi":{"tests":{"sram_ctrl_executable":{"max_time":1407.25,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_lc_escalate_en_intersig_mubi":{"tests":{"sram_ctrl_lc_escalation":{"max_time":10.52,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_prim_ram_ctrl_mubi":{"tests":{"sram_ctrl_mubi_enc_err":{"max_time":1.59,"sim_time":0.0,"passed":43,"total":50,"percent":86.0}},"passed":43,"total":50,"percent":86.0},"sec_cm_mem_integrity":{"tests":{"sram_ctrl_passthru_mem_tl_intg_err":{"max_time":4.24,"sim_time":0.0,"passed":19,"total":20,"percent":95.0}},"passed":19,"total":20,"percent":95.0},"sec_cm_mem_readback":{"tests":{"sram_ctrl_readback_err":{"max_time":1.69,"sim_time":0.0,"passed":37,"total":50,"percent":74.0}},"passed":37,"total":50,"percent":74.0},"sec_cm_mem_scramble":{"tests":{"sram_ctrl_smoke":{"max_time":102.3,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_addr_scramble":{"tests":{"sram_ctrl_smoke":{"max_time":102.3,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_instr_bus_lc_gated":{"tests":{"sram_ctrl_executable":{"max_time":1407.25,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_ram_tl_lc_gate_fsm_sparse":{"tests":{"sram_ctrl_sec_cm":{"max_time":0.93,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"sec_cm_key_global_esc":{"tests":{"sram_ctrl_lc_escalation":{"max_time":10.52,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_key_local_esc":{"tests":{"sram_ctrl_sec_cm":{"max_time":0.93,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"sec_cm_init_ctr_redun":{"tests":{"sram_ctrl_sec_cm":{"max_time":0.93,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"sec_cm_scramble_key_sideload":{"tests":{"sram_ctrl_smoke":{"max_time":102.3,"sim_time":0.0,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_tlul_fifo_ctr_redun":{"tests":{"sram_ctrl_sec_cm":{"max_time":0.93,"sim_time":0.0,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0}},"passed":728,"total":780,"percent":93.33333333333333},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sram_ctrl_stress_all_with_rand_reset":{"max_time":709.39,"sim_time":0.0,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0}},"coverage":{"code":{"block":null,"line_statement":99.07,"branch":97.98,"condition_expression":92.9,"toggle":90.66,"fsm":100.0},"assertion":95.79,"functional":98.14},"cov_report_page":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: *":[{"name":"sram_ctrl_csr_mem_rw_with_rand_reset","qual_name":"2.sram_ctrl_csr_mem_rw_with_rand_reset.85610505167780298308929787002059504793774918260947213311256320501308035975918","seed":85610505167780298308929787002059504793774918260947213311256320501308035975918,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  24702070 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0 \n","UVM_INFO @  24702070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done":[{"name":"sram_ctrl_csr_mem_rw_with_rand_reset","qual_name":"3.sram_ctrl_csr_mem_rw_with_rand_reset.20362692561803577304029177728193851592374778555062211149641466889907851312973","seed":20362692561803577304029177728193851592374778555062211149641466889907851312973,"line":96,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 10003627146 ps: (sram_ctrl_base_vseq.sv:168) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done\n","UVM_INFO @ 10003627146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between":[{"name":"sram_ctrl_passthru_mem_tl_intg_err","qual_name":"5.sram_ctrl_passthru_mem_tl_intg_err.98199361300020874963626755684934757322419220390939231172342535108774920767431","seed":98199361300020874963626755684934757322419220390939231172342535108774920767431,"line":111,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  94663714 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between\n","UVM_INFO @  94663714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: *":[{"name":"sram_ctrl_csr_mem_rw_with_rand_reset","qual_name":"8.sram_ctrl_csr_mem_rw_with_rand_reset.64237408177983947303759701031251534094002376245454111780655745297567178758721","seed":64237408177983947303759701031251534094002376245454111780655745297567178758721,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  33493885 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (12 [0xc] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9 \n","UVM_INFO @  33493885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_csr_mem_rw_with_rand_reset","qual_name":"10.sram_ctrl_csr_mem_rw_with_rand_reset.36847593957220858965374013323711256629046682814480615042505279969211973041272","seed":36847593957220858965374013323711256629046682814480615042505279969211973041272,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  99173363 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (6 [0x6] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9 \n","UVM_INFO @  99173363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *":[{"name":"sram_ctrl_sec_cm","qual_name":"0.sram_ctrl_sec_cm.23099563403338070157048345660542072034406112209130530813269382474797999172045","seed":23099563403338070157048345660542072034406112209130530813269382474797999172045,"line":99,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log","log_context":["UVM_ERROR @   5269432 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 \n","UVM_INFO @   5269432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_sec_cm","qual_name":"2.sram_ctrl_sec_cm.60995323503896317606852281909395452633937020522513178452411119804958312066203","seed":60995323503896317606852281909395452633937020522513178452411119804958312066203,"line":99,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log","log_context":["UVM_ERROR @   3512179 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 \n","UVM_INFO @   3512179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(depth_o <= *'(Depth))'":[{"name":"sram_ctrl_sec_cm","qual_name":"1.sram_ctrl_sec_cm.50509509602545209981513865332553186911971444240732331533348518098220261175562","seed":50509509602545209981513865332553186911971444240732331533348518098220261175562,"line":99,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log","log_context":["\tOffending '(depth_o <= 2'(Depth))'\n","UVM_ERROR @   1034659 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth\n","UVM_INFO @   1034659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_sec_cm","qual_name":"4.sram_ctrl_sec_cm.91587813576710423592529987275342510554494998674428109756745102151116454320336","seed":91587813576710423592529987275342510554494998674428109756745102151116454320336,"line":101,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log","log_context":["\tOffending '(depth_o <= 2'(Depth))'\n","UVM_ERROR @   8289679 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth\n","UVM_INFO @   8289679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)":[{"name":"sram_ctrl_readback_err","qual_name":"2.sram_ctrl_readback_err.29590464858515224215736558072912604362140211986036621438833758923731507596465","seed":29590464858515224215736558072912604362140211986036621438833758923731507596465,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  22865145 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1b) != exp (0x2d)\n","UVM_INFO @  22865145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"3.sram_ctrl_readback_err.17462832868952482407279400406025054586573739503708965018717703504209969227167","seed":17462832868952482407279400406025054586573739503708965018717703504209969227167,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 128466039 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3a) != exp (0x5f)\n","UVM_INFO @ 128466039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"4.sram_ctrl_readback_err.32963349787411433698313024791647889007640683403737184396935398360751820137620","seed":32963349787411433698313024791647889007640683403737184396935398360751820137620,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  23756855 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x76) != exp (0x42)\n","UVM_INFO @  23756855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"5.sram_ctrl_readback_err.64213274873726565285745658521406659051501842953034677776663253714028901807990","seed":64213274873726565285745658521406659051501842953034677776663253714028901807990,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  23458211 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x43) != exp (0x10)\n","UVM_INFO @  23458211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"21.sram_ctrl_readback_err.19177493033342851752925649504232233656012995029005517090681202984140432613973","seed":19177493033342851752925649504232233656012995029005517090681202984140432613973,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/21.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  89714189 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x37) != exp (0x5e)\n","UVM_INFO @  89714189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"27.sram_ctrl_readback_err.11988226050146241612365242028212072188790907295826551694468559339066158599855","seed":11988226050146241612365242028212072188790907295826551694468559339066158599855,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/27.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  85020867 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7f) != exp (0x25)\n","UVM_INFO @  85020867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"28.sram_ctrl_readback_err.46810999353716941415270573080887778443563654692522981972029160700973817082906","seed":46810999353716941415270573080887778443563654692522981972029160700973817082906,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/28.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  45026531 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5) != exp (0x7a)\n","UVM_INFO @  45026531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"30.sram_ctrl_readback_err.55928151025839509296791128022228073204864219029644968337585255335224913752705","seed":55928151025839509296791128022228073204864219029644968337585255335224913752705,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/30.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  52585209 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x17) != exp (0x47)\n","UVM_INFO @  52585209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"35.sram_ctrl_readback_err.78329515002104876803444490787243682586088997449386866605506967706519307412750","seed":78329515002104876803444490787243682586088997449386866605506967706519307412750,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/35.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  27578632 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x18) != exp (0x72)\n","UVM_INFO @  27578632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"39.sram_ctrl_readback_err.69914811762278019464516024574229675627697546285681602199416585267762256893363","seed":69914811762278019464516024574229675627697546285681602199416585267762256893363,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/39.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  24850192 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x47) != exp (0x72)\n","UVM_INFO @  24850192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"43.sram_ctrl_readback_err.65753486984042953740095317107230193772802153378728467851984935090660463757228","seed":65753486984042953740095317107230193772802153378728467851984935090660463757228,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/43.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  49944003 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x25) != exp (0x52)\n","UVM_INFO @  49944003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"46.sram_ctrl_readback_err.98619818989725578879110650016179804559078373720567248519729214735277399801272","seed":98619818989725578879110650016179804559078373720567248519729214735277399801272,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/46.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  52291988 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x62) != exp (0x7e)\n","UVM_INFO @  52291988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_readback_err","qual_name":"49.sram_ctrl_readback_err.41954454236699003042935908714022210694976545729534247792453395297885370818307","seed":41954454236699003042935908714022210694976545729534247792453395297885370818307,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/49.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @  88000200 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2f) != exp (0x36)\n","UVM_INFO @  88000200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(curr_fwd | pend_req[d2h.d_source].pend)'":[{"name":"sram_ctrl_sec_cm","qual_name":"3.sram_ctrl_sec_cm.14727970732117517066296033077350778977837507672053249479976790553235503790268","seed":14727970732117517066296033077350778977837507672053249479976790553235503790268,"line":100,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log","log_context":["\tOffending '(curr_fwd | pend_req[d2h.d_source].pend)'\n","\"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv\", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 1628414ps failed at 1628414ps\n","\tOffending '(curr_fwd | pend_req[d2h.d_source].pend)'\n","\"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv\", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 1638618ps failed at 1638618ps\n","\tOffending '(curr_fwd | pend_req[d2h.d_source].pend)'\n"]}],"Offending 'reqfifo_rvalid'":[{"name":"sram_ctrl_mubi_enc_err","qual_name":"17.sram_ctrl_mubi_enc_err.53541579529278930962722970421611782769061279855133188303461182616274718518810","seed":53541579529278930962722970421611782769061279855133188303461182616274718518810,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @  90858555 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @  90858555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"19.sram_ctrl_mubi_enc_err.96875563127410417760335167274033653121782011751453887954625907079567002510612","seed":96875563127410417760335167274033653121782011751453887954625907079567002510612,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 107266048 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 107266048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"24.sram_ctrl_mubi_enc_err.6713146472636721404373589127511914466925127890098892282405163987387444810283","seed":6713146472636721404373589127511914466925127890098892282405163987387444810283,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 181061135 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 181061135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"27.sram_ctrl_mubi_enc_err.55737287849395432864219479997504571887889034013435580611805512074047541990590","seed":55737287849395432864219479997504571887889034013435580611805512074047541990590,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @  92956513 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @  92956513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"31.sram_ctrl_mubi_enc_err.43600923721749462557822559267437643522203817635832070796015735993900203588871","seed":43600923721749462557822559267437643522203817635832070796015735993900203588871,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @  29838173 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @  29838173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"38.sram_ctrl_mubi_enc_err.65305783104524637814165502477751128967982371196451926852539187814689926446198","seed":65305783104524637814165502477751128967982371196451926852539187814689926446198,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @  41100889 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @  41100889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"49.sram_ctrl_mubi_enc_err.53735700957744474423860727873188853526402079127466857322962155398516166190655","seed":53735700957744474423860727873188853526402079127466857322962155398516166190655,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["\tOffending 'reqfifo_rvalid'\n","UVM_ERROR @ 433084431 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 433084431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"sram_ctrl_stress_all_with_rand_reset","qual_name":"26.sram_ctrl_stress_all_with_rand_reset.5190455788017099999779559588606853105353298378745755435260723353443497476668","seed":5190455788017099999779559588606853105353298378745755435260723353443497476668,"line":180,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1914056181 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1914056181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1893,"total":1950,"percent":97.07692307692308}