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---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"26.lc_ctrl_stress_all_with_rand_reset.93060632338145007502535189242199621573049064032957844152883504174611440581804","seed":93060632338145007502535189242199621573049064032957844152883504174611440581804,"line":4844,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 10823862023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"27.lc_ctrl_stress_all_with_rand_reset.19691351157159808239631430459452975417853410526724247417138499005780790794398","seed":19691351157159808239631430459452975417853410526724247417138499005780790794398,"line":1348,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 3446899413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"34.lc_ctrl_stress_all_with_rand_reset.57471770937631533535621282024801975338441011478247594780089557418710750821657","seed":57471770937631533535621282024801975338441011478247594780089557418710750821657,"line":8149,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 3181309844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"36.lc_ctrl_stress_all_with_rand_reset.9615190908298344031748822874704316464290055005774843891323034522901443921609","seed":9615190908298344031748822874704316464290055005774843891323034522901443921609,"line":12769,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 7189384133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"41.lc_ctrl_stress_all_with_rand_reset.100102247262033547245211613885857214845753015460781217250456657560193541563954","seed":100102247262033547245211613885857214845753015460781217250456657560193541563954,"line":205,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 906145551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"44.lc_ctrl_stress_all_with_rand_reset.33572172018474037633998689482470175543550670250064314704524184448782820233355","seed":33572172018474037633998689482470175543550670250064314704524184448782820233355,"line":151,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 1556145996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"47.lc_ctrl_stress_all_with_rand_reset.56203777806178519227258078669186823358891292114388395044120248014671012380849","seed":56203777806178519227258078669186823358891292114388395044120248014671012380849,"line":151,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 598956610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"16.lc_ctrl_stress_all_with_rand_reset.21573047523019914679403889671709356997999548786153225351383655258170238584604","seed":21573047523019914679403889671709356997999548786153225351383655258170238584604,"line":3059,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 3365497573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"21.lc_ctrl_stress_all_with_rand_reset.105003537120999929947256349636290430823879131648243315597980487456291030631900","seed":105003537120999929947256349636290430823879131648243315597980487456291030631900,"line":7247,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 15957976017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (lc_ctrl_scoreboard.sv:248) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked*":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"28.lc_ctrl_stress_all_with_rand_reset.107329354629577997767340711420195969471318760228865769016863258374469939799998","seed":107329354629577997767340711420195969471318760228865769016863258374469939799998,"line":2710,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 1540331974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1006,"total":1030,"percent":97.66990291262135}