{"block":{"name":"rstmgr_cnsty_chk","variant":null,"commit":"85f0913c4aced94cfe321db26139420ff076d36a","commit_short":"85f0913","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/85f0913c4aced94cfe321db26139420ff076d36a","revision_info":"GitHub Revision: [`85f0913`](https://github.com/lowrisc/opentitan/tree/85f0913c4aced94cfe321db26139420ff076d36a)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-10T17:12:19Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_darjeeling/ip_autogen/rstmgr/dv/data/rstmgr_cnsty_chk_testplan.html","stages":{"unmapped":{"testpoints":{"Unmapped":{"tests":{"rstmgr_cnsty_chk_test":{"max_time":2.42,"sim_time":10619.546407,"passed":9,"total":10,"percent":90.0}},"passed":9,"total":10,"percent":90.0}},"passed":9,"total":10,"percent":90.0}},"coverage":{"code":{"block":null,"line_statement":98.41,"branch":98.31,"condition_expression":86.21,"toggle":100.0,"fsm":92.31},"assertion":100.0,"functional":null},"cov_report_page":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *))":[{"name":"rstmgr_cnsty_chk_test","qual_name":"6.rstmgr_cnsty_chk_test.97556518647315049749111314561754932486702821057192740300648795520469949166776","seed":97556518647315049749111314561754932486702821057192740300648795520469949166776,"line":175,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/6.rstmgr_cnsty_chk_test/latest/run.log","log_context":["UVM_INFO @ 1816309102 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16\n","UVM_INFO @ 1834389102 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16\n","UVM_INFO @ 1852469102 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16\n","UVM_INFO @ 1870549102 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16\n"]}]}},"passed":9,"total":10,"percent":90.0}