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Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between":[{"name":"sram_ctrl_tl_intg_err","qual_name":"5.sram_ctrl_tl_intg_err.20006481436717952436886323955768903039648707471494737844576907796231962880889","seed":20006481436717952436886323955768903039648707471494737844576907796231962880889,"line":237,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_intg_err/latest/run.log","log_context":["UVM_INFO @  95758238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending 'reqfifo_rvalid'":[{"name":"sram_ctrl_mubi_enc_err","qual_name":"7.sram_ctrl_mubi_enc_err.47717509711128335430928159967610223657230229032692945121964282358465959386451","seed":47717509711128335430928159967610223657230229032692945121964282358465959386451,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["UVM_ERROR @  45281814 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @  45281814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"8.sram_ctrl_mubi_enc_err.78297435153423746344435186538047150880570365708196421484982515893054730935608","seed":78297435153423746344435186538047150880570365708196421484982515893054730935608,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["UVM_ERROR @  26992540 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @  26992540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sram_ctrl_mubi_enc_err","qual_name":"31.sram_ctrl_mubi_enc_err.78985855288704813820122269324372098475963687980643042180713479830423812199305","seed":78985855288704813820122269324372098475963687980643042180713479830423812199305,"line":104,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["UVM_ERROR @ 143382506 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @ 143382506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"sram_ctrl_stress_all_with_rand_reset","qual_name":"12.sram_ctrl_stress_all_with_rand_reset.11018608518103342429403624249908693435546144537408204500013059277079679033876","seed":11018608518103342429403624249908693435546144537408204500013059277079679033876,"line":245,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 914129213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_stress_all_with_rand_reset","qual_name":"43.sram_ctrl_stress_all_with_rand_reset.86813835034254683656740649484307536189387584795291978808513471469953094344429","seed":86813835034254683656740649484307536189387584795291978808513471469953094344429,"line":125,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 4035219941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: *":[{"name":"sram_ctrl_csr_mem_rw_with_rand_reset","qual_name":"17.sram_ctrl_csr_mem_rw_with_rand_reset.25400079050833671156976106955265270784737387493560991801662398220128418109543","seed":25400079050833671156976106955265270784737387493560991801662398220128418109543,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 169078790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface sram_ctrl_prim_reg_block, item had unexpected d_error value(predicted *, but saw *).":[{"name":"sram_ctrl_readback_err","qual_name":"29.sram_ctrl_readback_err.111897200786758135374430734452220414207833988465734469698756981680745263626517","seed":111897200786758135374430734452220414207833988465734469698756981680745263626517,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/29.sram_ctrl_readback_err/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@2933) { a_addr: 'hf03f1698  a_data: 'hc  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h28  a_opcode: 'h1  a_user: 'h2617f  d_param: 'h0  d_source: 'h28  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{}.\n","UVM_INFO @  80645755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"sram_ctrl_readback_err","qual_name":"31.sram_ctrl_readback_err.76950519436863155007634969707791905528473708500909193073068046757954586775447","seed":76950519436863155007634969707791905528473708500909193073068046757954586775447,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/31.sram_ctrl_readback_err/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@3465) { a_addr: 'h57e02248  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h42  a_opcode: 'h4  a_user: 'h24baa  d_param: 'h0  d_source: 'h42  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{}.\n","UVM_INFO @  24600093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}]}},"passed":1168,"total":1190,"percent":98.15126050420169}