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---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"5.alert_handler_ping_timeout.83636112215104098590259805290358876336435962832975290684174653051025339837988","seed":83636112215104098590259805290358876336435962832975290684174653051025339837988,"line":125,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 5347283690 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 5347283690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"8.alert_handler_ping_timeout.80239525280345146977013317821753006036757428975657522360274220708175411091906","seed":80239525280345146977013317821753006036757428975657522360274220708175411091906,"line":93,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 1472798368 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 1472798368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"10.alert_handler_ping_timeout.13627286172097772940481183861756038315274645023583320359988945661955983343853","seed":13627286172097772940481183861756038315274645023583320359988945661955983343853,"line":90,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 4357145121 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 4357145121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"14.alert_handler_ping_timeout.99650006387699309315417041064047311462466107222943016844659608128075332436396","seed":99650006387699309315417041064047311462466107222943016844659608128075332436396,"line":96,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 9234277661 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 9234277661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"18.alert_handler_ping_timeout.32708281903338577898180804386306400124573335520358944219493038413768253143011","seed":32708281903338577898180804386306400124573335520358944219493038413768253143011,"line":90,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 4055023437 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 4055023437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"21.alert_handler_ping_timeout.91095991833779314490874564852495307194816126335344318094143284662582644280819","seed":91095991833779314490874564852495307194816126335344318094143284662582644280819,"line":96,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 3584406467 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 3584406467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_lpg","qual_name":"26.alert_handler_lpg.28707524551561698735753262720632312174711037776402555815277626334155306370266","seed":28707524551561698735753262720632312174711037776402555815277626334155306370266,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/26.alert_handler_lpg/latest/run.log","log_context":["UVM_ERROR @ 89999360390 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 89999360390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"27.alert_handler_ping_timeout.36045067425255761998799819816375285859238487842173406641408091737099388200026","seed":36045067425255761998799819816375285859238487842173406641408091737099388200026,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 1036022408 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 1036022408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"28.alert_handler_ping_timeout.15121913241252098412251183540245895449995939869928695522882008272329214430274","seed":15121913241252098412251183540245895449995939869928695522882008272329214430274,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 6525488027 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 6525488027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"33.alert_handler_ping_timeout.52392858717029945725366021124649941259821501909246626582170528761868033664925","seed":52392858717029945725366021124649941259821501909246626582170528761868033664925,"line":111,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 59338635589 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 59338635589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"34.alert_handler_ping_timeout.82265933536804454508586298529733938942275634567852507054628747631946878584961","seed":82265933536804454508586298529733938942275634567852507054628747631946878584961,"line":93,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 2232514386 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 2232514386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"40.alert_handler_ping_timeout.70161065734170090690466199349911397608690369634014568060231816882081096188341","seed":70161065734170090690466199349911397608690369634014568060231816882081096188341,"line":142,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 16611714041 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 16611714041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"43.alert_handler_ping_timeout.27546245747283330419459788378562351047348706567784960533248510728079462241007","seed":27546245747283330419459788378562351047348706567784960533248510728079462241007,"line":99,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/43.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 1987017366 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 1987017366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"44.alert_handler_ping_timeout.101197601244860186820708472013067370251523377163514678012360506932494738812283","seed":101197601244860186820708472013067370251523377163514678012360506932494738812283,"line":93,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/44.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 6080707447 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 6080707447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"45.alert_handler_ping_timeout.8372509827099893153387846575750701665740446584103722318198578508609450146352","seed":8372509827099893153387846575750701665740446584103722318198578508609450146352,"line":102,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 2467534886 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 2467534886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"46.alert_handler_ping_timeout.97272174908073444007070046771514711128675831198278270984219105330849298680661","seed":97272174908073444007070046771514711128675831198278270984219105330849298680661,"line":102,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 4810383023 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 4810383023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_lpg","qual_name":"46.alert_handler_lpg.44290914970869761232115834386796983717446171939677397295947972808934454274838","seed":44290914970869761232115834386796983717446171939677397295947972808934454274838,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_lpg/latest/run.log","log_context":["UVM_ERROR @ 3458792824 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (10 [0xa] vs 14 [0xe]) reg name: intr_state\n","UVM_INFO @ 3458792824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"47.alert_handler_ping_timeout.108846751405738301154293784268379539645147553984382433321430554746179232544745","seed":108846751405738301154293784268379539645147553984382433321430554746179232544745,"line":114,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 11969228613 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 11969228613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_lpg","qual_name":"48.alert_handler_lpg.85670804230386710453377509661837664065603300602836661204995746935336350377415","seed":85670804230386710453377509661837664065603300602836661204995746935336350377415,"line":81,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/48.alert_handler_lpg/latest/run.log","log_context":["UVM_ERROR @ 27003233392 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (9 [0x9] vs 13 [0xd]) reg name: intr_state\n","UVM_INFO @ 27003233392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"49.alert_handler_ping_timeout.94956986971095525867588900825223404730282475371632304441761718426438881858763","seed":94956986971095525867588900825223404730282475371632304441761718426438881858763,"line":93,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 2920718134 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 2920718134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"1.alert_handler_stress_all_with_rand_reset.55297666088995349952078085090764758574138821759789954790342701493816493003394","seed":55297666088995349952078085090764758574138821759789954790342701493816493003394,"line":116,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3239468300 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3239468300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"4.alert_handler_stress_all_with_rand_reset.62677129420977466587683136431311248541944838392417436399379662206119779040265","seed":62677129420977466587683136431311248541944838392417436399379662206119779040265,"line":114,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8402105361 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 8402105361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"7.alert_handler_stress_all_with_rand_reset.86926666655182512650437214795694710973918632643368313317665911966781016091799","seed":86926666655182512650437214795694710973918632643368313317665911966781016091799,"line":167,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1881805080 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1881805080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"9.alert_handler_stress_all_with_rand_reset.35800812409319917489577389630402382818823961401320954083596302798210888960710","seed":35800812409319917489577389630402382818823961401320954083596302798210888960710,"line":137,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2347945227 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2347945227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"13.alert_handler_stress_all_with_rand_reset.5571770255422514644484524617749195649976176632804088017899380816321502150734","seed":5571770255422514644484524617749195649976176632804088017899380816321502150734,"line":199,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 34335729107 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 34335729107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"16.alert_handler_stress_all_with_rand_reset.28290926254654915318618824443100797923353842492897204855324205095221190014167","seed":28290926254654915318618824443100797923353842492897204855324205095221190014167,"line":177,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5481178232 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5481178232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"18.alert_handler_stress_all_with_rand_reset.685929779544910327160263799558495360127093499526097885005809498506438285861","seed":685929779544910327160263799558495360127093499526097885005809498506438285861,"line":144,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6510480175 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 6510480175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"21.alert_handler_stress_all_with_rand_reset.92869769105687163187231288087433103925936874389270237616911004196896889717751","seed":92869769105687163187231288087433103925936874389270237616911004196896889717751,"line":83,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 211974477 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 211974477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"22.alert_handler_stress_all_with_rand_reset.28316049095379808647040144606459944453886662141782266997381434367690643563391","seed":28316049095379808647040144606459944453886662141782266997381434367690643563391,"line":156,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2381068985 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2381068985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"26.alert_handler_stress_all_with_rand_reset.14742944684218512761940085547808241925819234437172682965989550034656272874037","seed":14742944684218512761940085547808241925819234437172682965989550034656272874037,"line":138,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/26.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7790053377 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 7790053377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"29.alert_handler_stress_all_with_rand_reset.81696597297054747992777044602463585336078915535797014584377778146095081461055","seed":81696597297054747992777044602463585336078915535797014584377778146095081461055,"line":121,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/29.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8949142794 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 8949142794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"31.alert_handler_stress_all_with_rand_reset.49993676426532727781107378374713815150849447845563043189489079916728874823840","seed":49993676426532727781107378374713815150849447845563043189489079916728874823840,"line":131,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 23124880802 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 23124880802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"34.alert_handler_stress_all_with_rand_reset.18370042040003832213522975219577485080116223473102878814371478296837581464316","seed":18370042040003832213522975219577485080116223473102878814371478296837581464316,"line":292,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/34.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8519747803 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 8519747803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"36.alert_handler_stress_all_with_rand_reset.3153334529223067745112960605095328652003327324021933024325856126207726111440","seed":3153334529223067745112960605095328652003327324021933024325856126207726111440,"line":155,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/36.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2910255404 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2910255404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"39.alert_handler_stress_all_with_rand_reset.69657479917128044683565480129656545887960082564139719745651712569629854356397","seed":69657479917128044683565480129656545887960082564139719745651712569629854356397,"line":98,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/39.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 453557282 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 453557282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"41.alert_handler_stress_all_with_rand_reset.12640322934944367563995126554248017483603572231633363826661305030940109496359","seed":12640322934944367563995126554248017483603572231633363826661305030940109496359,"line":103,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/41.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 652365993 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 652365993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"43.alert_handler_stress_all_with_rand_reset.56782359935737135196534543880028047021530388910874267654824093545735503315155","seed":56782359935737135196534543880028047021530388910874267654824093545735503315155,"line":144,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/43.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 14549721520 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 14549721520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model.":[{"name":"alert_handler_ping_timeout","qual_name":"4.alert_handler_ping_timeout.70482156391354819289757751904454077987085929198463389667781372173766929703062","seed":70482156391354819289757751904454077987085929198463389667781372173766929703062,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 565270405 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 565270405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"17.alert_handler_ping_timeout.83380233204693589549470812237460425853270323836861881795480293421115506971119","seed":83380233204693589549470812237460425853270323836861881795480293421115506971119,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 344286727 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 344286727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"22.alert_handler_ping_timeout.18427214820338522945121723487122580002798826916263630190269512910538402661331","seed":18427214820338522945121723487122580002798826916263630190269512910538402661331,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 1087919646 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 1087919646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"26.alert_handler_ping_timeout.31391022055977620187035901937314042125343658462111249250628937008810054845942","seed":31391022055977620187035901937314042125343658462111249250628937008810054845942,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 520510622 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 520510622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"32.alert_handler_ping_timeout.91684278868434381548857306691806303638680410721400270235381126148009517852108","seed":91684278868434381548857306691806303638680410721400270235381126148009517852108,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 898162140 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 898162140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"37.alert_handler_ping_timeout.65789774724117400826833523879238761631854355968126675992248780184460882102595","seed":65789774724117400826833523879238761631854355968126675992248780184460882102595,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 205725107 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 205725107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"38.alert_handler_ping_timeout.99747313469170141304022901918985608789922970498909357936315264751748407121522","seed":99747313469170141304022901918985608789922970498909357936315264751748407121522,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 5945781226 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 5945781226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"41.alert_handler_ping_timeout.113293084800042349584944616378418256894526797406326056529577728546826626836949","seed":113293084800042349584944616378418256894526797406326056529577728546826626836949,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 3677096212 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 3677096212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1149) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.":[{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"12.alert_handler_stress_all_with_rand_reset.25560796932012392790754711742306541970196223361238110665452061352116345739510","seed":25560796932012392790754711742306541970196223361238110665452061352116345739510,"line":311,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4563333805 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 4563333805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"35.alert_handler_stress_all_with_rand_reset.41767194974263106933376773820167111554175455016148073449717353870465167961232","seed":41767194974263106933376773820167111554175455016148073449717353870465167961232,"line":82,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/35.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  66751885 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @  66751885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":802,"total":850,"percent":94.3529411764706}