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---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"18.edn_disable_auto_req_mode.3853480028324721388233095588115054184113319771629737406621592944953905676881","seed":3853480028324721388233095588115054184113319771629737406621592944953905676881,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/18.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"19.edn_disable_auto_req_mode.92622044218335484038491367918795366538568373401557045109953205215070299087691","seed":92622044218335484038491367918795366538568373401557045109953205215070299087691,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/19.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"25.edn_disable_auto_req_mode.111702294025959097649943793549025412129633398606092422490777690961414181163279","seed":111702294025959097649943793549025412129633398606092422490777690961414181163279,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/25.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"27.edn_disable_auto_req_mode.111870433923478873105757986504922950740181446381015475288732623305629386560802","seed":111870433923478873105757986504922950740181446381015475288732623305629386560802,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/27.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"41.edn_disable_auto_req_mode.53324354534284680296350553281958005816679748826575463111631184475940369197876","seed":53324354534284680296350553281958005816679748826575463111631184475940369197876,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/41.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"edn_stress_all_with_rand_reset","qual_name":"8.edn_stress_all_with_rand_reset.28473958006852211253816675395602915632369327855652944722472386226626911121469","seed":28473958006852211253816675395602915632369327855652944722472386226626911121469,"line":144,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/8.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1011405002 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1011405002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"16.edn_stress_all_with_rand_reset.30436328590391562316665285004462197792904911426362033911344685595272683736297","seed":30436328590391562316665285004462197792904911426362033911344685595272683736297,"line":358,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/16.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4546109344 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4546109344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"20.edn_stress_all_with_rand_reset.20340068351827709863790659585505111686822888507065664708652788078585714503537","seed":20340068351827709863790659585505111686822888507065664708652788078585714503537,"line":280,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/20.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2379241878 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2379241878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"21.edn_stress_all_with_rand_reset.9054328905227000106515418215422189276272530946593986797380727430234001408419","seed":9054328905227000106515418215422189276272530946593986797380727430234001408419,"line":276,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/21.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1877226376 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1877226376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"28.edn_stress_all_with_rand_reset.83551878075579464622217812636913124957135041955231453451293214132857028990331","seed":83551878075579464622217812636913124957135041955231453451293214132857028990331,"line":368,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/28.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3284398252 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3284398252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"32.edn_stress_all_with_rand_reset.91114612378462478713610740772687341937374032683013318657235016601452643063936","seed":91114612378462478713610740772687341937374032683013318657235016601452643063936,"line":183,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/32.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 570348041 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 570348041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"33.edn_stress_all_with_rand_reset.21170685834616627711888229674567238412325729337712279895609400615693184156876","seed":21170685834616627711888229674567238412325729337712279895609400615693184156876,"line":249,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/33.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3403182206 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3403182206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"34.edn_stress_all_with_rand_reset.41862115694692879259498459790333523047899600045220334839544104477646495668575","seed":41862115694692879259498459790333523047899600045220334839544104477646495668575,"line":192,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/34.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1079965310 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1079965310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"45.edn_stress_all_with_rand_reset.38827588022962488808848872980471629490343367768122236919478096634553841233490","seed":38827588022962488808848872980471629490343367768122236919478096634553841233490,"line":237,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/45.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1438362172 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1438362172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"49.edn_stress_all_with_rand_reset.52459497015592339561748651414530755720330598367737183964090083774659656544681","seed":52459497015592339561748651414530755720330598367737183964090083774659656544681,"line":116,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/49.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 114934780 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 114934780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.":[{"name":"edn_disable_auto_req_mode","qual_name":"13.edn_disable_auto_req_mode.1053368176939720058656145584096393635205835773023917975225382663963497787296","seed":1053368176939720058656145584096393635205835773023917975225382663963497787296,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/13.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 103232945 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00467662 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @ 103232945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"48.edn_disable_auto_req_mode.110787334874366706673948370618262836920884510126662507765628502209036664254716","seed":110787334874366706673948370618262836920884510126662507765628502209036664254716,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/48.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  12898656 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x000016a3 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  12898656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1112,"total":1130,"percent":98.40707964601769}