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(edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.":[{"name":"edn_disable_auto_req_mode","qual_name":"0.edn_disable_auto_req_mode.43085873589700221833180836270578259177379387577513990782149209440277713146986","seed":43085873589700221833180836270578259177379387577513990782149209440277713146986,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  31713898 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00000942 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  31713898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"28.edn_disable_auto_req_mode.36524648510998608003467294791100690991480871470865846571222226816373112090630","seed":36524648510998608003467294791100690991480871470865846571222226816373112090630,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/28.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  27782741 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00a17692 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  27782741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"40.edn_disable_auto_req_mode.34027917569816125288040184374147195428277834735850097016394249919574891419689","seed":34027917569816125288040184374147195428277834735850097016394249919574891419689,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/40.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  59780511 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00000602 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  59780511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"edn_disable_auto_req_mode","qual_name":"5.edn_disable_auto_req_mode.61997662186984490872243931936984250836011548569362808728032364084525315634981","seed":61997662186984490872243931936984250836011548569362808728032364084525315634981,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"7.edn_disable_auto_req_mode.2451698408848147827371052270295125137166988652884123063024773128124120462478","seed":2451698408848147827371052270295125137166988652884123063024773128124120462478,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"15.edn_disable_auto_req_mode.67439908057761710641427542664117676895210644940072714620600670011159513482101","seed":67439908057761710641427542664117676895210644940072714620600670011159513482101,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"30.edn_disable_auto_req_mode.30616863052408740294588914428411874517382451011904598887161628459587854430033","seed":30616863052408740294588914428411874517382451011904598887161628459587854430033,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/30.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"38.edn_disable_auto_req_mode.93824034984157725889354940335766429524760324657804199635107812084312714877970","seed":93824034984157725889354940335766429524760324657804199635107812084312714877970,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/38.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Error-[FCIBH] Illegal bin hit":[{"name":"edn_stress_all_with_rand_reset","qual_name":"6.edn_stress_all_with_rand_reset.1281635173386922386256819811994887439986030640755632540815695161349454220483","seed":1281635173386922386256819811994887439986030640755632540815695161349454220483,"line":194,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_stress_all_with_rand_reset/latest/run.log","log_context":["Error-[FCIBH] Illegal bin hit\n","/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25\n","csrng_agent_pkg, \"csrng_agent_pkg::device_cmd_cg\"\n","  VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 1195138957 ps, Illegal \n","  state bin il of coverpoint csrng_cmd_cp in covergroup \n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"edn_stress_all_with_rand_reset","qual_name":"14.edn_stress_all_with_rand_reset.94877102008331427482490880345716708205169232593419905987379526820306948779335","seed":94877102008331427482490880345716708205169232593419905987379526820306948779335,"line":252,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/14.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1954838162 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1954838162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"38.edn_stress_all_with_rand_reset.6774848685158810511186623507682006769048265268023552906629129812742425185657","seed":6774848685158810511186623507682006769048265268023552906629129812742425185657,"line":299,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/38.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3094155092 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3094155092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1119,"total":1130,"percent":99.02654867256638}