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---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"5.keymgr_stress_all_with_rand_reset.10118708459988680437292054249880427326629391142459238410368679337729913296764","seed":10118708459988680437292054249880427326629391142459238410368679337729913296764,"line":249,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 294690133 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 294690133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"8.keymgr_stress_all_with_rand_reset.87944773716015252787487317456818318581857210404013083654385791159224366625428","seed":87944773716015252787487317456818318581857210404013083654385791159224366625428,"line":670,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/8.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 171294630 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 171294630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"13.keymgr_stress_all_with_rand_reset.88677566582053769200847770367823619779080644978094045070774532292813614021174","seed":88677566582053769200847770367823619779080644978094045070774532292813614021174,"line":703,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/13.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 760404550 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 760404550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"16.keymgr_stress_all_with_rand_reset.25777009707427548292856254167372257698492192298167522345103891778288421942087","seed":25777009707427548292856254167372257698492192298167522345103891778288421942087,"line":382,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/16.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 629993909 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 629993909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"17.keymgr_stress_all_with_rand_reset.95234901996485053342312947408608571252968815286615510664532576269332314429852","seed":95234901996485053342312947408608571252968815286615510664532576269332314429852,"line":428,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/17.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 203251854 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 203251854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"28.keymgr_stress_all_with_rand_reset.36750278274571983758287598857599589044032075059832781683390713624367267281720","seed":36750278274571983758287598857599589044032075059832781683390713624367267281720,"line":97,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/28.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 515750099 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 515750099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"30.keymgr_stress_all_with_rand_reset.4229394739134591150280403291836821764246480656082130749025310834342324379167","seed":4229394739134591150280403291836821764246480656082130749025310834342324379167,"line":355,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/30.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 136954107 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 136954107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"32.keymgr_stress_all_with_rand_reset.68415055566447186981955394746610546265313187076699175998804573919362670978945","seed":68415055566447186981955394746610546265313187076699175998804573919362670978945,"line":643,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/32.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 334178409 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 334178409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"33.keymgr_stress_all_with_rand_reset.84997887625434796781257510551899216699873669648570324641850519548105162537646","seed":84997887625434796781257510551899216699873669648570324641850519548105162537646,"line":425,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/33.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 200653823 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 200653823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"34.keymgr_stress_all_with_rand_reset.16614301045073868217138802937269449891408823966826593772919531242734173834219","seed":16614301045073868217138802937269449891408823966826593772919531242734173834219,"line":107,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/34.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 620686059 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 620686059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"35.keymgr_stress_all_with_rand_reset.41460111044352818360535834575079529618838198789990539515244401570211748514364","seed":41460111044352818360535834575079529618838198789990539515244401570211748514364,"line":378,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/35.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 212852099 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 212852099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"36.keymgr_stress_all_with_rand_reset.89272809884734303333901029995861611553655040122147022570475516155198245149295","seed":89272809884734303333901029995861611553655040122147022570475516155198245149295,"line":394,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/36.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 143138732 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 143138732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"38.keymgr_stress_all_with_rand_reset.29250497088368922630887481007199107202960106445156184443500098831894774600553","seed":29250497088368922630887481007199107202960106445156184443500098831894774600553,"line":144,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/38.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 219026913 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 219026913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"40.keymgr_stress_all_with_rand_reset.100019891770812365505144422641023011465209149089037038690431649870942245243962","seed":100019891770812365505144422641023011465209149089037038690431649870942245243962,"line":191,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/40.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 465768950 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 465768950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"42.keymgr_stress_all_with_rand_reset.25742546069813934849948604899420627308527023473627779716329597654193475509478","seed":25742546069813934849948604899420627308527023473627779716329597654193475509478,"line":162,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/42.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 121160391 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 121160391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"43.keymgr_stress_all_with_rand_reset.16007030576086380333687143896749144414036218816508671709708320302901289481077","seed":16007030576086380333687143896749144414036218816508671709708320302901289481077,"line":406,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/43.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 486996592 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 486996592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"45.keymgr_stress_all_with_rand_reset.104813376999224355584865595432820653210654532569570913219903921599693649234418","seed":104813376999224355584865595432820653210654532569570913219903921599693649234418,"line":302,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/45.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 523420917 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 523420917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"47.keymgr_stress_all_with_rand_reset.87812580750343742127827903085083534488047716540272645384191829113676751382136","seed":87812580750343742127827903085083534488047716540272645384191829113676751382136,"line":1471,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/47.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1616097968 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1616097968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"48.keymgr_stress_all_with_rand_reset.78209818295447013327646475365055545797414162202029896345906213897684497727222","seed":78209818295447013327646475365055545797414162202029896345906213897684497727222,"line":333,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/48.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 162153008 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 162153008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"49.keymgr_stress_all_with_rand_reset.19075304215433077359851652121380540019604163309153847698474941084167178677567","seed":19075304215433077359851652121380540019604163309153847698474941084167178677567,"line":209,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/49.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 421911880 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 421911880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert recov_operation_err is not received!":[{"name":"keymgr_sync_async_fault_cross","qual_name":"31.keymgr_sync_async_fault_cross.65511925785822228251347003118225243730758716483844232348816829415222187625113","seed":65511925785822228251347003118225243730758716483844232348816829415222187625113,"line":161,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/31.keymgr_sync_async_fault_cross/latest/run.log","log_context":["UVM_ERROR @ 107238709 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!\n","UVM_INFO @ 107238709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_sync_async_fault_cross","qual_name":"35.keymgr_sync_async_fault_cross.40615269923946688899206352222013604098200911952077512284564013141388127805270","seed":40615269923946688899206352222013604098200911952077512284564013141388127805270,"line":155,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/35.keymgr_sync_async_fault_cross/latest/run.log","log_context":["UVM_ERROR @  77032132 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!\n","UVM_INFO @  77032132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerIntKey for Sealing Aes":[{"name":"keymgr_lc_disable","qual_name":"47.keymgr_lc_disable.51366275674912512458571287262635098623831868311973879463525160519507213217904","seed":51366275674912512458571287262635098623831868311973879463525160519507213217904,"line":314,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/47.keymgr_lc_disable/latest/run.log","log_context":["UVM_ERROR @ 1486507919 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (6425430764999401232515082186741839513596077565902696240588568277270346073921804190963066557793347137058722383038475995749158386444232711318956388769982426 [0x7aaed9f2384eff231d8eb7247ad9649199a44cef0ec548a29ecb01f131ed943eac5297ca417ebcd3821b405d2352778f6f83fd3830a9850a6476feeb7f35e7da] vs 6425430764999401232515082186741839513596077565902696240588568277270346073921804190963066557793347137058722383038475995749158386444232711318956388769982426 [0x7aaed9f2384eff231d8eb7247ad9649199a44cef0ec548a29ecb01f131ed943eac5297ca417ebcd3821b405d2352778f6f83fd3830a9850a6476feeb7f35e7da]) AES key at state StOwnerIntKey for Sealing Aes\n","UVM_INFO @ 1486507919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1086,"total":1110,"percent":97.83783783783784}