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---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"2.lc_ctrl_stress_all_with_rand_reset.70047641407704559264615905575408245284124770076602259025399459300622595431560","seed":70047641407704559264615905575408245284124770076602259025399459300622595431560,"line":6137,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3379641763 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3379641763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"3.lc_ctrl_stress_all_with_rand_reset.75756368859244931409703332269775789850432667874798405621123401793500596168679","seed":75756368859244931409703332269775789850432667874798405621123401793500596168679,"line":8426,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2876720393 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2876720393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"4.lc_ctrl_stress_all_with_rand_reset.61607114657530654683767359216605965212944994486902229628404781304412018948573","seed":61607114657530654683767359216605965212944994486902229628404781304412018948573,"line":264,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2173342644 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2173342644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"8.lc_ctrl_stress_all_with_rand_reset.91183275763803951907832129695267250823386059090916289244352836864199302171032","seed":91183275763803951907832129695267250823386059090916289244352836864199302171032,"line":150,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 106164343 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 106164343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"9.lc_ctrl_stress_all_with_rand_reset.25495419728051245334906175665591028834939390061007429585799845666173276907536","seed":25495419728051245334906175665591028834939390061007429585799845666173276907536,"line":739,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1610323765 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1610323765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"11.lc_ctrl_stress_all_with_rand_reset.33711990817289473221185393022522091458295308993894788496700965281591589151195","seed":33711990817289473221185393022522091458295308993894788496700965281591589151195,"line":956,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1055642699 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1055642699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"13.lc_ctrl_stress_all_with_rand_reset.7068873255419760840940807481383486466117194029878518163091875572851127894691","seed":7068873255419760840940807481383486466117194029878518163091875572851127894691,"line":4039,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7775069669 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 7775069669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"14.lc_ctrl_stress_all_with_rand_reset.19433163696738357742125541856474779801970467963785048678956307701585800912996","seed":19433163696738357742125541856474779801970467963785048678956307701585800912996,"line":209,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 449043892 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 449043892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"15.lc_ctrl_stress_all_with_rand_reset.105997176819511791514548228475332393807815058378018453765425864294043628166198","seed":105997176819511791514548228475332393807815058378018453765425864294043628166198,"line":10622,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1650814466 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1650814466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"17.lc_ctrl_stress_all_with_rand_reset.39892144659076922664659682263206692543074955023079829998728948495113934938090","seed":39892144659076922664659682263206692543074955023079829998728948495113934938090,"line":3374,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5687458059 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5687458059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"18.lc_ctrl_stress_all_with_rand_reset.87794290560747854422483039258594190296795267986098556007343129994698999226070","seed":87794290560747854422483039258594190296795267986098556007343129994698999226070,"line":1194,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5042965519 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5042965519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"20.lc_ctrl_stress_all_with_rand_reset.43843224989314932043022744223573939589536336733420564467814903768324806431239","seed":43843224989314932043022744223573939589536336733420564467814903768324806431239,"line":8451,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7978554854 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 7978554854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"21.lc_ctrl_stress_all_with_rand_reset.75999719059048742958047392348393859707986276971148511703126924949105840857972","seed":75999719059048742958047392348393859707986276971148511703126924949105840857972,"line":579,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7595389821 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 7595389821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"22.lc_ctrl_stress_all_with_rand_reset.96934721480376393950554693729001847324414147718055834506624378786537008619808","seed":96934721480376393950554693729001847324414147718055834506624378786537008619808,"line":540,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 526197516 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 526197516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"23.lc_ctrl_stress_all_with_rand_reset.56742544636989744050139257475779614428649764832814149324478384664182597100630","seed":56742544636989744050139257475779614428649764832814149324478384664182597100630,"line":2059,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1996137522 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1996137522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"24.lc_ctrl_stress_all_with_rand_reset.4624473972324308995677977614850106161552594508649388698277196710707628591808","seed":4624473972324308995677977614850106161552594508649388698277196710707628591808,"line":150,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 217203622 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 217203622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"27.lc_ctrl_stress_all_with_rand_reset.45247019058389205543136422499468643611129846366437131893386688842253150281354","seed":45247019058389205543136422499468643611129846366437131893386688842253150281354,"line":354,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1704799376 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1704799376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"28.lc_ctrl_stress_all_with_rand_reset.101542077134726850025760277242652721496305933610269991368726184803811666055976","seed":101542077134726850025760277242652721496305933610269991368726184803811666055976,"line":3209,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 858824010 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 858824010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"29.lc_ctrl_stress_all_with_rand_reset.71497086626875403114155209122919481004440416024523516279884878127645988001150","seed":71497086626875403114155209122919481004440416024523516279884878127645988001150,"line":194,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 396660085 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 396660085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"31.lc_ctrl_stress_all_with_rand_reset.64711886780144680220077957859827423531378138661133349416389981611819932842329","seed":64711886780144680220077957859827423531378138661133349416389981611819932842329,"line":488,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4621590653 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4621590653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"33.lc_ctrl_stress_all_with_rand_reset.7914139641446708995448712205508978582500962644892912161308515788421292915848","seed":7914139641446708995448712205508978582500962644892912161308515788421292915848,"line":746,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 501573824 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 501573824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"35.lc_ctrl_stress_all_with_rand_reset.105785393574942487506002752279649316543136470126229146364884902362280924350193","seed":105785393574942487506002752279649316543136470126229146364884902362280924350193,"line":4760,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4814756494 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4814756494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"36.lc_ctrl_stress_all_with_rand_reset.36251177672648657140786283617413274461051370021158007709922714233279668287121","seed":36251177672648657140786283617413274461051370021158007709922714233279668287121,"line":201,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 251814238 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 251814238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"38.lc_ctrl_stress_all_with_rand_reset.82032593459700210788858052349738298817432058809933914413908263967069787691403","seed":82032593459700210788858052349738298817432058809933914413908263967069787691403,"line":1595,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2523593734 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2523593734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"40.lc_ctrl_stress_all_with_rand_reset.18700119536972012203491354033370666082660602493926051536683649485035059379061","seed":18700119536972012203491354033370666082660602493926051536683649485035059379061,"line":209,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 278505229 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 278505229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"41.lc_ctrl_stress_all_with_rand_reset.39781448152673103870012576557501555950263203841370910998367934180696408990488","seed":39781448152673103870012576557501555950263203841370910998367934180696408990488,"line":4238,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 996960122 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 996960122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"44.lc_ctrl_stress_all_with_rand_reset.28770895104888522914444497863156646740431877495878709587093771015385848183800","seed":28770895104888522914444497863156646740431877495878709587093771015385848183800,"line":3912,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2410029441 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2410029441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"48.lc_ctrl_stress_all_with_rand_reset.103427011337040109728284346996541796073960249336086816068265534386693561768502","seed":103427011337040109728284346996541796073960249336086816068265534386693561768502,"line":8315,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 10278314496 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 10278314496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])":[{"name":"lc_ctrl_sec_mubi","qual_name":"33.lc_ctrl_sec_mubi.37891250924013518755264923476472065109198660528095901242994290230802685684290","seed":37891250924013518755264923476472065109198660528095901242994290230802685684290,"line":2764,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_sec_mubi/latest/run.log","log_context":["UVM_ERROR @ 211202895 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 211202895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"47.lc_ctrl_stress_all_with_rand_reset.51360195205191416918734122615757862618274431703032466120542826272344894465749","seed":51360195205191416918734122615757862618274431703032466120542826272344894465749,"line":5467,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 9954470346 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error\n","UVM_INFO @ 9954470346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":999,"total":1030,"percent":96.99029126213593}