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---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"2.rv_dm_delayed_resp_sba_tl_access.39429390060443932173859452565063250890494881048006157340018082756852133263586","seed":39429390060443932173859452565063250890494881048006157340018082756852133263586,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"2.rv_dm_bad_sba_tl_access.2271133973957468971116137670414236609212580460713311204578119204635018229183","seed":2271133973957468971116137670414236609212580460713311204578119204635018229183,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"2.rv_dm_autoincr_sba_tl_access.33178410251420167192571392111774645784046346110104012202913843161109759450658","seed":33178410251420167192571392111774645784046346110104012202913843161109759450658,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"3.rv_dm_sba_tl_access.72198189047151166661065481878280400701213384650656463619223395081334363999937","seed":72198189047151166661065481878280400701213384650656463619223395081334363999937,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"3.rv_dm_delayed_resp_sba_tl_access.6135428344291152288354965173081831243924777933205243719422679839601429173402","seed":6135428344291152288354965173081831243924777933205243719422679839601429173402,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"3.rv_dm_bad_sba_tl_access.24024986032064581979847673090723208312293774731805336039891660974025422121695","seed":24024986032064581979847673090723208312293774731805336039891660974025422121695,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"3.rv_dm_autoincr_sba_tl_access.78778997279108450162988268558069742280937666383771504993268569951585769945398","seed":78778997279108450162988268558069742280937666383771504993268569951585769945398,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"4.rv_dm_sba_tl_access.40551711522715669416342398311480847878371927286983579562639879831473097646138","seed":40551711522715669416342398311480847878371927286983579562639879831473097646138,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"4.rv_dm_delayed_resp_sba_tl_access.98284470295480707272976588465818434629704933131289520852337918427464564782308","seed":98284470295480707272976588465818434629704933131289520852337918427464564782308,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"4.rv_dm_bad_sba_tl_access.69106159511940227564240494189868629901884148889593859897999946123926516181488","seed":69106159511940227564240494189868629901884148889593859897999946123926516181488,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"4.rv_dm_autoincr_sba_tl_access.81762302771590592117905368947027362828544930076651692589695729606638891181194","seed":81762302771590592117905368947027362828544930076651692589695729606638891181194,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"4.rv_dm_stress_all.35329742122940991513590647947286331793816726936305416827807673169872363080502","seed":35329742122940991513590647947286331793816726936305416827807673169872363080502,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log","log_context":["UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"5.rv_dm_sba_tl_access.81743456986618713780014822668792577435869027946641908822853635385629432707084","seed":81743456986618713780014822668792577435869027946641908822853635385629432707084,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"5.rv_dm_delayed_resp_sba_tl_access.12739363929760666539312667224999580676291016874147574275198064064445021760947","seed":12739363929760666539312667224999580676291016874147574275198064064445021760947,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"5.rv_dm_bad_sba_tl_access.93225352117343403943861594272061233107532284648377165381546029686163952570717","seed":93225352117343403943861594272061233107532284648377165381546029686163952570717,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"5.rv_dm_autoincr_sba_tl_access.27090608081332301592737767271541719700015719524310172343320471221397502727401","seed":27090608081332301592737767271541719700015719524310172343320471221397502727401,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"6.rv_dm_sba_tl_access.114538849385562686339252233896271011030301835668337967772667562069104958594057","seed":114538849385562686339252233896271011030301835668337967772667562069104958594057,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"6.rv_dm_delayed_resp_sba_tl_access.40570912067477328550705030405622509925174600768663818812629878635591766002865","seed":40570912067477328550705030405622509925174600768663818812629878635591766002865,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"6.rv_dm_bad_sba_tl_access.61335188880681338193457884968796517440128995530412223660503455626031138247649","seed":61335188880681338193457884968796517440128995530412223660503455626031138247649,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"6.rv_dm_autoincr_sba_tl_access.24540154057093223132086469190759297475493980665582482992999347993731187128704","seed":24540154057093223132086469190759297475493980665582482992999347993731187128704,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"7.rv_dm_sba_tl_access.44281194699439329662409473556875419271942045739579595864405544450662816143701","seed":44281194699439329662409473556875419271942045739579595864405544450662816143701,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"7.rv_dm_delayed_resp_sba_tl_access.92499775994499358105103643638420869663689058073789198033839119734466564885432","seed":92499775994499358105103643638420869663689058073789198033839119734466564885432,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"7.rv_dm_bad_sba_tl_access.46922332097828574537432549507974642298985973167975548614164259840684476019990","seed":46922332097828574537432549507974642298985973167975548614164259840684476019990,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"7.rv_dm_autoincr_sba_tl_access.61008423189685344731435773032757528592425978119663885895735643838527339828530","seed":61008423189685344731435773032757528592425978119663885895735643838527339828530,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"7.rv_dm_stress_all.101316415613452189215580549030351086201351689433659691996948555890606894806935","seed":101316415613452189215580549030351086201351689433659691996948555890606894806935,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_stress_all/latest/run.log","log_context":["UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"8.rv_dm_sba_tl_access.94219845904324566824564272060606163917294783710661622269699573050526838356517","seed":94219845904324566824564272060606163917294783710661622269699573050526838356517,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"8.rv_dm_delayed_resp_sba_tl_access.103374736112878556005438864688432656337725700816734045323447499866605050738964","seed":103374736112878556005438864688432656337725700816734045323447499866605050738964,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"8.rv_dm_bad_sba_tl_access.6566706515566388557137140834407735797538029306679257282546884995351063567225","seed":6566706515566388557137140834407735797538029306679257282546884995351063567225,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"8.rv_dm_autoincr_sba_tl_access.84236062969298125560343563788311376389501968919703751560608484810159509067725","seed":84236062969298125560343563788311376389501968919703751560608484810159509067725,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"9.rv_dm_sba_tl_access.72536581755538307833193867544333730228716517203019516540860039838017015050962","seed":72536581755538307833193867544333730228716517203019516540860039838017015050962,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"9.rv_dm_delayed_resp_sba_tl_access.13537242985549094487646477785678997455548870614150612856699103411647385461972","seed":13537242985549094487646477785678997455548870614150612856699103411647385461972,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"9.rv_dm_bad_sba_tl_access.54439991810948283104831582062490928760912265716915359821516015718763853180200","seed":54439991810948283104831582062490928760912265716915359821516015718763853180200,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"9.rv_dm_autoincr_sba_tl_access.98282894671130458741534666017822299237554713811775769288383423798588234894363","seed":98282894671130458741534666017822299237554713811775769288383423798588234894363,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"10.rv_dm_sba_tl_access.35712352676022078272406840188983795875567637004188351459174229396285684969771","seed":35712352676022078272406840188983795875567637004188351459174229396285684969771,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/10.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"10.rv_dm_delayed_resp_sba_tl_access.21340688000530903839922293171074076292230218185444554385006144800716258992805","seed":21340688000530903839922293171074076292230218185444554385006144800716258992805,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/10.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"10.rv_dm_bad_sba_tl_access.76537274647144097427042902787218365937419984776645930052729093705831126203211","seed":76537274647144097427042902787218365937419984776645930052729093705831126203211,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/10.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"10.rv_dm_autoincr_sba_tl_access.112590576525807681414513292679591913395286955216735885145586315791747173866944","seed":112590576525807681414513292679591913395286955216735885145586315791747173866944,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"11.rv_dm_sba_tl_access.67199746083409303635428148982577423277669026869912658007868532861606144300800","seed":67199746083409303635428148982577423277669026869912658007868532861606144300800,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"11.rv_dm_delayed_resp_sba_tl_access.27474850627798316607197999522881352338642425529417075801524200675814651611171","seed":27474850627798316607197999522881352338642425529417075801524200675814651611171,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/11.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"11.rv_dm_bad_sba_tl_access.86796958081609470532201136168500263706214441074193470981534485140927787805991","seed":86796958081609470532201136168500263706214441074193470981534485140927787805991,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/11.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"11.rv_dm_autoincr_sba_tl_access.82473529267413263736861522926140091710998652621662134260389817000779709397583","seed":82473529267413263736861522926140091710998652621662134260389817000779709397583,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"12.rv_dm_sba_tl_access.52560539265608035012228966668092120526868645092896490215106117940922511295059","seed":52560539265608035012228966668092120526868645092896490215106117940922511295059,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/12.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"12.rv_dm_delayed_resp_sba_tl_access.1737072306082133786648761858170311392556524994401223419784276293606413747508","seed":1737072306082133786648761858170311392556524994401223419784276293606413747508,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/12.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"12.rv_dm_bad_sba_tl_access.13939851201434965816888707123304383015715518394265578224189144245679676278883","seed":13939851201434965816888707123304383015715518394265578224189144245679676278883,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"12.rv_dm_autoincr_sba_tl_access.33813087930466849196066083563054506746995560943553172287533663319005099897285","seed":33813087930466849196066083563054506746995560943553172287533663319005099897285,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"13.rv_dm_sba_tl_access.70483142076561987150782891331593355627100298019262110528092500817804539530882","seed":70483142076561987150782891331593355627100298019262110528092500817804539530882,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/13.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"13.rv_dm_delayed_resp_sba_tl_access.51467901661476264806463763852150890529224808459438096309648153427286408973076","seed":51467901661476264806463763852150890529224808459438096309648153427286408973076,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/13.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"13.rv_dm_bad_sba_tl_access.69452020043870021322980018335999666427018235620294038434807372310538363193827","seed":69452020043870021322980018335999666427018235620294038434807372310538363193827,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/13.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"13.rv_dm_autoincr_sba_tl_access.41102264629772110564381741358765742905985326107466084496315524492751866723122","seed":41102264629772110564381741358765742905985326107466084496315524492751866723122,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"13.rv_dm_stress_all.89699912302714501626049203606717144968683088542271008301758146086230119954787","seed":89699912302714501626049203606717144968683088542271008301758146086230119954787,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/13.rv_dm_stress_all/latest/run.log","log_context":["UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"14.rv_dm_sba_tl_access.70855857602459399324533047976876861979419252488794901494148702405184876489426","seed":70855857602459399324533047976876861979419252488794901494148702405184876489426,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/14.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"14.rv_dm_delayed_resp_sba_tl_access.32103461340392862753690227966859671533852132738823558732633328581773227892848","seed":32103461340392862753690227966859671533852132738823558732633328581773227892848,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/14.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"14.rv_dm_bad_sba_tl_access.46485513223530910451293661329494761988318287400260621222191789942908730182096","seed":46485513223530910451293661329494761988318287400260621222191789942908730182096,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/14.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"14.rv_dm_autoincr_sba_tl_access.86347063789460807379328128793391211399795682767847174934750030791224072213490","seed":86347063789460807379328128793391211399795682767847174934750030791224072213490,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"15.rv_dm_sba_tl_access.85079736621804591290399764914771627645162496327911683252241949659646591353585","seed":85079736621804591290399764914771627645162496327911683252241949659646591353585,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/15.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"15.rv_dm_delayed_resp_sba_tl_access.73780344069498773594887316234254029040443888265631028146662256265555424056101","seed":73780344069498773594887316234254029040443888265631028146662256265555424056101,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/15.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"15.rv_dm_bad_sba_tl_access.91971814019711866778035683992783935566926208742379583938207425916566160065014","seed":91971814019711866778035683992783935566926208742379583938207425916566160065014,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"15.rv_dm_autoincr_sba_tl_access.28303985926803347982381965517856905670113288768551847014115363544039585190914","seed":28303985926803347982381965517856905670113288768551847014115363544039585190914,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"16.rv_dm_sba_tl_access.4173007596941721202263242288252120419364898489500540050163825572536298041658","seed":4173007596941721202263242288252120419364898489500540050163825572536298041658,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/16.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"16.rv_dm_delayed_resp_sba_tl_access.65660331138218915567816438451049062805032663852648192426649443954913881310383","seed":65660331138218915567816438451049062805032663852648192426649443954913881310383,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/16.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"16.rv_dm_bad_sba_tl_access.70735085637088843617252875031835564958375843451373659911661297494638685654067","seed":70735085637088843617252875031835564958375843451373659911661297494638685654067,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/16.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"16.rv_dm_autoincr_sba_tl_access.29208067722719494489317513855315979590884211378091854436188896409341952618450","seed":29208067722719494489317513855315979590884211378091854436188896409341952618450,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/16.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"16.rv_dm_stress_all.100580528256054871496151519931384864855114087431450765650131279435862433125527","seed":100580528256054871496151519931384864855114087431450765650131279435862433125527,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/16.rv_dm_stress_all/latest/run.log","log_context":["UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"17.rv_dm_sba_tl_access.83456390894392416318782340327702513656883522871268213280593188147648513195736","seed":83456390894392416318782340327702513656883522871268213280593188147648513195736,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/17.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"17.rv_dm_delayed_resp_sba_tl_access.76936815413027051268095617776953285133051439316861334795883715764089964600146","seed":76936815413027051268095617776953285133051439316861334795883715764089964600146,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/17.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"17.rv_dm_bad_sba_tl_access.5473473291997212364690738478638241697318829786226078446842332203482000167899","seed":5473473291997212364690738478638241697318829786226078446842332203482000167899,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/17.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"17.rv_dm_autoincr_sba_tl_access.54286315885707215044596535267178188003387690598942020265841523599684835762858","seed":54286315885707215044596535267178188003387690598942020265841523599684835762858,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"18.rv_dm_sba_tl_access.87128912106444103201603272959843484071614922722667030127407130157111382035819","seed":87128912106444103201603272959843484071614922722667030127407130157111382035819,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/18.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"18.rv_dm_delayed_resp_sba_tl_access.49417518716582620303259732071051824053759018226115819066889382257375730288640","seed":49417518716582620303259732071051824053759018226115819066889382257375730288640,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/18.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"18.rv_dm_bad_sba_tl_access.74290662539043924602687830823815198916841647350857056271683714907743899524013","seed":74290662539043924602687830823815198916841647350857056271683714907743899524013,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/18.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"18.rv_dm_autoincr_sba_tl_access.28508613735938631395461648022612357603901640225450038339404208719445937126538","seed":28508613735938631395461648022612357603901640225450038339404208719445937126538,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"19.rv_dm_sba_tl_access.112191886966356173095848917212153702545227279327668775809591040421051908304198","seed":112191886966356173095848917212153702545227279327668775809591040421051908304198,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/19.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"19.rv_dm_delayed_resp_sba_tl_access.26136814037584892206061388057272621522504116989069085375356592870474037106591","seed":26136814037584892206061388057272621522504116989069085375356592870474037106591,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/19.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"19.rv_dm_bad_sba_tl_access.16898371946694092999963587290693119514853061744947520771685632882437569860924","seed":16898371946694092999963587290693119514853061744947520771685632882437569860924,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/19.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"19.rv_dm_autoincr_sba_tl_access.1912824467462457786502515537448286249495208060499493160886606118044094805695","seed":1912824467462457786502515537448286249495208060499493160886606118044094805695,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/19.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"34.rv_dm_stress_all.5652260984782622804090111443168048729619564521521758083072183175282195186598","seed":5652260984782622804090111443168048729619564521521758083072183175282195186598,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/34.rv_dm_stress_all/latest/run.log","log_context":["UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"47.rv_dm_stress_all.41601114627846286085325628530822920273722000788911259334314644950193906679013","seed":41601114627846286085325628530822920273722000788911259334314644950193906679013,"line":82,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/47.rv_dm_stress_all/latest/run.log","log_context":["UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == *'b* (* [*] vs * [*])":[{"name":"rv_dm_mem_tl_access_resuming","qual_name":"0.rv_dm_mem_tl_access_resuming.50640319218920492879695899412781812107061062549276720184146866883585849547238","seed":50640319218920492879695899412781812107061062549276720184146866883585849547238,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest/run.log","log_context":["UVM_ERROR @ 209323576 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 209323576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_mem_tl_access_resuming","qual_name":"1.rv_dm_mem_tl_access_resuming.28688485965187773843302149443127516675566343802391295498339329912635213453432","seed":28688485965187773843302149443127516675566343802391295498339329912635213453432,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest/run.log","log_context":["UVM_ERROR @  60715128 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  60715128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"1.rv_dm_stress_all.33324054838440925487103631769921347364177906735222093727148658066299827282496","seed":33324054838440925487103631769921347364177906735222093727148658066299827282496,"line":84,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 6621744810 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 6621744810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"2.rv_dm_stress_all.10833370485359672140442353171583681252805748411836872774896056233693598000745","seed":10833370485359672140442353171583681252805748411836872774896056233693598000745,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 256463194 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 256463194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"5.rv_dm_stress_all.71183964276420389253139583899774756119986226374117748557814525053640111638289","seed":71183964276420389253139583899774756119986226374117748557814525053640111638289,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1827407739 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1827407739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"8.rv_dm_stress_all.53728480398367001153245786561996743063258659824102449151445503803361160790819","seed":53728480398367001153245786561996743063258659824102449151445503803361160790819,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @  86303366 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  86303366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"11.rv_dm_stress_all.45019827910938890725837885549551699733052251184290405996358755670431042579372","seed":45019827910938890725837885549551699733052251184290405996358755670431042579372,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/11.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 169924005 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 169924005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"19.rv_dm_stress_all.61347937946224600983726785533580564668302418892680573074694194038529882357449","seed":61347937946224600983726785533580564668302418892680573074694194038529882357449,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/19.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 339177962 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 339177962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"22.rv_dm_stress_all.14328193398170464274566277131274864914895736745620993062951218065937042863607","seed":14328193398170464274566277131274864914895736745620993062951218065937042863607,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/22.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 125332602 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 125332602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"25.rv_dm_stress_all.38358195123071707949885063523758785709576235453467446351575767628857732075902","seed":38358195123071707949885063523758785709576235453467446351575767628857732075902,"line":83,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/25.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 2213874849 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 2213874849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"28.rv_dm_stress_all.62917122250018825175563233842292556720987085915393550518611612633364313376430","seed":62917122250018825175563233842292556720987085915393550518611612633364313376430,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/28.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 863686346 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 863686346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"32.rv_dm_stress_all.54011601464575045265588898795413009862154498683470297142598933939407493927236","seed":54011601464575045265588898795413009862154498683470297142598933939407493927236,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/32.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1410625175 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1410625175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"33.rv_dm_stress_all.108160305570642905717146034741232056280427905368985047135101674162676828721022","seed":108160305570642905717146034741232056280427905368985047135101674162676828721022,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/33.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 2110303268 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 2110303268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"37.rv_dm_stress_all.49146087626785704564537689702377924759441079700643122637310526777819624076430","seed":49146087626785704564537689702377924759441079700643122637310526777819624076430,"line":99,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/37.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 3697606772 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 3697606772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [*] vs * [*])":[{"name":"rv_dm_hart_unavail","qual_name":"0.rv_dm_hart_unavail.753104768841024070428942172497859357981848802845942560444945149323405023835","seed":753104768841024070428942172497859357981848802845942560444945149323405023835,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest/run.log","log_context":["UVM_ERROR @ 135997921 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 135997921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_hart_unavail","qual_name":"1.rv_dm_hart_unavail.105769150741884722429896026732921711555872824028316906880647321157103503080605","seed":105769150741884722429896026732921711555872824028316906880647321157103503080605,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_hart_unavail/latest/run.log","log_context":["UVM_ERROR @ 102254113 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 102254113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_hart_unavail","qual_name":"2.rv_dm_hart_unavail.37694878722026005788388990505103984168189479995239680356031351396739065357302","seed":37694878722026005788388990505103984168189479995239680356031351396739065357302,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_hart_unavail/latest/run.log","log_context":["UVM_ERROR @ 107289131 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 107289131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_hart_unavail","qual_name":"3.rv_dm_hart_unavail.32867395200946090560430157437474548030459417307186925058052287829341571696134","seed":32867395200946090560430157437474548030459417307186925058052287829341571696134,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_hart_unavail/latest/run.log","log_context":["UVM_ERROR @ 327587488 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 327587488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_hart_unavail","qual_name":"4.rv_dm_hart_unavail.22664322559789291402572068167175414359242689622857022878721688326231466984464","seed":22664322559789291402572068167175414359242689622857022878721688326231466984464,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_hart_unavail/latest/run.log","log_context":["UVM_ERROR @  27871034 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  27871034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"4.rv_dm_stress_all_with_rand_reset.87659444861631632403549873407584702039102152705282463773650859313547610074381","seed":87659444861631632403549873407584702039102152705282463773650859313547610074381,"line":107,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2944972166 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 2944972166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"7.rv_dm_stress_all_with_rand_reset.65480636973141871624628445313884241034980852746430717798432493550972027352295","seed":65480636973141871624628445313884241034980852746430717798432493550972027352295,"line":103,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1309127874 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1309127874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"9.rv_dm_stress_all.60830104608878082853027922131820203243307354190247229697389487711697913519489","seed":60830104608878082853027922131820203243307354190247229697389487711697913519489,"line":85,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 7711719686 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 7711719686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"18.rv_dm_stress_all.31609572025911904203992473892205762372853624330781045981525046153318470564839","seed":31609572025911904203992473892205762372853624330781045981525046153318470564839,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/18.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 597588693 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 597588693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"21.rv_dm_stress_all.40487061504773155948033593311563808257976946897043400469559932578147170005192","seed":40487061504773155948033593311563808257976946897043400469559932578147170005192,"line":84,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/21.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 3137150063 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 3137150063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"24.rv_dm_stress_all.65384254153987134074211425980196305322995405220346279801115898817035486940582","seed":65384254153987134074211425980196305322995405220346279801115898817035486940582,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/24.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 447766963 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 447766963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"26.rv_dm_stress_all.50385912609286907941812530550637346038820716220787425813183842304245790309108","seed":50385912609286907941812530550637346038820716220787425813183842304245790309108,"line":81,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/26.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 2385459348 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 2385459348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"27.rv_dm_stress_all.88272304047826011573007414426364845492360335330813781683170650285000109665053","seed":88272304047826011573007414426364845492360335330813781683170650285000109665053,"line":81,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/27.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1296945203 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1296945203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"30.rv_dm_stress_all.24079371367295193511630134248202897088577561183481635289298696414658219088120","seed":24079371367295193511630134248202897088577561183481635289298696414658219088120,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/30.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 345216080 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 345216080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"35.rv_dm_stress_all.2400945732780640550487688849691861000365432948210278064926111731781050369701","seed":2400945732780640550487688849691861000365432948210278064926111731781050369701,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/35.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @  79991350 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  79991350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"36.rv_dm_stress_all.94378132412105432784303237725567132692437209416153727015948375646418141425595","seed":94378132412105432784303237725567132692437209416153727015948375646418141425595,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/36.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 127886605 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 127886605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"38.rv_dm_stress_all.110361056915878791909343709620221597249444997027004944923333203515292983235548","seed":110361056915878791909343709620221597249444997027004944923333203515292983235548,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/38.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 140985153 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 140985153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"40.rv_dm_stress_all.20312670027562754729148243365609092295765662655110087248024475191383090338078","seed":20312670027562754729148243365609092295765662655110087248024475191383090338078,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/40.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1798410689 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1798410689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"46.rv_dm_stress_all.104341024835662393056989427111522462485469979293238636458094101268746315553668","seed":104341024835662393056989427111522462485469979293238636458094101268746315553668,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/46.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 433301594 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 433301594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"48.rv_dm_stress_all.109493574604082266444452198465977198110680029746801077223897108192269834593874","seed":109493574604082266444452198465977198110680029746801077223897108192269834593874,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/48.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @  62751683 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  62751683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"49.rv_dm_stress_all.24541970291484338877341544543637047403253358640191796246877931096062951292443","seed":24541970291484338877341544543637047403253358640191796246877931096062951292443,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/49.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 308508190 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 308508190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*])":[{"name":"rv_dm_jtag_dmi_debug_disabled","qual_name":"0.rv_dm_jtag_dmi_debug_disabled.112725254830675543254564870106986216722334376927441875120945266773329145804950","seed":112725254830675543254564870106986216722334376927441875120945266773329145804950,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log","log_context":["UVM_ERROR @ 320064549 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3810271918 [0xe31c22ae] vs 0 [0x0]) \n","UVM_INFO @ 320064549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_jtag_dmi_debug_disabled","qual_name":"1.rv_dm_jtag_dmi_debug_disabled.113726693133171103506355029609624865988388534786518980299866854510905650317495","seed":113726693133171103506355029609624865988388534786518980299866854510905650317495,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest/run.log","log_context":["UVM_ERROR @ 207336614 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (4276000887 [0xfede9877] vs 0 [0x0]) \n","UVM_INFO @ 207336614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"3.rv_dm_stress_all.61139416037427741043438186437170104683310283335084616991978116394048796769964","seed":61139416037427741043438186437170104683310283335084616991978116394048796769964,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 524257044 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3746400696 [0xdf4d89b8] vs 0 [0x0]) \n","UVM_INFO @ 524257044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"6.rv_dm_stress_all.96444565002286541543335924999854202652424828673875328466318078075107212215492","seed":96444565002286541543335924999854202652424828673875328466318078075107212215492,"line":83,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 2938259591 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (357346673 [0x154cad71] vs 0 [0x0]) \n","UVM_INFO @ 2938259591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"9.rv_dm_stress_all_with_rand_reset.14529478899798905994455688380970419961530079993266751154394364258189492414369","seed":14529478899798905994455688380970419961530079993266751154394364258189492414369,"line":100,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1017557791 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (63231642 [0x3c4d69a] vs 0 [0x0]) \n","UVM_INFO @ 1017557791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"12.rv_dm_stress_all.17734381949151111263190568414067522016672151209581901613945163699458477478006","seed":17734381949151111263190568414067522016672151209581901613945163699458477478006,"line":81,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/12.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1458485887 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1708071875 [0x65cf1bc3] vs 0 [0x0]) \n","UVM_INFO @ 1458485887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"14.rv_dm_stress_all.114684680944570011358188959788139189982194294023313512415484026843225249729249","seed":114684680944570011358188959788139189982194294023313512415484026843225249729249,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/14.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 154924980 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2581794016 [0x99e30ce0] vs 0 [0x0]) \n","UVM_INFO @ 154924980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"17.rv_dm_stress_all.20576937604386989209581562553438783293713224398963224153970865391425876138515","seed":20576937604386989209581562553438783293713224398963224153970865391425876138515,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/17.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 818031274 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (146127626 [0x8b5bb0a] vs 0 [0x0]) \n","UVM_INFO @ 818031274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"20.rv_dm_stress_all.42624701166937967986277898191300462234974984287938888153783096552996576019396","seed":42624701166937967986277898191300462234974984287938888153783096552996576019396,"line":81,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/20.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 7592753780 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (9937033 [0x97a089] vs 0 [0x0]) \n","UVM_INFO @ 7592753780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"23.rv_dm_stress_all.98986689782070879561422606276876144601162234442215193983433729879352597329123","seed":98986689782070879561422606276876144601162234442215193983433729879352597329123,"line":81,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/23.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 2913588843 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1999472358 [0x772d86e6] vs 0 [0x0]) \n","UVM_INFO @ 2913588843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"39.rv_dm_stress_all.75258501519895391508258027796832367973682501419469450183083884917450402387458","seed":75258501519895391508258027796832367973682501419469450183083884917450402387458,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/39.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 275330055 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2459052480 [0x929229c0] vs 0 [0x0]) \n","UVM_INFO @ 275330055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"45.rv_dm_stress_all.72223778767847016603741594629916663399528134307898297146380879074415221942359","seed":72223778767847016603741594629916663399528134307898297146380879074415221942359,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/45.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 9663287063 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (164179245 [0x9c92d2d] vs 0 [0x0]) \n","UVM_INFO @ 9663287063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (cip_base_vseq.sv:1170) [rv_dm_common_vseq] Check failed (vseq_done)":[{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"2.rv_dm_stress_all_with_rand_reset.12705176229401446225572204288869937409577560358159712658544789811822672210611","seed":12705176229401446225572204288869937409577560358159712658544789811822672210611,"line":113,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 2509359759 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)  \n","UVM_INFO @ 2509359759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"3.rv_dm_stress_all_with_rand_reset.4863074208421871257133804563834603548679783660248836275385954752134930338641","seed":4863074208421871257133804563834603548679783660248836275385954752134930338641,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 4266319157 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)  \n","UVM_INFO @ 4266319157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"6.rv_dm_stress_all_with_rand_reset.25626740679202954462709247833209805522475681543257139021812772474869631147366","seed":25626740679202954462709247833209805522475681543257139021812772474869631147366,"line":140,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 5922879508 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)  \n","UVM_INFO @ 5922879508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"8.rv_dm_stress_all_with_rand_reset.71575283372035715625584383711934236717669982832170826643927573554185547385189","seed":71575283372035715625584383711934236717669982832170826643927573554185547385189,"line":88,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 3250144641 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)  \n","UVM_INFO @ 3250144641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [*] vs * [*])":[{"name":"rv_dm_buffered_enable","qual_name":"3.rv_dm_buffered_enable.49232660221511815000299393795582774522109016062125574498603921981193614347275","seed":49232660221511815000299393795582774522109016062125574498603921981193614347275,"line":88,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_buffered_enable/latest/run.log","log_context":["UVM_ERROR @ 267471016 ps: (rv_dm_buffered_enable_vseq.sv:164) [uvm_test_top.env.virtual_sequencer.rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 267471016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_buffered_enable","qual_name":"6.rv_dm_buffered_enable.39992482162238410188432365287616232762873397141747400803709149220288461042533","seed":39992482162238410188432365287616232762873397141747400803709149220288461042533,"line":84,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_buffered_enable/latest/run.log","log_context":["UVM_ERROR @  92546899 ps: (rv_dm_buffered_enable_vseq.sv:164) [uvm_test_top.env.virtual_sequencer.rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  92546899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_buffered_enable","qual_name":"8.rv_dm_buffered_enable.35684400360943272198051429095327042540287784906141694597360773297107166784132","seed":35684400360943272198051429095327042540287784906141694597360773297107166784132,"line":88,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_buffered_enable/latest/run.log","log_context":["UVM_ERROR @ 513322272 ps: (rv_dm_buffered_enable_vseq.sv:164) [uvm_test_top.env.virtual_sequencer.rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 513322272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job timed out after * minutes":[{"name":"rv_dm_stress_all","qual_name":"10.rv_dm_stress_all.26273918238918948220458527759137409626557552974286440386499479946958756020506","seed":26273918238918948220458527759137409626557552974286440386499479946958756020506,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/10.rv_dm_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"rv_dm_stress_all","qual_name":"29.rv_dm_stress_all.952168724068387621824258924135723931222104793959567153813831948302420321704","seed":952168724068387621824258924135723931222104793959567153813831948302420321704,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/29.rv_dm_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"rv_dm_stress_all","qual_name":"31.rv_dm_stress_all.34222211311508906070512510197723518639611033327205174544552437622323561433861","seed":34222211311508906070512510197723518639611033327205174544552437622323561433861,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/31.rv_dm_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"rv_dm_stress_all","qual_name":"44.rv_dm_stress_all.115300352731610975758176955218499996156261982644892925022462792523967364004959","seed":115300352731610975758176955218499996156261982644892925022462792523967364004959,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/44.rv_dm_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]}]}},"passed":338,"total":483,"percent":69.97929606625259}