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---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"4.alert_handler_stress_all_with_rand_reset.49329718211786512370758869774937160488156123800692954655479976236498011824364","seed":49329718211786512370758869774937160488156123800692954655479976236498011824364,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 114334861 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 114334861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"6.alert_handler_stress_all_with_rand_reset.43483672347930780292013643260125289113360910855068066491402215909640642117076","seed":43483672347930780292013643260125289113360910855068066491402215909640642117076,"line":134,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8094712664 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 8094712664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"9.alert_handler_stress_all_with_rand_reset.3036300116251136578906558395681555229222510901054419226852590439404778628083","seed":3036300116251136578906558395681555229222510901054419226852590439404778628083,"line":129,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1992205036 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1992205036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"12.alert_handler_stress_all_with_rand_reset.113454593681275458088295130684526604457305199417315233799166957792527751472458","seed":113454593681275458088295130684526604457305199417315233799166957792527751472458,"line":172,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4938612879 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4938612879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"13.alert_handler_stress_all_with_rand_reset.20313050112431475084196858156472394722539756448791942074765287165177916578329","seed":20313050112431475084196858156472394722539756448791942074765287165177916578329,"line":90,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1342135767 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1342135767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"16.alert_handler_stress_all_with_rand_reset.40265922420548978431106626519093050550296524639945105236854808608391102311739","seed":40265922420548978431106626519093050550296524639945105236854808608391102311739,"line":119,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 762452496 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 762452496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"19.alert_handler_stress_all_with_rand_reset.81009057060067796982552345277339662974184173440551931867534169291755663336056","seed":81009057060067796982552345277339662974184173440551931867534169291755663336056,"line":88,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 753342568 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 753342568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"21.alert_handler_stress_all_with_rand_reset.33156492145610743464132674756049610701487384073156077259737929954656393317449","seed":33156492145610743464132674756049610701487384073156077259737929954656393317449,"line":119,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2224256477 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2224256477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"24.alert_handler_stress_all_with_rand_reset.83600362997340956060933510221855536194124289760954884361442179828556625106544","seed":83600362997340956060933510221855536194124289760954884361442179828556625106544,"line":83,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1543724560 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1543724560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"25.alert_handler_stress_all_with_rand_reset.16160511507193245188686361372415983690430848230372613448763301883115198642197","seed":16160511507193245188686361372415983690430848230372613448763301883115198642197,"line":83,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/25.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2187153065 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2187153065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"26.alert_handler_stress_all_with_rand_reset.29116049668080402839561923196012498848663651879731783609905197614968537993470","seed":29116049668080402839561923196012498848663651879731783609905197614968537993470,"line":121,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/26.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7801836649 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 7801836649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"27.alert_handler_stress_all_with_rand_reset.62341448830679321781464866499432365600747750452192651520881821034708575612065","seed":62341448830679321781464866499432365600747750452192651520881821034708575612065,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 892294297 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 892294297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"31.alert_handler_stress_all_with_rand_reset.55362917690689146126682419721316604510127273612721787156523501592910132968343","seed":55362917690689146126682419721316604510127273612721787156523501592910132968343,"line":203,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2513848828 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2513848828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"35.alert_handler_stress_all_with_rand_reset.35623479305589479266755699036753088481098791388917796648351665486101606957758","seed":35623479305589479266755699036753088481098791388917796648351665486101606957758,"line":83,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/35.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 104170561 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 104170561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"36.alert_handler_stress_all_with_rand_reset.76116843511690791026563527367081840045325399810364067619697739027589693500706","seed":76116843511690791026563527367081840045325399810364067619697739027589693500706,"line":112,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/36.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6840825217 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 6840825217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"40.alert_handler_stress_all_with_rand_reset.87834296335914545447819969219935518336047124987353983529360906303508079440135","seed":87834296335914545447819969219935518336047124987353983529360906303508079440135,"line":143,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 20939179495 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 20939179495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"41.alert_handler_stress_all_with_rand_reset.46728259184683248064895471725643063109071800025691247055254105272387405219949","seed":46728259184683248064895471725643063109071800025691247055254105272387405219949,"line":106,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/41.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7259053199 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 7259053199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"44.alert_handler_stress_all_with_rand_reset.14470846869109223977693829269916381724341548721295719752626061763305490700415","seed":14470846869109223977693829269916381724341548721295719752626061763305490700415,"line":107,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/44.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1056772939 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1056772939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"45.alert_handler_stress_all_with_rand_reset.21289089886677098088084377083493421899905203640826203256673549962384529658223","seed":21289089886677098088084377083493421899905203640826203256673549962384529658223,"line":184,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/45.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2721402268 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2721402268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"46.alert_handler_stress_all_with_rand_reset.72979674737316238940814596758243808037990497292873611882063587718623652741814","seed":72979674737316238940814596758243808037990497292873611882063587718623652741814,"line":127,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5299082643 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5299082643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model.":[{"name":"alert_handler_lpg","qual_name":"1.alert_handler_lpg.5346160095120667422311572830865042977127437345808931793474439250283764264211","seed":5346160095120667422311572830865042977127437345808931793474439250283764264211,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_lpg/latest/run.log","log_context":["UVM_ERROR @ 1881926707 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 1881926707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_lpg","qual_name":"3.alert_handler_lpg.101399857543118727743465790863967536488307297335465876036165567520621246899425","seed":101399857543118727743465790863967536488307297335465876036165567520621246899425,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_lpg/latest/run.log","log_context":["UVM_ERROR @ 995445833 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 995445833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"45.alert_handler_ping_timeout.81260962957596057242057318678617041961422548039505071820791304197473269536521","seed":81260962957596057242057318678617041961422548039505071820791304197473269536521,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 460962821 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 460962821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"46.alert_handler_ping_timeout.4001375979667373677349095942257621515765644139766650202854730202403424171547","seed":4001375979667373677349095942257621515765644139766650202854730202403424171547,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 740966125 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 740966125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_lpg","qual_name":"46.alert_handler_lpg.99892423173710924800358435298833936159741700494882110834292454170505252486662","seed":99892423173710924800358435298833936159741700494882110834292454170505252486662,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_lpg/latest/run.log","log_context":["UVM_ERROR @ 5605043144 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 5605043144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state":[{"name":"alert_handler_ping_timeout","qual_name":"2.alert_handler_ping_timeout.68139889141075991540589581579802917435009322084797840995619882760070032111983","seed":68139889141075991540589581579802917435009322084797840995619882760070032111983,"line":90,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 3243277817 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 3243277817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"3.alert_handler_ping_timeout.48845586730843032318404170870321892979985510144713183368434434916481446744384","seed":48845586730843032318404170870321892979985510144713183368434434916481446744384,"line":93,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 2819247731 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 2819247731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"4.alert_handler_ping_timeout.90382003967817475156252872172070802912875207074653007994974310185571903765054","seed":90382003967817475156252872172070802912875207074653007994974310185571903765054,"line":138,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 7761026756 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 7761026756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"5.alert_handler_ping_timeout.80583047456993405926596918131240209734845555109414611028650105670823465136904","seed":80583047456993405926596918131240209734845555109414611028650105670823465136904,"line":129,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 6276818267 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 6276818267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"6.alert_handler_ping_timeout.80969631959858878046831012181722128457211385025561244610266876985902792307715","seed":80969631959858878046831012181722128457211385025561244610266876985902792307715,"line":93,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 9385701626 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 9385701626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"7.alert_handler_ping_timeout.103907798006876775739296405316396763929507018942488918399901220548200566141916","seed":103907798006876775739296405316396763929507018942488918399901220548200566141916,"line":87,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 10159070772 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 10159070772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"8.alert_handler_ping_timeout.56364502561599629967004572983228434754305644370456141277354366523401974025961","seed":56364502561599629967004572983228434754305644370456141277354366523401974025961,"line":87,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 1431218630 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 1431218630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"10.alert_handler_ping_timeout.7311819802248280125911845272561857437404955044149546003987229802200523736538","seed":7311819802248280125911845272561857437404955044149546003987229802200523736538,"line":90,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 6377591537 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 6377591537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"11.alert_handler_ping_timeout.92955243195343188689507843094944189376386108856270584022253255829932564234027","seed":92955243195343188689507843094944189376386108856270584022253255829932564234027,"line":111,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 25053553685 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 25053553685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"12.alert_handler_ping_timeout.28774276790553643492183836083609038050673904229647305312277968491064184362504","seed":28774276790553643492183836083609038050673904229647305312277968491064184362504,"line":96,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 2618307114 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 2618307114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"14.alert_handler_ping_timeout.50996598691497531385866801999511273160375468666118561690061484609444603488394","seed":50996598691497531385866801999511273160375468666118561690061484609444603488394,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 3614791372 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 3614791372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"15.alert_handler_ping_timeout.1899268089431634282979945304097435102905493668560516793176080072888287008497","seed":1899268089431634282979945304097435102905493668560516793176080072888287008497,"line":135,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 11873730719 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 11873730719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"17.alert_handler_ping_timeout.9950059937337979368260373027354597601667865829552295170710822021028485108068","seed":9950059937337979368260373027354597601667865829552295170710822021028485108068,"line":115,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 31860974192 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 31860974192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"18.alert_handler_ping_timeout.53547056306471527673608314336907347086582036649114824707264879212598321541310","seed":53547056306471527673608314336907347086582036649114824707264879212598321541310,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 3982856320 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 3982856320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"22.alert_handler_ping_timeout.79729357817242130533244908367668148017362443723816515438151862884015332141477","seed":79729357817242130533244908367668148017362443723816515438151862884015332141477,"line":122,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 71435623365 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 71435623365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"24.alert_handler_ping_timeout.77948333592970225549875021771987158760509914791728568685626695741668244382483","seed":77948333592970225549875021771987158760509914791728568685626695741668244382483,"line":95,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 7969632733 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 7969632733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"25.alert_handler_ping_timeout.89178905621533919825198591473912315095555220148460718030486036295148401719289","seed":89178905621533919825198591473912315095555220148460718030486036295148401719289,"line":141,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/25.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 9190649580 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 9190649580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"26.alert_handler_ping_timeout.48240674090096882301651974780037176843196291946426779305702474907780063102598","seed":48240674090096882301651974780037176843196291946426779305702474907780063102598,"line":105,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 19510005907 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 19510005907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"27.alert_handler_ping_timeout.39955951099802769761897526243539134946318386499899948101214136855060378005515","seed":39955951099802769761897526243539134946318386499899948101214136855060378005515,"line":105,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 19609473891 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 19609473891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"30.alert_handler_ping_timeout.107849892281255555564838256187420373637025088169487552985274374284392957388326","seed":107849892281255555564838256187420373637025088169487552985274374284392957388326,"line":112,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/30.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 3605844233 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 3605844233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"33.alert_handler_ping_timeout.35682994503967136468881891783304524507590620187748789187555107360607639324581","seed":35682994503967136468881891783304524507590620187748789187555107360607639324581,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 1834513362 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 1834513362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"35.alert_handler_ping_timeout.76113427366977572823110525498622770208689603153842149336263531195055942394198","seed":76113427366977572823110525498622770208689603153842149336263531195055942394198,"line":120,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 52268204737 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 52268204737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"36.alert_handler_ping_timeout.104787236173097550278740822112012947998058474589101467009154885413289144575436","seed":104787236173097550278740822112012947998058474589101467009154885413289144575436,"line":93,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/36.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 5793149035 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 5793149035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"37.alert_handler_ping_timeout.86067969029075735921708745667500645611364254683730718620220398739838016384572","seed":86067969029075735921708745667500645611364254683730718620220398739838016384572,"line":117,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 6916211366 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 6916211366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"38.alert_handler_ping_timeout.38767671193451092457423683402240943037033103353466512232212200576448275513393","seed":38767671193451092457423683402240943037033103353466512232212200576448275513393,"line":90,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 17099374534 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 17099374534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"40.alert_handler_ping_timeout.70769948996863511442496355776595425243890215522929521907162780856832958737678","seed":70769948996863511442496355776595425243890215522929521907162780856832958737678,"line":114,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 51659711705 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 51659711705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"42.alert_handler_ping_timeout.12196757632689205683321812842206256992076427032546574557138680269354363521797","seed":12196757632689205683321812842206256992076427032546574557138680269354363521797,"line":99,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/42.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 9978008543 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 9978008543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"49.alert_handler_ping_timeout.97529918630931840090756688995568872370713655231709424566252610516541235227978","seed":97529918630931840090756688995568872370713655231709424566252610516541235227978,"line":102,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 13016895273 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 13016895273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"alert_handler_lpg","qual_name":"8.alert_handler_lpg.24125220033138090822720669874076652947313735594503467579323097557938317788702","seed":24125220033138090822720669874076652947313735594503467579323097557938317788702,"line":81,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_lpg/latest/run.log","log_context":["UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_lpg","qual_name":"39.alert_handler_lpg.4865314567646673855287724741094929421413495166979763291027965818495041130857","seed":4865314567646673855287724741094929421413495166979763291027965818495041130857,"line":81,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/39.alert_handler_lpg/latest/run.log","log_context":["UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalEscIntFail)":[{"name":"alert_handler_stress_all","qual_name":"16.alert_handler_stress_all.63552526781315993707003493360791571022630264679091538916703328005546673089440","seed":63552526781315993707003493360791571022630264679091538916703328005546673089440,"line":339,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_stress_all/latest/run.log","log_context":["UVM_ERROR @ 239647849294 ps: (alert_handler_scoreboard.sv:258) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[0]: saw 0, but expected 1. (is_int_err = 1, local_alert_type = LocalEscIntFail)\n","UVM_INFO @ 239647849294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":793,"total":850,"percent":93.29411764705883}