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'0)'":[{"name":"chip_tl_errors","qual_name":"0.chip_tl_errors.38417122649157458506842390838546812241166890555115491772995336355202290385995","seed":38417122649157458506842390838546812241166890555115491772995336355202290385995,"line":232,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log","log_context":["\tOffending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'\n","UVM_ERROR @ 118.000000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 118.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"1.chip_tl_errors.28277905682818242673422431036216901440275339281869718257370163786654350313946","seed":28277905682818242673422431036216901440275339281869718257370163786654350313946,"line":232,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_tl_errors/latest/run.log","log_context":["\tOffending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'\n","UVM_ERROR @ 117.741000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 117.741000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"2.chip_tl_errors.46072481700372351675865824887173292616180784685793769736238759961004020550160","seed":46072481700372351675865824887173292616180784685793769736238759961004020550160,"line":232,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_tl_errors/latest/run.log","log_context":["\tOffending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'\n","UVM_ERROR @ 118.004000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 118.004000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"5.chip_tl_errors.96388641138825124673952132519519833891167287346624825800776019172821783518255","seed":96388641138825124673952132519519833891167287346624825800776019172821783518255,"line":232,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_tl_errors/latest/run.log","log_context":["\tOffending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'\n","UVM_ERROR @ 118.044000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 118.044000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"6.chip_tl_errors.37937302032701899170603555978903226226700215329204634440278919589885261004578","seed":37937302032701899170603555978903226226700215329204634440278919589885261004578,"line":232,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_tl_errors/latest/run.log","log_context":["\tOffending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'\n","UVM_ERROR @ 118.060000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 118.060000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"10.chip_tl_errors.39827207319737487184534318769315434725930718872138287767452164497545187800078","seed":39827207319737487184534318769315434725930718872138287767452164497545187800078,"line":232,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_tl_errors/latest/run.log","log_context":["\tOffending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'\n","UVM_ERROR @ 118.010000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 118.010000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"13.chip_tl_errors.91141931019795238444210794424786375169703658504480129024682347189530275666761","seed":91141931019795238444210794424786375169703658504480129024682347189530275666761,"line":232,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_tl_errors/latest/run.log","log_context":["\tOffending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'\n","UVM_ERROR @ 117.915000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 117.915000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"14.chip_tl_errors.21678278747157697395740072013067030208232796901154939637335998331726115076110","seed":21678278747157697395740072013067030208232796901154939637335998331726115076110,"line":232,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_tl_errors/latest/run.log","log_context":["\tOffending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'\n","UVM_ERROR @ 117.953000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 117.953000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"15.chip_tl_errors.29114308702302559405674207632631478755927320376220364518506204148081692826564","seed":29114308702302559405674207632631478755927320376220364518506204148081692826564,"line":232,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_tl_errors/latest/run.log","log_context":["\tOffending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'\n","UVM_ERROR @ 117.752000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 117.752000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"16.chip_tl_errors.109239929591087454232703829580998690270035513550627010405553262139150055868409","seed":109239929591087454232703829580998690270035513550627010405553262139150055868409,"line":232,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_tl_errors/latest/run.log","log_context":["\tOffending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'\n","UVM_ERROR @ 117.984000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 117.984000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"18.chip_tl_errors.29560183256421465120700038030226024869344072076087497625395626376590392607842","seed":29560183256421465120700038030226024869344072076087497625395626376590392607842,"line":232,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.chip_tl_errors/latest/run.log","log_context":["\tOffending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'\n","UVM_ERROR @ 117.706000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 117.706000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"22.chip_tl_errors.71303023898801098994929767034377414966467651923212816921698630485686531308225","seed":71303023898801098994929767034377414966467651923212816921698630485686531308225,"line":232,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.chip_tl_errors/latest/run.log","log_context":["\tOffending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'\n","UVM_ERROR @ 117.711000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 117.711000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_tl_errors","qual_name":"24.chip_tl_errors.114834413516674623879829976715390990910545317775227375793288676988278930199601","seed":114834413516674623879829976715390990910545317775227375793288676988278930199601,"line":232,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.chip_tl_errors/latest/run.log","log_context":["\tOffending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'\n","UVM_ERROR @ 117.709000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 117.709000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch":[{"name":"chip_rv_dm_lc_disabled","qual_name":"0.chip_rv_dm_lc_disabled.107843174572485832423768302019529177040201116759784518451449025578568063565156","seed":107843174572485832423768302019529177040201116759784518451449025578568063565156,"line":205,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_ERROR @ 130.829000 us: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x40624 read out mismatch\n","UVM_INFO @ 130.829000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_rv_dm_lc_disabled","qual_name":"1.chip_rv_dm_lc_disabled.4075927976534349841033478078217208809184071132179283621095311420124825863969","seed":4075927976534349841033478078217208809184071132179283621095311420124825863969,"line":213,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_ERROR @ 255.172000 us: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x4066c read out mismatch\n","UVM_INFO @ 255.172000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_soc_dbg_reg_block, item had unexpected d_error value(predicted *, but saw *).":[{"name":"chip_tl_errors","qual_name":"3.chip_tl_errors.91048316779866609340654547152217735671100733446081219269995306318941447965726","seed":91048316779866609340654547152217735671100733446081219269995306318941447965726,"line":231,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 118.009000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_soc_dbg_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@31717) { a_addr: 'h2210  a_data: 'hbe1162e5  a_mask: 'h3  a_size: 'h2  a_param: 'h0  a_source: 'hbe  a_opcode: 'h1  a_user: 'h24e79  d_param: 'h0  d_source: 'hbe  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 118.009000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"12.chip_tl_errors.42627711612070751722082491250854031788417005199712104122409748624934131182823","seed":42627711612070751722082491250854031788417005199712104122409748624934131182823,"line":231,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 118.236000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_soc_dbg_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@33261) { a_addr: 'h2214  a_data: 'h1d9dbfb2  a_mask: 'h4  a_size: 'h2  a_param: 'h0  a_source: 'he2  a_opcode: 'h1  a_user: 'h24d2f  d_param: 'h0  d_source: 'he2  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 118.236000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"26.chip_tl_errors.16912895542535483592042580674228876817115879428188800122274919304008822921871","seed":16912895542535483592042580674228876817115879428188800122274919304008822921871,"line":231,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 117.966000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_soc_dbg_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@31517) { a_addr: 'h2214  a_data: 'ha6cef5a9  a_mask: 'ha  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h1  a_user: 'h250dc  d_param: 'h0  d_source: 'h2  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 117.966000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"28.chip_tl_errors.69384729451032563705386622054953212125928171455302415985304757358561284234529","seed":69384729451032563705386622054953212125928171455302415985304757358561284234529,"line":231,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 118.003000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_soc_dbg_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@31655) { a_addr: 'h2210  a_data: 'hd302d4a4  a_mask: 'h8  a_size: 'h2  a_param: 'h0  a_source: 'hd8  a_opcode: 'h1  a_user: 'h259df  d_param: 'h0  d_source: 'hd8  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 118.003000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_soc_mbx_reg_block, item had unexpected d_error value(predicted *, but saw *).":[{"name":"chip_tl_errors","qual_name":"4.chip_tl_errors.55879765620563266313169341156915337363893710278024987988147232442744292289478","seed":55879765620563266313169341156915337363893710278024987988147232442744292289478,"line":231,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 117.734000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_soc_mbx_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@32259) { a_addr: 'h1465410  a_data: 'h9593ecd7  a_mask: 'ha  a_size: 'h2  a_param: 'h0  a_source: 'h6e  a_opcode: 'h1  a_user: 'h27014  d_param: 'h0  d_source: 'h6e  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 117.734000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"7.chip_tl_errors.27169911252127305517423742203292272431820899165707464991316810707897729368424","seed":27169911252127305517423742203292272431820899165707464991316810707897729368424,"line":231,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 118.055000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_soc_mbx_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@31933) { a_addr: 'h1465214  a_data: 'h7ff16885  a_mask: 'h2  a_size: 'h2  a_param: 'h0  a_source: 'he3  a_opcode: 'h1  a_user: 'h27557  d_param: 'h0  d_source: 'he3  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 118.055000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"8.chip_tl_errors.86445207231307024298072667473983759683378685408973085631759891165554047752544","seed":86445207231307024298072667473983759683378685408973085631759891165554047752544,"line":231,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 117.736000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_soc_mbx_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@32175) { a_addr: 'h1460114  a_data: 'h45cdb2e8  a_mask: 'h1  a_size: 'h0  a_param: 'h0  a_source: 'hde  a_opcode: 'h1  a_user: 'h25776  d_param: 'h0  d_source: 'hde  d_data: 'h0  d_size: 'h0  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h152a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 117.736000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"9.chip_tl_errors.98244996630842489347794069079716142105315122458195875509959718260458953599185","seed":98244996630842489347794069079716142105315122458195875509959718260458953599185,"line":231,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 117.705000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_soc_mbx_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@32203) { a_addr: 'h1460114  a_data: 'hc31c3bdd  a_mask: 'h5  a_size: 'h2  a_param: 'h0  a_source: 'hf6  a_opcode: 'h1  a_user: 'h25eb4  d_param: 'h0  d_source: 'hf6  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 117.705000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"11.chip_tl_errors.94712788154650579068440502222316113620760312618501663547958384613800362371838","seed":94712788154650579068440502222316113620760312618501663547958384613800362371838,"line":231,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 117.986000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_soc_mbx_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@31651) { a_addr: 'h1496014  a_data: 'h23e78259  a_mask: 'h9  a_size: 'h2  a_param: 'h0  a_source: 'h21  a_opcode: 'h1  a_user: 'h271e0  d_param: 'h0  d_source: 'h21  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 117.986000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"17.chip_tl_errors.31825801403965924613320570463833839002306277544200288227405277076726570436854","seed":31825801403965924613320570463833839002306277544200288227405277076726570436854,"line":231,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 117.721000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_soc_mbx_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@31823) { a_addr: 'h1465310  a_data: 'hca2e1b7b  a_mask: 'h2  a_size: 'h1  a_param: 'h0  a_source: 'hfe  a_opcode: 'h1  a_user: 'h27ee4  d_param: 'h0  d_source: 'hfe  d_data: 'h0  d_size: 'h1  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h10aa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 117.721000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"19.chip_tl_errors.112020176327475144854181563272090533836888304976697859251114227232877225186097","seed":112020176327475144854181563272090533836888304976697859251114227232877225186097,"line":231,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 118.290000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_soc_mbx_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@33779) { a_addr: 'h1465110  a_data: 'ha30bd779  a_mask: 'h3  a_size: 'h1  a_param: 'h0  a_source: 'he9  a_opcode: 'h1  a_user: 'h2765d  d_param: 'h0  d_source: 'he9  d_data: 'h0  d_size: 'h1  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h10aa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 118.290000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"21.chip_tl_errors.78400271720590964463523074095516302008937551015995148658309876129720359564392","seed":78400271720590964463523074095516302008937551015995148658309876129720359564392,"line":231,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 118.081000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_soc_mbx_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@31805) { a_addr: 'h1465414  a_data: 'hbdfd3b7a  a_mask: 'h2  a_size: 'h2  a_param: 'h0  a_source: 'had  a_opcode: 'h1  a_user: 'h26d36  d_param: 'h0  d_source: 'had  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 118.081000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"23.chip_tl_errors.85275167225713979988011013634434832076245026260524513735519727338928864248067","seed":85275167225713979988011013634434832076245026260524513735519727338928864248067,"line":231,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 118.026000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_soc_mbx_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@31865) { a_addr: 'h1460210  a_data: 'h6a7c2b6f  a_mask: 'ha  a_size: 'h2  a_param: 'h0  a_source: 'hd1  a_opcode: 'h1  a_user: 'h24039  d_param: 'h0  d_source: 'hd1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 118.026000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"25.chip_tl_errors.26801014702076387238012633142321456398039102974109455123440291911155025042828","seed":26801014702076387238012633142321456398039102974109455123440291911155025042828,"line":231,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 117.723000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_soc_mbx_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@31795) { a_addr: 'h1465310  a_data: 'hf4aea1f4  a_mask: 'hd  a_size: 'h2  a_param: 'h0  a_source: 'h3  a_opcode: 'h1  a_user: 'h260e1  d_param: 'h0  d_source: 'h3  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 117.723000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"27.chip_tl_errors.103126654917279599695982693458476390523651279735326242024778934591445508302841","seed":103126654917279599695982693458476390523651279735326242024778934591445508302841,"line":231,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 118.029000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_soc_mbx_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@31791) { a_addr: 'h1465210  a_data: 'h71bc5cca  a_mask: 'ha  a_size: 'h2  a_param: 'h0  a_source: 'h35  a_opcode: 'h1  a_user: 'h26871  d_param: 'h0  d_source: 'h35  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 118.029000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"29.chip_tl_errors.21740895957442650222307141826930405112062991226293160472582124234094888277706","seed":21740895957442650222307141826930405112062991226293160472582124234094888277706,"line":231,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 117.736000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_soc_mbx_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@31843) { a_addr: 'h1465110  a_data: 'h98f2fd0a  a_mask: 'h4  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h1  a_user: 'h279bf  d_param: 'h0  d_source: 'h2  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"} .\n","UVM_INFO @ 117.736000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).":[{"name":"chip_tl_errors","qual_name":"20.chip_tl_errors.42312547069177618894936691826814454466920887626452170991040555679134771657857","seed":42312547069177618894936691826814454466920887626452170991040555679134771657857,"line":231,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 117.690000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@31497) { a_addr: 'h407ec  a_data: 'h94fd01cd  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd  a_opcode: 'h4  a_user: 'h1a66b  d_param: 'h0  d_source: 'hd  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 117.690000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_jtag_csr_rw","qual_name":"0.chip_jtag_csr_rw.93392571212889816684763786832421724914518374118999026142918481747161619080382","seed":93392571212889816684763786832421724914518374118999026142918481747161619080382,"line":5952,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log","log_context":["UVM_ERROR @ 117.022000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@41718) { a_addr: 'h30480000  a_data: 'h63a4a42e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h19  a_opcode: 'h0  a_user: 'h26958  d_param: 'h0  d_source: 'h19  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unmapped address\"} .\n","UVM_INFO @ 117.022000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_jtag_mem_access","qual_name":"0.chip_jtag_mem_access.48880097505177976220480391598284412958293895830488338148591209311569773002542","seed":48880097505177976220480391598284412958293895830488338148591209311569773002542,"line":5952,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log","log_context":["UVM_ERROR @ 117.043000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@41718) { a_addr: 'h30480000  a_data: 'h85d0a34  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h37  a_opcode: 'h1  a_user: 'h248ba  d_param: 'h0  d_source: 'h37  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unmapped address\"} .\n","UVM_INFO @ 117.043000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_jtag_csr_rw","qual_name":"1.chip_jtag_csr_rw.53096035106640852748999131126017932426288066578088484267779344406512222905044","seed":53096035106640852748999131126017932426288066578088484267779344406512222905044,"line":5952,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log","log_context":["UVM_ERROR @ 117.026000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@41718) { a_addr: 'h30480000  a_data: 'h376359e2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd  a_opcode: 'h1  a_user: 'h248ea  d_param: 'h0  d_source: 'hd  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unmapped address\"} .\n","UVM_INFO @ 117.026000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_jtag_mem_access","qual_name":"1.chip_jtag_mem_access.65343315881160243404066335677011133355950685337135784033619412564462857903844","seed":65343315881160243404066335677011133355950685337135784033619412564462857903844,"line":5952,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log","log_context":["UVM_ERROR @ 117.036000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@41718) { a_addr: 'h30480000  a_data: 'h8941be85  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h9  a_opcode: 'h0  a_user: 'h26975  d_param: 'h0  d_source: 'h9  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unmapped address\"} .\n","UVM_INFO @ 117.036000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_jtag_csr_rw","qual_name":"2.chip_jtag_csr_rw.16526374116196600552815552463527405097167173902609944349378839266154938563614","seed":16526374116196600552815552463527405097167173902609944349378839266154938563614,"line":5952,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_jtag_csr_rw/latest/run.log","log_context":["UVM_ERROR @ 117.033000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@41718) { a_addr: 'h30480000  a_data: 'h49437eaf  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf  a_opcode: 'h0  a_user: 'h26920  d_param: 'h0  d_source: 'hf  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unmapped address\"} .\n","UVM_INFO @ 117.033000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_jtag_mem_access","qual_name":"2.chip_jtag_mem_access.102339081407987725165923605796667676293810334136006362327435606381060683206192","seed":102339081407987725165923605796667676293810334136006362327435606381060683206192,"line":5952,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_jtag_mem_access/latest/run.log","log_context":["UVM_ERROR @ 117.015000 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@41718) { a_addr: 'h30480000  a_data: 'hec8f7326  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h15  a_opcode: 'h1  a_user: 'h248f5  d_param: 'h0  d_source: 'h15  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unmapped address\"} .\n","UVM_INFO @ 117.015000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode":[{"name":"chip_csr_bit_bash","qual_name":"0.chip_csr_bit_bash.85676056894625251659872642422744538688631875654566333938987816319898805408852","seed":85676056894625251659872642422744538688631875654566333938987816319898805408852,"line":136,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log","log_context":["UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode\n","UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_csr_aliasing","qual_name":"0.chip_csr_aliasing.14336349222603630048431509084995563986088685438537818945591875671961834117180","seed":14336349222603630048431509084995563986088685438537818945591875671961834117180,"line":136,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log","log_context":["UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode\n","UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_same_csr_outstanding","qual_name":"0.chip_same_csr_outstanding.68751649041566059568198209223079244503506397395736521352655862680684584134665","seed":68751649041566059568198209223079244503506397395736521352655862680684584134665,"line":136,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log","log_context":["UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode\n","UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_csr_bit_bash","qual_name":"1.chip_csr_bit_bash.100284630763892143168594289887825582559005939516019027402847932733018527583255","seed":100284630763892143168594289887825582559005939516019027402847932733018527583255,"line":136,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log","log_context":["UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode\n","UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_csr_aliasing","qual_name":"1.chip_csr_aliasing.99567295033426313343674335072859344746392126915156667131704160763304796681859","seed":99567295033426313343674335072859344746392126915156667131704160763304796681859,"line":136,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log","log_context":["UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode\n","UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_same_csr_outstanding","qual_name":"1.chip_same_csr_outstanding.63224683354649728143069415214418622094940171490984978452203258840218717693490","seed":63224683354649728143069415214418622094940171490984978452203258840218717693490,"line":136,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log","log_context":["UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode\n","UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_csr_bit_bash","qual_name":"2.chip_csr_bit_bash.48106245122953960432045938442763933521010578805559475693817193560696628989212","seed":48106245122953960432045938442763933521010578805559475693817193560696628989212,"line":136,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_csr_bit_bash/latest/run.log","log_context":["UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode\n","UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_csr_aliasing","qual_name":"2.chip_csr_aliasing.72513627805424763302770408739709840318532007393303862904386246818722405056823","seed":72513627805424763302770408739709840318532007393303862904386246818722405056823,"line":136,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log","log_context":["UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode\n","UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_same_csr_outstanding","qual_name":"2.chip_same_csr_outstanding.24072581093145339911594761277595826133830568795477270779015672845558943392346","seed":24072581093145339911594761277595826133830568795477270779015672845558943392346,"line":136,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_same_csr_outstanding/latest/run.log","log_context":["UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode\n","UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode":[{"name":"chip_sw_example_rom","qual_name":"0.chip_sw_example_rom.61038911101376259481013358873937083926091651228729161329390162157266157963271","seed":61038911101376259481013358873937083926091651228729161329390162157266157963271,"line":284,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log","log_context":["UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_example_rom","qual_name":"1.chip_sw_example_rom.21349854083579362209443719924637327508785439611738281451758789810803339562026","seed":21349854083579362209443719924637327508785439611738281451758789810803339562026,"line":284,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log","log_context":["UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_example_rom","qual_name":"2.chip_sw_example_rom.34736140378354850577298964227862356488210809328778195903849639262007837990723","seed":34736140378354850577298964227862356488210809328778195903849639262007837990723,"line":284,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_rom/latest/run.log","log_context":["UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job returned non-zero exit code":[{"name":"chip_sw_example_manufacturer","qual_name":"0.chip_sw_example_manufacturer.79371607005220254846628873818283163066031070326047972450031788043084766337561","seed":79371607005220254846628873818283163066031070326047972450031788043084766337561,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.655s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_data_integrity_escalation","qual_name":"0.chip_sw_data_integrity_escalation.48688233862135330602977945611719168889378688078305129810618598196568795918719","seed":48688233862135330602977945611719168889378688078305129810618598196568795918719,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 5.221s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sleep_pin_wake","qual_name":"0.chip_sw_sleep_pin_wake.81120868265595925341965392220212709278824428229401060779453727709408722660380","seed":81120868265595925341965392220212709278824428229401060779453727709408722660380,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 23.839s, Critical Path: 0.09s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sleep_pin_retention","qual_name":"0.chip_sw_sleep_pin_retention.78681472076822131776854832858321633868269400519457026422442854235097780283849","seed":78681472076822131776854832858321633868269400519457026422442854235097780283849,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.509s, Critical Path: 0.08s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx","qual_name":"0.chip_sw_uart_tx_rx.76106322246310324014741675329129506250659727116196584897373155615207769729562","seed":76106322246310324014741675329129506250659727116196584897373155615207769729562,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 4.241s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx_bootstrap","qual_name":"0.chip_sw_uart_tx_rx_bootstrap.44796024190996362301706073972597612847197123706252981111181892651630626537792","seed":44796024190996362301706073972597612847197123706252981111181892651630626537792,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 5.276s, Critical Path: 0.00s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_inject_scramble_seed","qual_name":"0.chip_sw_inject_scramble_seed.94986362048215767204890004753995733638093947742637092803000469229922394452903","seed":94986362048215767204890004753995733638093947742637092803000469229922394452903,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_inject_scramble_seed/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 4.274s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_exit_test_unlocked_bootstrap","qual_name":"0.chip_sw_exit_test_unlocked_bootstrap.17176775841161200144856823190485060919921014376392782803288271054593435367805","seed":17176775841161200144856823190485060919921014376392782803288271054593435367805,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 55.747s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"0.chip_sw_uart_rand_baudrate.68478664354751375406877828373585187044155332390823623796885236284896232693930","seed":68478664354751375406877828373585187044155332390823623796885236284896232693930,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 9.198s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx_alt_clk_freq","qual_name":"0.chip_sw_uart_tx_rx_alt_clk_freq.115727835683757205732407120176221816865174392694860458761809557094775217926296","seed":115727835683757205732407120176221816865174392694860458761809557094775217926296,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 9.334s, Critical Path: 0.10s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_i2c_host_tx_rx","qual_name":"0.chip_sw_i2c_host_tx_rx.98748486644613534377095656559028837502509030660164652046188479725426874450809","seed":98748486644613534377095656559028837502509030660164652046188479725426874450809,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 33.765s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_i2c_device_tx_rx","qual_name":"0.chip_sw_i2c_device_tx_rx.55415700188768327774413574129918886082071613897014201722962774685786534395368","seed":55415700188768327774413574129918886082071613897014201722962774685786534395368,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_i2c_device_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.216s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_spi_device_tpm","qual_name":"0.chip_sw_spi_device_tpm.11477348426149479797577388179289835286343782224732939919260142067317437985554","seed":11477348426149479797577388179289835286343782224732939919260142067317437985554,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_tpm/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.058s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_spi_host_tx_rx","qual_name":"0.chip_sw_spi_host_tx_rx.65459355069350474737932355364760801404161755867430124397553289529306393672345","seed":65459355069350474737932355364760801404161755867430124397553289529306393672345,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_host_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.523s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_otp_hw_cfg","qual_name":"0.chip_sw_lc_ctrl_otp_hw_cfg.81066446986856057535384516940831278461334370251572676465519232798638451705544","seed":81066446986856057535384516940831278461334370251572676465519232798638451705544,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_otp_hw_cfg/latest/run.log","log_context":["Another command (pid=3198539) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=3204540) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=3174793) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)\n","ERROR: no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_test_unlocked0","qual_name":"0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.83456796720486327215339943050271415816488592686824155201070065675389651711036","seed":83456796720486327215339943050271415816488592686824155201070065675389651711036,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 14.360s, Critical Path: 0.10s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_dev","qual_name":"0.chip_sw_otp_ctrl_lc_signals_dev.9585741526870964457222870919472314031180652618502502236910583535306113509897","seed":9585741526870964457222870919472314031180652618502502236910583535306113509897,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_dev/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 38.283s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_prod","qual_name":"0.chip_sw_otp_ctrl_lc_signals_prod.76980400054840010207162919510103200138210479282051461224510981627422296272557","seed":76980400054840010207162919510103200138210479282051461224510981627422296272557,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_prod/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.598s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"0.chip_sw_otp_ctrl_lc_signals_rma.53213957347118321939043317598489908828870586345242062759643900802581172954497","seed":53213957347118321939043317598489908828870586345242062759643900802581172954497,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.200s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_vendor_test_csr_access","qual_name":"0.chip_sw_otp_ctrl_vendor_test_csr_access.46470462761102846401852850454616325401501413558981323018988646307220321363992","seed":46470462761102846401852850454616325401501413558981323018988646307220321363992,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.743s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_nvm_cnt","qual_name":"0.chip_sw_otp_ctrl_nvm_cnt.1620533380284054110064953573933300419114185049005047023149195247229185136117","seed":1620533380284054110064953573933300419114185049005047023149195247229185136117,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_nvm_cnt/latest/run.log","log_context":["Another command (pid=3175141) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=3191057) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=3185910) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_sw_parts","qual_name":"0.chip_sw_otp_ctrl_sw_parts.65709749231816113987618766804839998976286739660150099919533678548433361094597","seed":65709749231816113987618766804839998976286739660150099919533678548433361094597,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_sw_parts/latest/run.log","log_context":["Another command (pid=3201925) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=3174727) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=3176607) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"0.chip_sw_lc_ctrl_transition.114740118003643426908365571613588653611765577516033799023939839548421656935953","seed":114740118003643426908365571613588653611765577516033799023939839548421656935953,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.630s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"0.chip_sw_lc_walkthrough_dev.11884825834327339819677100558927495273998638604672664956940236779441175579931","seed":11884825834327339819677100558927495273998638604672664956940236779441175579931,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 9.242s, Critical Path: 0.09s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"0.chip_sw_lc_walkthrough_prod.102269003364782085839081310660997636709334568615576653799192059481987304374079","seed":102269003364782085839081310660997636709334568615576653799192059481987304374079,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 39.261s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_prodend","qual_name":"0.chip_sw_lc_walkthrough_prodend.79751346970357878192730162937423267807025583290659580507008462784015509745733","seed":79751346970357878192730162937423267807025583290659580507008462784015509745733,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_prodend/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.797s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"0.chip_sw_lc_walkthrough_rma.5191235481196818654305248935498675025503111485856166764191291726784719143218","seed":5191235481196818654305248935498675025503111485856166764191291726784719143218,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 13.340s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_testunlocks","qual_name":"0.chip_sw_lc_walkthrough_testunlocks.103477485399302837100020088244990560649697661325355525411544216945907914714699","seed":103477485399302837100020088244990560649697661325355525411544216945907914714699,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.743s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_main_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_main_power_glitch_reset.33209184058988215764097136546147328172151985822643468414647152646831219043424","seed":33209184058988215764097136546147328172151985822643468414647152646831219043424,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_main_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.606s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_sleep_power_glitch_reset.22150755400849839052621843367057004806771570417506173188903976395925849424791","seed":22150755400849839052621843367057004806771570417506173188903976395925849424791,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 6.379s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.49532658456600924505333510323565853120756097816901071464034119462423749631426","seed":49532658456600924505333510323565853120756097816901071464034119462423749631426,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 12.781s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.42864654962078601012789925833254296373592844259034390648427439840037584296746","seed":42864654962078601012789925833254296373592844259034390648427439840037584296746,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 6.246s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_disabled","qual_name":"0.chip_sw_pwrmgr_sleep_disabled.85624111875617307940855726497250279669137313192223290426155985278557417243235","seed":85624111875617307940855726497250279669137313192223290426155985278557417243235,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_disabled/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.745s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_wdog_reset","qual_name":"0.chip_sw_pwrmgr_wdog_reset.44653256948267676536248714342033813250323418597835811648102947053556541981332","seed":44653256948267676536248714342033813250323418597835811648102947053556541981332,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_wdog_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 27.742s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_test","qual_name":"0.chip_sw_alert_test.89834960314461941899812332867497706004152816561515762457325740856706862475781","seed":89834960314461941899812332867497706004152816561515762457325740856706862475781,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log","log_context":["---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests/autogen/top_darjeeling:alert_test_sim_dv': no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - sw/device/tests/autogen/top_darjeeling\n","ERROR: no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - sw/device/tests/autogen/top_darjeeling\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_escalation","qual_name":"0.chip_sw_alert_handler_escalation.86270300108229363475173897193478774968027635013061919647487179013856193465173","seed":86270300108229363475173897193478774968027635013061919647487179013856193465173,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_escalation/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_escalation_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.426s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_reverse_ping_in_deep_sleep","qual_name":"0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.45447140243991343653129621678150558453983530269750976589668870649951956080318","seed":45447140243991343653129621678150558453983530269750976589668870649951956080318,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.030s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_alerts.23336601491844204983898437457946166647960067702339211811959791221488149480686","seed":23336601491844204983898437457946166647960067702339211811959791221488149480686,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_pings.57541894977983592351391722022568977168994928402952428208556502988886121608546","seed":57541894977983592351391722022568977168994928402952428208556502988886121608546,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.344s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_clkoff","qual_name":"0.chip_sw_alert_handler_lpg_clkoff.100255331825636293707814791767821857158512594157490423313476833848645106579599","seed":100255331825636293707814791767821857158512594157490423313476833848645106579599,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_lpg_clkoff/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.327s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_reset_toggle","qual_name":"0.chip_sw_alert_handler_lpg_reset_toggle.113407485847956778935961167189677264410573915428786133247937523584983053782593","seed":113407485847956778935961167189677264410573915428786133247937523584983053782593,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_lpg_reset_toggle/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.324s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_entropy","qual_name":"0.chip_sw_alert_handler_entropy.54948626002506037322617128417252761038680526203158552565229976754995181539181","seed":54948626002506037322617128417252761038680526203158552565229976754995181539181,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_entropy/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.666s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_csrng_fuse_en_sw_app_read_test","qual_name":"0.chip_sw_csrng_fuse_en_sw_app_read_test.46630749460862980120306945080873415418471962697445196889670591578004393585252","seed":46630749460862980120306945080873415418471962697445196889670591578004393585252,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 5.289s, Critical Path: 0.09s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_kmac_app_rom","qual_name":"0.chip_sw_kmac_app_rom.38976342737250536748275180773336578595226469339693308275462478327417857696531","seed":38976342737250536748275180773336578595226469339693308275462478327417857696531,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3497600) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Build option --define has changed, discarding analysis cache (this can be expensive, see https://bazel.build/advanced/performance/iteration-speed).\n","DEBUG: /nightly/current_run/opentitan/rules/autogen.bzl:536:14: NOTE: stamping is disabled, the build_info section will use a fixed version string\n","ERROR: Error doing post analysis query: Evaluation of subquery \"labels('data', //sw/device/tests:kmac_app_rom_test_sim_dv)\" failed (did you want to use --keep_going?): in 'data' of rule //sw/device/tests:kmac_app_rom_test_sim_dv: configured target of type test_suite does not have attribute 'data'\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access_jitter_en","qual_name":"0.chip_sw_sram_ctrl_scrambled_access_jitter_en.23132484987981114386899495547860451413637827906893876033827733201284470424790","seed":23132484987981114386899495547860451413637827906893876033827733201284470424790,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=3505619) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=3504697) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD\n","ERROR: no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sram_ctrl_execution_main","qual_name":"0.chip_sw_sram_ctrl_execution_main.72478195276287859007882429273776046129936078053191538417648325892002505707582","seed":72478195276287859007882429273776046129936078053191538417648325892002505707582,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 5.279s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_coremark","qual_name":"0.chip_sw_coremark.101365775545516258772230477646299450943931090845559327731129331412926569389933","seed":101365775545516258772230477646299450943931090845559327731129331412926569389933,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_coremark/latest/run.log","log_context":["Another command (pid=3513846) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//third_party/coremark/top_darjeeling:coremark_test_sim_dv': no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - third_party/coremark/top_darjeeling\n","ERROR: no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - third_party/coremark/top_darjeeling\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_clkmgr_reset_frequency","qual_name":"0.chip_sw_clkmgr_reset_frequency.82133567940484219352093811024960366939410726674871533252752459263739136954175","seed":82133567940484219352093811024960366939410726674871533252752459263739136954175,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_reset_frequency/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:clkmgr_reset_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_reset_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:clkmgr_reset_frequency_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 4.919s, Critical Path: 0.10s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_clkmgr_sleep_frequency","qual_name":"0.chip_sw_clkmgr_sleep_frequency.52353829358840509807823222114262441035660439716655727483143267668449762904739","seed":52353829358840509807823222114262441035660439716655727483143267668449762904739,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_sleep_frequency/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.628s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_ast_clk_outputs","qual_name":"0.chip_sw_ast_clk_outputs.65455552887115934643198093058441842361079030603172037872315130539278790718584","seed":65455552887115934643198093058441842361079030603172037872315130539278790718584,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_ast_clk_outputs/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:ast_clk_outs_test_sim_dv' failed; build aborted: Target //sw/device/tests:ast_clk_outs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:ast_clk_outs_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.314s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_program_error","qual_name":"0.chip_sw_lc_ctrl_program_error.90080731319794218240069500446810260697691175514403310050342317710611389353003","seed":90080731319794218240069500446810260697691175514403310050342317710611389353003,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.069s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.95118924786557049864610768949025975478898104572191254708179744897247997964920","seed":95118924786557049864610768949025975478898104572191254708179744897247997964920,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)\n","ERROR: no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"0.chip_sw_rv_dm_access_after_wakeup.56579929597954458145175796374638759164815932501003795084677477435149519113052","seed":56579929597954458145175796374638759164815932501003795084677477435149519113052,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)\n","ERROR: no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_access_after_escalation_reset","qual_name":"0.chip_sw_rv_dm_access_after_escalation_reset.54269205867261245112702772145416698028322428985320662093750055332667480388300","seed":54269205867261245112702772145416698028322428985320662093750055332667480388300,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_escalation_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.361s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_power_virus","qual_name":"0.chip_sw_power_virus.17413109784665599412151345697173407201008278867790584934556382451731157207367","seed":17413109784665599412151345697173407201008278867790584934556382451731157207367,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:power_virus_systemtest_sim_dv' failed; build aborted: Target //sw/device/tests:power_virus_systemtest_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:power_virus_systemtest_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.432s, Critical Path: 0.07s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"base_rom_e2e_smoke","qual_name":"0.base_rom_e2e_smoke.68522363264576070123757598310634055171906418051784638017491321761500405818166","seed":68522363264576070123757598310634055171906418051784638017491321761500405818166,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.base_rom_e2e_smoke/latest/run.log","log_context":["    _deploy_software_collateral(args)\n","    ~~~~~~~~~~~~~~~~~~~~~~~~~~~^^^^^^\n","  File \"/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py\", line 324, in _deploy_software_collateral\n","    image_string = ImageString(image)\n","  File \"<string>\", line 4, in __init__\n","  File \"/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py\", line 256, in __post_init__\n","    assert flag in KNOWN_FLAGS, f\"Unknown flag '{flag}' used in sw_image '{self.raw}'\"\n","           ^^^^^^^^^^^^^^^^^^^\n","AssertionError: Unknown flag 'test_in_second_rom' used in sw_image '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom'\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_smoke","qual_name":"0.rom_e2e_smoke.103597414938673477018156151102632504057743126817926206743156629352029153991047","seed":103597414938673477018156151102632504057743126817926206743156629352029153991047,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_smoke/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3623081) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_shutdown_exception_c","qual_name":"0.rom_e2e_shutdown_exception_c.67317148358309131539797746701901186175549708996998405256439016705433033876943","seed":67317148358309131539797746701901186175549708996998405256439016705433033876943,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_shutdown_output","qual_name":"0.rom_e2e_shutdown_output.11111040554324727714512231187607615642597219124183893388670082693825626861554","seed":11111040554324727714512231187607615642597219124183893388670082693825626861554,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3630411) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.112472658058934595487512894101266458701604924461715007411972220150681286117163","seed":112472658058934595487512894101266458701604924461715007411972220150681286117163,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_dev.92009329842692330325446512997046987487594167933355837366935157178275369464746","seed":92009329842692330325446512997046987487594167933355837366935157178275369464746,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3631360) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_prod.29648943981106423316122477542225228287338570672152441334552341175939329292113","seed":29648943981106423316122477542225228287338570672152441334552341175939329292113,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.26177844002462642994299354332573425081219271814623593148425558712916841165816","seed":26177844002462642994299354332573425081219271814623593148425558712916841165816,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_rma.63564677544169626740525104720879947466253021379060087482288626148145585533042","seed":63564677544169626740525104720879947466253021379060087482288626148145585533042,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.35187135976580863868142681362244651136116452103137869744959685824276993091804","seed":35187135976580863868142681362244651136116452103137869744959685824276993091804,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.67875830637371563431770064967895455213394867942799066538615315894709307474520","seed":67875830637371563431770064967895455213394867942799066538615315894709307474520,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.92309234922695422366732214420124963544024780241056171018615569273716121909756","seed":92309234922695422366732214420124963544024780241056171018615569273716121909756,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.79015550716502107993113764400640284165623822434198690664268958260277054160236","seed":79015550716502107993113764400640284165623822434198690664268958260277054160236,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.52505814461715720186468337420049422692784280685000875433133816668221043847563","seed":52505814461715720186468337420049422692784280685000875433133816668221043847563,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.93075096327780150071213159393113959221795784336457480820839938987896319542978","seed":93075096327780150071213159393113959221795784336457480820839938987896319542978,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.40477498259706934839607139284678141802162817918304571307675186226991969764437","seed":40477498259706934839607139284678141802162817918304571307675186226991969764437,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.72906125775535756686430547526283919123800103120609610413904767091170260071599","seed":72906125775535756686430547526283919123800103120609610413904767091170260071599,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.7603671540301520052415443331309687836433620347245065081498584774204813673559","seed":7603671540301520052415443331309687836433620347245065081498584774204813673559,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.79279059691499585271434862235414952425803670334413411286341908785161061612714","seed":79279059691499585271434862235414952425803670334413411286341908785161061612714,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.102522799015946450647605563835268459299581317324457500372320682496435852911174","seed":102522799015946450647605563835268459299581317324457500372320682496435852911174,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_dev.103085474834532266705764694904793126477759286966132494439952531136163994790730","seed":103085474834532266705764694904793126477759286966132494439952531136163994790730,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3640700) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod.89288358095742577356175438784805554821631169284485549631127854030478121488031","seed":89288358095742577356175438784805554821631169284485549631127854030478121488031,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3638294) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.113204810007429740017015462760862017591426029748370173532848421857226957160894","seed":113204810007429740017015462760862017591426029748370173532848421857226957160894,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=3638826) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=3638567) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_rma.81077730221582455736468198683675959108096725189769807755586097647270263234142","seed":81077730221582455736468198683675959108096725189769807755586097647270263234142,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3639407) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.73663613296354733212846990171502764960491631741253510918793084218851713380609","seed":73663613296354733212846990171502764960491631741253510918793084218851713380609,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3638531) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.104888974860998190602233530821117161740167589593222119966665977676798992347605","seed":104888974860998190602233530821117161740167589593222119966665977676798992347605,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3640448) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.107069618305495640891862988242633779958418474861026355910390316697946451453662","seed":107069618305495640891862988242633779958418474861026355910390316697946451453662,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3642026) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.51404047708490929021392797723774021146394812271078746048721408723059512768103","seed":51404047708490929021392797723774021146394812271078746048721408723059512768103,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3642467) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.65703080046746747375134502154921263520234915177493463515061995306094978772742","seed":65703080046746747375134502154921263520234915177493463515061995306094978772742,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.113829743229109084297749142835785247198575148478968017477778243441106738173610","seed":113829743229109084297749142835785247198575148478968017477778243441106738173610,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3643958) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.90516078599642488926505439800419466710373490508618026312008781006783004456523","seed":90516078599642488926505439800419466710373490508618026312008781006783004456523,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3643865) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.64610175338398811731257253495526433805755108834312171195047141999956841659663","seed":64610175338398811731257253495526433805755108834312171195047141999956841659663,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.6256165533545234654371738573657945670426147664014273402961384668277999368962","seed":6256165533545234654371738573657945670426147664014273402961384668277999368962,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.84382335896874123054776651005927949796732114760499930856979832756730320885878","seed":84382335896874123054776651005927949796732114760499930856979832756730320885878,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3646151) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"0.rom_e2e_asm_init_test_unlocked0.108885031083843087658377068065789600638200049002618172468721626783049260077957","seed":108885031083843087658377068065789600638200049002618172468721626783049260077957,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3645895) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"0.rom_e2e_asm_init_dev.87107175991993129615258260741188325538482196653491729071274179643623339952110","seed":87107175991993129615258260741188325538482196653491729071274179643623339952110,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_asm_init_dev/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3647280) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"0.rom_e2e_asm_init_prod.37609058459583624888536539946393492712957597416220026833180852649276664043597","seed":37609058459583624888536539946393492712957597416220026833180852649276664043597,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"0.rom_e2e_asm_init_prod_end.45882036861427248484898152216770315027199399911736201446213567419731181593747","seed":45882036861427248484898152216770315027199399911736201446213567419731181593747,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"0.rom_e2e_asm_init_rma.55040858456163267623896846527954863650966274622755200613637660062572507844580","seed":55040858456163267623896846527954863650966274622755200613637660062572507844580,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_asm_init_rma/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3648667) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_debug_test_unlocked0","qual_name":"0.rom_e2e_jtag_debug_test_unlocked0.98415236195813092262822346615085474957870802914759502554788093473122335412779","seed":98415236195813092262822346615085474957870802914759502554788093473122335412779,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_debug_dev","qual_name":"0.rom_e2e_jtag_debug_dev.83357874872467634983596080258417307194205220062005415855032282602833973189104","seed":83357874872467634983596080258417307194205220062005415855032282602833973189104,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3648411) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_debug_rma","qual_name":"0.rom_e2e_jtag_debug_rma.103052193914455870368258181163080765604072784236221483803670931713432212343087","seed":103052193914455870368258181163080765604072784236221483803670931713432212343087,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_inject_test_unlocked0","qual_name":"0.rom_e2e_jtag_inject_test_unlocked0.13077686539452542396486710717046729346749516614598356096243073986854894974786","seed":13077686539452542396486710717046729346749516614598356096243073986854894974786,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_inject_dev","qual_name":"0.rom_e2e_jtag_inject_dev.44274173995815962319061002093772819196674794350103291591513906607253269319466","seed":44274173995815962319061002093772819196674794350103291591513906607253269319466,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_inject_rma","qual_name":"0.rom_e2e_jtag_inject_rma.89033321881949821079601057414064576281050011239439091941328276275467862460428","seed":89033321881949821079601057414064576281050011239439091941328276275467862460428,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_static_critical","qual_name":"0.rom_e2e_static_critical.28755240388057080065755490926594051477348285727292443080032095609314112687865","seed":28755240388057080065755490926594051477348285727292443080032095609314112687865,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_meas","qual_name":"0.rom_e2e_keymgr_init_rom_ext_meas.10018517631031797690157757845991040896362878922468678865199729784855503589664","seed":10018517631031797690157757845991040896362878922468678865199729784855503589664,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3648723) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_no_meas","qual_name":"0.rom_e2e_keymgr_init_rom_ext_no_meas.19176084724535311257961566854083828460851808309601519166810387667741401943625","seed":19176084724535311257961566854083828460851808309601519166810387667741401943625,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3650675) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_invalid_meas","qual_name":"0.rom_e2e_keymgr_init_rom_ext_invalid_meas.87752978797561709075261281006830025956999772008447438975522132769824793308071","seed":87752978797561709075261281006830025956999772008447438975522132769824793308071,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_test_unlocked0_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.55848102608725205292306181667946065110850512801909819428084743720024212990730","seed":55848102608725205292306181667946065110850512801909819428084743720024212990730,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_test_unlocked0_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_test_unlocked0_sw.22877964371882728678517395120435700255288650084360564949180833706203630286890","seed":22877964371882728678517395120435700255288650084360564949180833706203630286890,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_dev_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_dev_otbn.47311237238461956772643413532254133220153202025481435396537456075671443915468","seed":47311237238461956772643413532254133220153202025481435396537456075671443915468,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_dev_otbn/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3651259) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_dev_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_dev_sw.110754658850545461838338760880660423511329684868111689818320544600323505517317","seed":110754658850545461838338760880660423511329684868111689818320544600323505517317,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_dev_sw/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3651857) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_prod_otbn.92280792600909164834346694681845387299352509135471063890511670107872806559425","seed":92280792600909164834346694681845387299352509135471063890511670107872806559425,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_prod_sw.60494685724305221455786835881286422949995407252977971656160936940953322906702","seed":60494685724305221455786835881286422949995407252977971656160936940953322906702,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_end_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_prod_end_otbn.77014434265620857106552301554096191285127141632577769063378651003299699493168","seed":77014434265620857106552301554096191285127141632577769063378651003299699493168,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_end_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_end_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_prod_end_sw.10883239165801649937457501905597212766976128052207101762823330674205415701626","seed":10883239165801649937457501905597212766976128052207101762823330674205415701626,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_end_sw/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3651857) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_rma_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_rma_otbn.98201914896198162905343500493881386170354338751312617618658501711331336469995","seed":98201914896198162905343500493881386170354338751312617618658501711331336469995,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_rma_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_rma_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_rma_sw.14767129817384030826525544543135712374402148644779952909040555353588693535745","seed":14767129817384030826525544543135712374402148644779952909040555353588693535745,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_rma_sw/latest/run.log","log_context":["cwd=/nightly/current_run/opentitan\n","\n","Waiting for it to complete...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"0.rom_volatile_raw_unlock.114890291504353530231036043617011781860026077204387432062998349801131326079368","seed":114890291504353530231036043617011781860026077204387432062998349801131326079368,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_volatile_raw_unlock/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"0.rom_raw_unlock.112154694296955495990960950634085199552571698138364109946344097658892961583383","seed":112154694296955495990960950634085199552571698138364109946344097658892961583383,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_raw_unlock/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"0.rom_e2e_self_hash.4687165589398096937627012006134265379354015317576215284803297891735713150535","seed":4687165589398096937627012006134265379354015317576215284803297891735713150535,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_smoketest_signed","qual_name":"0.chip_sw_uart_smoketest_signed.86712462603546127513758841432265147351641926739112910797271681658789208456695","seed":86712462603546127513758841432265147351641926739112910797271681658789208456695,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_smoketest_signed/latest/run.log","log_context":["cwd=/nightly/current_run/opentitan\n","\n","Waiting for it to complete...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:uart_smoketest_signed_sim_dv': no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_keymgr_functest","qual_name":"0.rom_keymgr_functest.113193772287296113375080367775142723256698506141599258592613576626586633734639","seed":113193772287296113375080367775142723256698506141599258592613576626586633734639,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_keymgr_functest/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv' failed; build aborted: Target //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.381s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_example_manufacturer","qual_name":"1.chip_sw_example_manufacturer.42149108094568485020425939305836132488281445588545987722462804022822585765647","seed":42149108094568485020425939305836132488281445588545987722462804022822585765647,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log","log_context":["ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.171s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_data_integrity_escalation","qual_name":"1.chip_sw_data_integrity_escalation.20628927063175556907568651653391016488293849112200808748603617984245219986191","seed":20628927063175556907568651653391016488293849112200808748603617984245219986191,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.260s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sleep_pin_wake","qual_name":"1.chip_sw_sleep_pin_wake.975844493877531310798582302125532107248862640734265365081574969881903010699","seed":975844493877531310798582302125532107248862640734265365081574969881903010699,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 6.672s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sleep_pin_retention","qual_name":"1.chip_sw_sleep_pin_retention.71409115350814358377160244260333413239640850382655672500409822625840830020953","seed":71409115350814358377160244260333413239640850382655672500409822625840830020953,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 9.264s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx","qual_name":"1.chip_sw_uart_tx_rx.28986389992930023671025693286977387827397663185970045110666272702206586600047","seed":28986389992930023671025693286977387827397663185970045110666272702206586600047,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 12.415s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx_bootstrap","qual_name":"1.chip_sw_uart_tx_rx_bootstrap.60782410763712213373750588506224961798616915511786407527975916877197780935234","seed":60782410763712213373750588506224961798616915511786407527975916877197780935234,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 6.852s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_inject_scramble_seed","qual_name":"1.chip_sw_inject_scramble_seed.4370113825581571290447986766392434223768731264132750260695687065110499723006","seed":4370113825581571290447986766392434223768731264132750260695687065110499723006,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_inject_scramble_seed/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.156s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_exit_test_unlocked_bootstrap","qual_name":"1.chip_sw_exit_test_unlocked_bootstrap.76592251839364083736180124093297581625934630843072626836893692927764292353946","seed":76592251839364083736180124093297581625934630843072626836893692927764292353946,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_exit_test_unlocked_bootstrap/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.218s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"1.chip_sw_uart_rand_baudrate.96486596216353736596571705467917347553781867435619606445387821615207552099329","seed":96486596216353736596571705467917347553781867435619606445387821615207552099329,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 18.788s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx_alt_clk_freq","qual_name":"1.chip_sw_uart_tx_rx_alt_clk_freq.78334384835194792976453515619968182731193514699031573545171307670673622321807","seed":78334384835194792976453515619968182731193514699031573545171307670673622321807,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.589s, Critical Path: 0.00s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_i2c_host_tx_rx","qual_name":"1.chip_sw_i2c_host_tx_rx.17853301065002863192379291976954614040237172510604017663756057365138738186787","seed":17853301065002863192379291976954614040237172510604017663756057365138738186787,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_i2c_host_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.656s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_i2c_device_tx_rx","qual_name":"1.chip_sw_i2c_device_tx_rx.18136546321948815722120153690627396398776609799351898081114032121898721667531","seed":18136546321948815722120153690627396398776609799351898081114032121898721667531,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_i2c_device_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.202s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_spi_device_tpm","qual_name":"1.chip_sw_spi_device_tpm.67656061263522655189183219096490047583263791381532774095580439664810050146374","seed":67656061263522655189183219096490047583263791381532774095580439664810050146374,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_tpm/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.988s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_spi_host_tx_rx","qual_name":"1.chip_sw_spi_host_tx_rx.24078180345478175538863794475699143356345927426601146939881154964275195549604","seed":24078180345478175538863794475699143356345927426601146939881154964275195549604,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_host_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 5.159s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_otp_hw_cfg","qual_name":"1.chip_sw_lc_ctrl_otp_hw_cfg.24758966140543628272150897088569387117418141035299716327560134133245887367749","seed":24758966140543628272150897088569387117418141035299716327560134133245887367749,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_otp_hw_cfg/latest/run.log","log_context":["Another command (pid=3759541) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=3761885) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=3763125) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)\n","ERROR: no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_test_unlocked0","qual_name":"1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.109376149305433001923792581328577895380641474997702805100222802097515251215778","seed":109376149305433001923792581328577895380641474997702805100222802097515251215778,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 6.721s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_dev","qual_name":"1.chip_sw_otp_ctrl_lc_signals_dev.37624389770975257776556840137017212912241672193475912635568014005378243178052","seed":37624389770975257776556840137017212912241672193475912635568014005378243178052,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_dev/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 13.824s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_prod","qual_name":"1.chip_sw_otp_ctrl_lc_signals_prod.59028314108275129144753690764779383988936243390932113430583903650056736781635","seed":59028314108275129144753690764779383988936243390932113430583903650056736781635,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_prod/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 7.293s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"1.chip_sw_otp_ctrl_lc_signals_rma.73273314522341806193037139254959705454075778110118849298562194832632452981491","seed":73273314522341806193037139254959705454075778110118849298562194832632452981491,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 5.357s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_vendor_test_csr_access","qual_name":"1.chip_sw_otp_ctrl_vendor_test_csr_access.1288043065826273139496810264947262760947824411979759307570826994176940036762","seed":1288043065826273139496810264947262760947824411979759307570826994176940036762,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.274s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"1.chip_sw_lc_ctrl_transition.63212296621811515350921158534878055120241971653773559545375984110243786468206","seed":63212296621811515350921158534878055120241971653773559545375984110243786468206,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.596s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"1.chip_sw_lc_walkthrough_dev.3706122587947945363554030396900738227364098993041573680713224610975988027367","seed":3706122587947945363554030396900738227364098993041573680713224610975988027367,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.533s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"1.chip_sw_lc_walkthrough_prod.4427995770136394505957971721087796407668292396777981133524897960483165166423","seed":4427995770136394505957971721087796407668292396777981133524897960483165166423,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.158s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_prodend","qual_name":"1.chip_sw_lc_walkthrough_prodend.23465227138689744076292239194426195119396517427290895310755349151168191259402","seed":23465227138689744076292239194426195119396517427290895310755349151168191259402,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_walkthrough_prodend/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.335s, Critical Path: 0.06s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"1.chip_sw_lc_walkthrough_rma.90266490484582748269220583789175957817949338685448776359846539262136240884494","seed":90266490484582748269220583789175957817949338685448776359846539262136240884494,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 10.944s, Critical Path: 0.12s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_testunlocks","qual_name":"1.chip_sw_lc_walkthrough_testunlocks.2747074017776922234946369044067832538449647196916745937193126465523716824333","seed":2747074017776922234946369044067832538449647196916745937193126465523716824333,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_walkthrough_testunlocks/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.895s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_main_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_main_power_glitch_reset.43207498853959680363732406162654857087491809253012447715208697930852681821362","seed":43207498853959680363732406162654857087491809253012447715208697930852681821362,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_main_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.244s, Critical Path: 0.06s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_sleep_power_glitch_reset.47425373601409014808612441555753061845537502968903500854053757267480320663112","seed":47425373601409014808612441555753061845537502968903500854053757267480320663112,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.753s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.45489866391591289929484860688867453688606846831064185925988671981331810807681","seed":45489866391591289929484860688867453688606846831064185925988671981331810807681,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.856s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.17315092623114627050223444026390849902346560598223916669551169666325002548581","seed":17315092623114627050223444026390849902346560598223916669551169666325002548581,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.631s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_disabled","qual_name":"1.chip_sw_pwrmgr_sleep_disabled.106241351325581217788089876921138792517341123432275453916623122849114816732267","seed":106241351325581217788089876921138792517341123432275453916623122849114816732267,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_disabled/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.374s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_wdog_reset","qual_name":"1.chip_sw_pwrmgr_wdog_reset.8152199115164021532721565025924887820125384550292280850497909100508695764128","seed":8152199115164021532721565025924887820125384550292280850497909100508695764128,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_wdog_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.390s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_test","qual_name":"1.chip_sw_alert_test.40319435728495707869382470186391301204274465158654014236995699589296723850718","seed":40319435728495707869382470186391301204274465158654014236995699589296723850718,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_test/latest/run.log","log_context":["Another command (pid=3933821) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests/autogen/top_darjeeling:alert_test_sim_dv': no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - sw/device/tests/autogen/top_darjeeling\n","ERROR: no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - sw/device/tests/autogen/top_darjeeling\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_escalation","qual_name":"1.chip_sw_alert_handler_escalation.72318814971867192981599088408708588954180117152775633014471731084976901122257","seed":72318814971867192981599088408708588954180117152775633014471731084976901122257,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_escalation/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_escalation_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.132s, Critical Path: 0.07s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_reverse_ping_in_deep_sleep","qual_name":"1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.29129780425917547541777205706067449295751124537627570664129971473325480113300","seed":29129780425917547541777205706067449295751124537627570664129971473325480113300,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.755s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"1.chip_sw_alert_handler_lpg_sleep_mode_alerts.11022698781465167059621949750722694695467782001525764407792669828467461892717","seed":11022698781465167059621949750722694695467782001525764407792669828467461892717,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Another command (pid=3933821) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=3923903) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=3939250) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"1.chip_sw_alert_handler_lpg_sleep_mode_pings.112813076471112065434447752732072746974854969727072671998072399160084802198471","seed":112813076471112065434447752732072746974854969727072671998072399160084802198471,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.194s, Critical Path: 0.05s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_clkoff","qual_name":"1.chip_sw_alert_handler_lpg_clkoff.24073207123572217723706289046056465108538689628642151732732519905612507859492","seed":24073207123572217723706289046056465108538689628642151732732519905612507859492,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_lpg_clkoff/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.233s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_reset_toggle","qual_name":"1.chip_sw_alert_handler_lpg_reset_toggle.100039076710945984376999269542130205399828222855932674759799919333649349268140","seed":100039076710945984376999269542130205399828222855932674759799919333649349268140,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_lpg_reset_toggle/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.370s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_entropy","qual_name":"1.chip_sw_alert_handler_entropy.18432967305827681111157569201998579665173804924900558135707655317657704798337","seed":18432967305827681111157569201998579665173804924900558135707655317657704798337,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_alert_handler_entropy/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.320s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_csrng_fuse_en_sw_app_read_test","qual_name":"1.chip_sw_csrng_fuse_en_sw_app_read_test.91985986905189529174009376034881143781740304483051398628911655461106671639111","seed":91985986905189529174009376034881143781740304483051398628911655461106671639111,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.495s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_kmac_app_rom","qual_name":"1.chip_sw_kmac_app_rom.58937546891085222141789753503738597526961293103098864218753594761445317781327","seed":58937546891085222141789753503738597526961293103098864218753594761445317781327,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest/run.log","log_context":["INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery labels(data, //sw/device/tests:kmac_app_rom_test_sim_dv) union labels(srcs, //sw/device/tests:kmac_app_rom_test_sim_dv) --ui_event_filters=-info --noshow_progress --//hw/top=darjeeling --//hw/top=darjeeling --output=starlark\n","---- STDOUT ----\n","\n","---- STDERR ----\n","Another command (pid=4020156) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","ERROR: Error doing post analysis query: Evaluation of subquery \"labels('data', //sw/device/tests:kmac_app_rom_test_sim_dv)\" failed (did you want to use --keep_going?): in 'data' of rule //sw/device/tests:kmac_app_rom_test_sim_dv: configured target of type test_suite does not have attribute 'data'\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access_jitter_en","qual_name":"1.chip_sw_sram_ctrl_scrambled_access_jitter_en.106616373477002353305905778731262937886457364375226029212793177705379399286167","seed":106616373477002353305905778731262937886457364375226029212793177705379399286167,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD\n","ERROR: no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sram_ctrl_execution_main","qual_name":"1.chip_sw_sram_ctrl_execution_main.16180313449923242188248067667540298922410021389659391781735232801052863654208","seed":16180313449923242188248067667540298922410021389659391781735232801052863654208,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_execution_main/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.408s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_clkmgr_reset_frequency","qual_name":"1.chip_sw_clkmgr_reset_frequency.30181073021325973823473973851958808529629876287946488703641495784751579300407","seed":30181073021325973823473973851958808529629876287946488703641495784751579300407,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_reset_frequency/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:clkmgr_reset_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_reset_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:clkmgr_reset_frequency_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.367s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_clkmgr_sleep_frequency","qual_name":"1.chip_sw_clkmgr_sleep_frequency.73155666650145044129487208667316349399567091379105766896122471929728893487754","seed":73155666650145044129487208667316349399567091379105766896122471929728893487754,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_sleep_frequency/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.072s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_ast_clk_outputs","qual_name":"1.chip_sw_ast_clk_outputs.71443324288376420130228900454703493826838726221388852754411070738511953770047","seed":71443324288376420130228900454703493826838726221388852754411070738511953770047,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_ast_clk_outputs/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:ast_clk_outs_test_sim_dv' failed; build aborted: Target //sw/device/tests:ast_clk_outs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:ast_clk_outs_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.368s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_program_error","qual_name":"1.chip_sw_lc_ctrl_program_error.69066356443068641926112660796231038894516812481233876817219745790647195033964","seed":69066356443068641926112660796231038894516812481233876817219745790647195033964,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.669s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.103439042866409446699691305975347615642888521030524379131687578670016271333158","seed":103439042866409446699691305975347615642888521030524379131687578670016271333158,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=4085221) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=4085696) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)\n","ERROR: no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"1.chip_sw_rv_dm_access_after_wakeup.28664185533744768198090214129788639354535371853168196569762783799848204242282","seed":28664185533744768198090214129788639354535371853168196569762783799848204242282,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)\n","ERROR: no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_access_after_escalation_reset","qual_name":"1.chip_sw_rv_dm_access_after_escalation_reset.7222313136234617396358283572513360050164725533126023252398929589769888244768","seed":7222313136234617396358283572513360050164725533126023252398929589769888244768,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_escalation_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.398s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_power_virus","qual_name":"1.chip_sw_power_virus.112582723126748834622015222548910920253033192952419842145394008475035980980676","seed":112582723126748834622015222548910920253033192952419842145394008475035980980676,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests:power_virus_systemtest_sim_dv' failed; build aborted: Target //sw/device/tests:power_virus_systemtest_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:power_virus_systemtest_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.125s, Critical Path: 0.05s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"base_rom_e2e_smoke","qual_name":"1.base_rom_e2e_smoke.80320767233091555488098963467928489245001304406024109474105860359246867038449","seed":80320767233091555488098963467928489245001304406024109474105860359246867038449,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.base_rom_e2e_smoke/latest/run.log","log_context":["    _deploy_software_collateral(args)\n","    ~~~~~~~~~~~~~~~~~~~~~~~~~~~^^^^^^\n","  File \"/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py\", line 324, in _deploy_software_collateral\n","    image_string = ImageString(image)\n","  File \"<string>\", line 4, in __init__\n","  File \"/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py\", line 256, in __post_init__\n","    assert flag in KNOWN_FLAGS, f\"Unknown flag '{flag}' used in sw_image '{self.raw}'\"\n","           ^^^^^^^^^^^^^^^^^^^\n","AssertionError: Unknown flag 'test_in_second_rom' used in sw_image '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom'\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_smoke","qual_name":"1.rom_e2e_smoke.48506532879671492837927300765561762665098483341837392094635150957946761617997","seed":48506532879671492837927300765561762665098483341837392094635150957946761617997,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_smoke/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_shutdown_exception_c","qual_name":"1.rom_e2e_shutdown_exception_c.10266193201457330664954885353950045567619415036829383066989576641817661800626","seed":10266193201457330664954885353950045567619415036829383066989576641817661800626,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest/run.log","log_context":["cwd=/nightly/current_run/opentitan\n","\n","Waiting for it to complete...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_shutdown_output","qual_name":"1.rom_e2e_shutdown_output.59148581834394926876601618167950146873274407359311505417262369170402070633433","seed":59148581834394926876601618167950146873274407359311505417262369170402070633433,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"1.rom_e2e_asm_init_test_unlocked0.53499291709711547809075880330770496398766830034576862414615938080266023114526","seed":53499291709711547809075880330770496398766830034576862414615938080266023114526,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"1.rom_e2e_asm_init_dev.113921604971164617943590842979024043582810487501732318796709805025199773739751","seed":113921604971164617943590842979024043582810487501732318796709805025199773739751,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_asm_init_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"1.rom_e2e_asm_init_prod.17255048153432980651941772146505657465872400155270264735493701854614949319642","seed":17255048153432980651941772146505657465872400155270264735493701854614949319642,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"1.rom_e2e_asm_init_prod_end.42845659667609548038959098528032571388425880972664757693904023841738002584091","seed":42845659667609548038959098528032571388425880972664757693904023841738002584091,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"1.rom_e2e_asm_init_rma.23768772760953471166545452735506382833575899069750092557307568075448140827988","seed":23768772760953471166545452735506382833575899069750092557307568075448140827988,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_asm_init_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_static_critical","qual_name":"1.rom_e2e_static_critical.76168991163593385008377050859518303497419196163006504540047294173019571957834","seed":76168991163593385008377050859518303497419196163006504540047294173019571957834,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_meas","qual_name":"1.rom_e2e_keymgr_init_rom_ext_meas.44996828420844886448789221468109994870386628153218943432289271825842546441291","seed":44996828420844886448789221468109994870386628153218943432289271825842546441291,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_no_meas","qual_name":"1.rom_e2e_keymgr_init_rom_ext_no_meas.39728941400306848347180354313966643627628095183803817269358187888599749101549","seed":39728941400306848347180354313966643627628095183803817269358187888599749101549,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_invalid_meas","qual_name":"1.rom_e2e_keymgr_init_rom_ext_invalid_meas.84530971599180682728119417253672371132227293353867411515673517402083638279382","seed":84530971599180682728119417253672371132227293353867411515673517402083638279382,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_test_unlocked0_otbn","qual_name":"1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.90162151830578213947535146072905629771543649588482048590642121329954861958975","seed":90162151830578213947535146072905629771543649588482048590642121329954861958975,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_test_unlocked0_sw","qual_name":"1.rom_e2e_sigverify_mod_exp_test_unlocked0_sw.114360236438965842584592559626561179642209585293213490588640616060679480782637","seed":114360236438965842584592559626561179642209585293213490588640616060679480782637,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_dev_otbn","qual_name":"1.rom_e2e_sigverify_mod_exp_dev_otbn.74273928679651646535713132592804497025367074616500368619340411688434399126476","seed":74273928679651646535713132592804497025367074616500368619340411688434399126476,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_dev_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_dev_sw","qual_name":"1.rom_e2e_sigverify_mod_exp_dev_sw.64663497503449088652992551968502211371440616828169624164551310237337465163986","seed":64663497503449088652992551968502211371440616828169624164551310237337465163986,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_dev_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_otbn","qual_name":"1.rom_e2e_sigverify_mod_exp_prod_otbn.31953838223855759691978158651673877117607469800781561276668493047346864144683","seed":31953838223855759691978158651673877117607469800781561276668493047346864144683,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_sw","qual_name":"1.rom_e2e_sigverify_mod_exp_prod_sw.56849081989489867593829101944524101264686983857165505681777841182960736751955","seed":56849081989489867593829101944524101264686983857165505681777841182960736751955,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_end_otbn","qual_name":"1.rom_e2e_sigverify_mod_exp_prod_end_otbn.18665337155490345991155132853538577603519232118736534831779314242057705299750","seed":18665337155490345991155132853538577603519232118736534831779314242057705299750,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_end_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_end_sw","qual_name":"1.rom_e2e_sigverify_mod_exp_prod_end_sw.22200911316105826549070889921469150579780060257249200039970191042213281043386","seed":22200911316105826549070889921469150579780060257249200039970191042213281043386,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_prod_end_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_rma_otbn","qual_name":"1.rom_e2e_sigverify_mod_exp_rma_otbn.32373008897644636602645314112317629537310758404181148795733639450365422084835","seed":32373008897644636602645314112317629537310758404181148795733639450365422084835,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_rma_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_rma_sw","qual_name":"1.rom_e2e_sigverify_mod_exp_rma_sw.65293056345509389410912048444542573042498712702715413136070527915412716070442","seed":65293056345509389410912048444542573042498712702715413136070527915412716070442,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_rma_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"1.rom_volatile_raw_unlock.20186283472246117505694239625699139649267587255220975955248608305270092951800","seed":20186283472246117505694239625699139649267587255220975955248608305270092951800,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_volatile_raw_unlock/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"1.rom_raw_unlock.109419254556704429450304134157539776502430192554684032293653093358589431043325","seed":109419254556704429450304134157539776502430192554684032293653093358589431043325,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_raw_unlock/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"1.rom_e2e_self_hash.81195697448933038147217171861994920394418110562866268769126650864946121759425","seed":81195697448933038147217171861994920394418110562866268769126650864946121759425,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_smoketest_signed","qual_name":"1.chip_sw_uart_smoketest_signed.90082473149646282582272153038802291674192490142239645753295399714789613831199","seed":90082473149646282582272153038802291674192490142239645753295399714789613831199,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_smoketest_signed/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:uart_smoketest_signed_sim_dv': no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_keymgr_functest","qual_name":"1.rom_keymgr_functest.61920690566300428891679259295045616023604643928490731016463952221484889242191","seed":61920690566300428891679259295045616023604643928490731016463952221484889242191,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.rom_keymgr_functest/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv' failed; build aborted: Target //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.352s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_example_manufacturer","qual_name":"2.chip_sw_example_manufacturer.50509175003215039064046740962575898203154719134093901601182164182922501753563","seed":50509175003215039064046740962575898203154719134093901601182164182922501753563,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_manufacturer/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.937s, Critical Path: 0.05s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_data_integrity_escalation","qual_name":"2.chip_sw_data_integrity_escalation.71526242433012178288703457479975286778484301734047427462096501058252696995024","seed":71526242433012178288703457479975286778484301734047427462096501058252696995024,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_data_integrity_escalation/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 19.236s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sleep_pin_wake","qual_name":"2.chip_sw_sleep_pin_wake.26855365590336178229787551862134134135708564276809244849630597336628028922119","seed":26855365590336178229787551862134134135708564276809244849630597336628028922119,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sleep_pin_wake/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 6.212s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sleep_pin_retention","qual_name":"2.chip_sw_sleep_pin_retention.98319339007992994933329330016799604141378726307831276737929680927352013634313","seed":98319339007992994933329330016799604141378726307831276737929680927352013634313,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sleep_pin_retention/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.573s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx","qual_name":"2.chip_sw_uart_tx_rx.38373615751013168405012175645731438899983131855519454137012182524453728489291","seed":38373615751013168405012175645731438899983131855519454137012182524453728489291,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.650s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx_bootstrap","qual_name":"2.chip_sw_uart_tx_rx_bootstrap.113589848590177465494618528975364560286915772392239106970148592392411503714279","seed":113589848590177465494618528975364560286915772392239106970148592392411503714279,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_tx_rx_bootstrap/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.199s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_inject_scramble_seed","qual_name":"2.chip_sw_inject_scramble_seed.16721198126952170366187191646132746809588270475868108513641647911622137867678","seed":16721198126952170366187191646132746809588270475868108513641647911622137867678,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_inject_scramble_seed/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.714s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_exit_test_unlocked_bootstrap","qual_name":"2.chip_sw_exit_test_unlocked_bootstrap.112408723811316569884098805818076829038842243159975997453480569236235375115712","seed":112408723811316569884098805818076829038842243159975997453480569236235375115712,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_exit_test_unlocked_bootstrap/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.734s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"2.chip_sw_uart_rand_baudrate.24390708945923584677186375063647331174625515167397155366316353500142649031748","seed":24390708945923584677186375063647331174625515167397155366316353500142649031748,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 11.716s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx_alt_clk_freq","qual_name":"2.chip_sw_uart_tx_rx_alt_clk_freq.18886170453115554265588141784019877402136812528889643579821437721012368781172","seed":18886170453115554265588141784019877402136812528889643579821437721012368781172,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.809s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_i2c_host_tx_rx","qual_name":"2.chip_sw_i2c_host_tx_rx.96398232383739646497431858323916448442218611137851777841813407110629643993290","seed":96398232383739646497431858323916448442218611137851777841813407110629643993290,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_i2c_host_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 4.084s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_i2c_device_tx_rx","qual_name":"2.chip_sw_i2c_device_tx_rx.114615639410945912754955609141864354949909919721665436024854091587818878925740","seed":114615639410945912754955609141864354949909919721665436024854091587818878925740,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_i2c_device_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 5.250s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_spi_device_tpm","qual_name":"2.chip_sw_spi_device_tpm.39355447620658201270781744599321433122568961205651255972456291697469415183787","seed":39355447620658201270781744599321433122568961205651255972456291697469415183787,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_device_tpm/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 10.768s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_spi_host_tx_rx","qual_name":"2.chip_sw_spi_host_tx_rx.29594324732870777736213622757577613353796856722855662631591403222382800539588","seed":29594324732870777736213622757577613353796856722855662631591403222382800539588,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_host_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.284s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_otp_hw_cfg","qual_name":"2.chip_sw_lc_ctrl_otp_hw_cfg.99968173433093526081285626708883080724248990361761548584044532706300176558034","seed":99968173433093526081285626708883080724248990361761548584044532706300176558034,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_otp_hw_cfg/latest/run.log","log_context":["Another command (pid=68583) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=73323) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=74736) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)\n","ERROR: no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_test_unlocked0","qual_name":"2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.83014751225310591994712251535391960514160161387698818536050375111581488901867","seed":83014751225310591994712251535391960514160161387698818536050375111581488901867,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 14.824s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_dev","qual_name":"2.chip_sw_otp_ctrl_lc_signals_dev.58618289351953766612893628052543613351158525794117655776165071262713375868353","seed":58618289351953766612893628052543613351158525794117655776165071262713375868353,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_dev/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.335s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_prod","qual_name":"2.chip_sw_otp_ctrl_lc_signals_prod.63203548220062112318455927368452891411616521567759432761699993448216171758680","seed":63203548220062112318455927368452891411616521567759432761699993448216171758680,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_prod/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 4.624s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"2.chip_sw_otp_ctrl_lc_signals_rma.70683463630737635584124292713439702043580456639117798983298751614548719996706","seed":70683463630737635584124292713439702043580456639117798983298751614548719996706,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 7.731s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_vendor_test_csr_access","qual_name":"2.chip_sw_otp_ctrl_vendor_test_csr_access.99076715992463442996152783944538569735564800385277699515160711306535728023054","seed":99076715992463442996152783944538569735564800385277699515160711306535728023054,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.780s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"2.chip_sw_lc_ctrl_transition.52710360281387724671147282329566761261442548163568368875134489485656372670828","seed":52710360281387724671147282329566761261442548163568368875134489485656372670828,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.844s, Critical Path: 0.05s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"2.chip_sw_lc_walkthrough_dev.69941426306629643407302616964262512292187269113134540147292872602359806923056","seed":69941426306629643407302616964262512292187269113134540147292872602359806923056,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.673s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"2.chip_sw_lc_walkthrough_prod.8674614410349202890000810106244432523296893685127531292965416309178985058832","seed":8674614410349202890000810106244432523296893685127531292965416309178985058832,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 8.816s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_prodend","qual_name":"2.chip_sw_lc_walkthrough_prodend.91743501942038876696461850289020014621456336969757607134009803946371843350650","seed":91743501942038876696461850289020014621456336969757607134009803946371843350650,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_walkthrough_prodend/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.133s, Critical Path: 0.00s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"2.chip_sw_lc_walkthrough_rma.59888877893754212923549641926286375756420035934650597717652337594451471341322","seed":59888877893754212923549641926286375756420035934650597717652337594451471341322,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.095s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_testunlocks","qual_name":"2.chip_sw_lc_walkthrough_testunlocks.22325785707486585015890224121733682595022838093773466950594785907364635820965","seed":22325785707486585015890224121733682595022838093773466950594785907364635820965,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_walkthrough_testunlocks/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 7.790s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_main_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_main_power_glitch_reset.81462917573951005258606096462739842668077197293216572412263469530211589097348","seed":81462917573951005258606096462739842668077197293216572412263469530211589097348,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_main_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 8.317s, Critical Path: 0.09s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_sleep_power_glitch_reset.105340913096153424411003958236508227654695854886360570553688656201326005682901","seed":105340913096153424411003958236508227654695854886360570553688656201326005682901,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 12.805s, Critical Path: 0.10s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3099550617606389852631852104443719696948278356391912392035547908909465014608","seed":3099550617606389852631852104443719696948278356391912392035547908909465014608,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.294s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.98891892631952496122439712905385567347428147970082797499053919631953461003348","seed":98891892631952496122439712905385567347428147970082797499053919631953461003348,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 10.791s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_disabled","qual_name":"2.chip_sw_pwrmgr_sleep_disabled.50200665172343102929881714004155937152358527397471401486240972826393468614203","seed":50200665172343102929881714004155937152358527397471401486240972826393468614203,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_disabled/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 5.541s, Critical Path: 0.05s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_wdog_reset","qual_name":"2.chip_sw_pwrmgr_wdog_reset.209768986000043672845476028340957179322947503688267189360542975610684701150","seed":209768986000043672845476028340957179322947503688267189360542975610684701150,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_pwrmgr_wdog_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.071s, Critical Path: 0.06s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_test","qual_name":"2.chip_sw_alert_test.94915067149296164628899131979279786978720103252892543928860454590241529397133","seed":94915067149296164628899131979279786978720103252892543928860454590241529397133,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_test/latest/run.log","log_context":["Another command (pid=251381) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests/autogen/top_darjeeling:alert_test_sim_dv': no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - sw/device/tests/autogen/top_darjeeling\n","ERROR: no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - sw/device/tests/autogen/top_darjeeling\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_escalation","qual_name":"2.chip_sw_alert_handler_escalation.34282368726159872864031821372507621147453969463103277478729584457387169255828","seed":34282368726159872864031821372507621147453969463103277478729584457387169255828,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_escalation/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_escalation_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.577s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_reverse_ping_in_deep_sleep","qual_name":"2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.100702530905374338332590995855519987814235869470577036147441824351613383185284","seed":100702530905374338332590995855519987814235869470577036147441824351613383185284,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.074s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"2.chip_sw_alert_handler_lpg_sleep_mode_alerts.115720503317183603098780938115553025116733993478464774870131267779029686583183","seed":115720503317183603098780938115553025116733993478464774870131267779029686583183,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=254354) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"2.chip_sw_alert_handler_lpg_sleep_mode_pings.105583487263530797748012727124861604822313081578220615218410863995003994564089","seed":105583487263530797748012727124861604822313081578220615218410863995003994564089,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.557s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_clkoff","qual_name":"2.chip_sw_alert_handler_lpg_clkoff.85051904438063550030868183123299239601549435806867404091687846236924864488090","seed":85051904438063550030868183123299239601549435806867404091687846236924864488090,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_lpg_clkoff/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.576s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_reset_toggle","qual_name":"2.chip_sw_alert_handler_lpg_reset_toggle.48226755707875945432531730190320689171343533495182065453527734062314636414482","seed":48226755707875945432531730190320689171343533495182065453527734062314636414482,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_lpg_reset_toggle/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.607s, Critical Path: 0.06s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_entropy","qual_name":"2.chip_sw_alert_handler_entropy.53502838178434981775909302989459932435433632440240229950285071950380411062242","seed":53502838178434981775909302989459932435433632440240229950285071950380411062242,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_alert_handler_entropy/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.574s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_csrng_fuse_en_sw_app_read_test","qual_name":"2.chip_sw_csrng_fuse_en_sw_app_read_test.20379438686465290659850750846598258904800724668192486485827501368761997426195","seed":20379438686465290659850750846598258904800724668192486485827501368761997426195,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 10.717s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_kmac_app_rom","qual_name":"2.chip_sw_kmac_app_rom.44128449654182956463485884507850049965006895113870421279092188070344433326280","seed":44128449654182956463485884507850049965006895113870421279092188070344433326280,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_app_rom/latest/run.log","log_context":["Another command (pid=342147) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=342408) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=344243) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Build option --define has changed, discarding analysis cache (this can be expensive, see https://bazel.build/advanced/performance/iteration-speed).\n","DEBUG: /nightly/current_run/opentitan/rules/autogen.bzl:536:14: NOTE: stamping is disabled, the build_info section will use a fixed version string\n","ERROR: Error doing post analysis query: Evaluation of subquery \"labels('data', //sw/device/tests:kmac_app_rom_test_sim_dv)\" failed (did you want to use --keep_going?): in 'data' of rule //sw/device/tests:kmac_app_rom_test_sim_dv: configured target of type test_suite does not have attribute 'data'\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access_jitter_en","qual_name":"2.chip_sw_sram_ctrl_scrambled_access_jitter_en.92023023601119282033707511958099082347973523436558437497842429966240683617801","seed":92023023601119282033707511958099082347973523436558437497842429966240683617801,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=345411) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD\n","ERROR: no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sram_ctrl_execution_main","qual_name":"2.chip_sw_sram_ctrl_execution_main.27898188237273401272234209340067846333177623685818724609445357683554659786203","seed":27898188237273401272234209340067846333177623685818724609445357683554659786203,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_execution_main/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.719s, Critical Path: 0.05s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_clkmgr_reset_frequency","qual_name":"2.chip_sw_clkmgr_reset_frequency.12900965620079218175186972415447407748325509695906680679879137414423776855583","seed":12900965620079218175186972415447407748325509695906680679879137414423776855583,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_reset_frequency/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:clkmgr_reset_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_reset_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:clkmgr_reset_frequency_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.715s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_clkmgr_sleep_frequency","qual_name":"2.chip_sw_clkmgr_sleep_frequency.7178551420212576026706780187454592969896145267723879891852202416170800253437","seed":7178551420212576026706780187454592969896145267723879891852202416170800253437,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_sleep_frequency/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.771s, Critical Path: 0.07s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_ast_clk_outputs","qual_name":"2.chip_sw_ast_clk_outputs.21986632714380574696330274160906665865620851297421646625630625098509349976485","seed":21986632714380574696330274160906665865620851297421646625630625098509349976485,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_ast_clk_outputs/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:ast_clk_outs_test_sim_dv' failed; build aborted: Target //sw/device/tests:ast_clk_outs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:ast_clk_outs_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.385s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_program_error","qual_name":"2.chip_sw_lc_ctrl_program_error.14166341325174735074234118037766237510190940770547461921487867219818951785432","seed":14166341325174735074234118037766237510190940770547461921487867219818951785432,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_lc_ctrl_program_error/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.381s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.104712763589420843071012168688335448332566914386139554801988514928942116984977","seed":104712763589420843071012168688335448332566914386139554801988514928942116984977,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=400105) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)\n","ERROR: no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"2.chip_sw_rv_dm_access_after_wakeup.65912507495822095929075234254391029998244032490278272843546595750330616856755","seed":65912507495822095929075234254391029998244032490278272843546595750330616856755,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)\n","ERROR: no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_access_after_escalation_reset","qual_name":"2.chip_sw_rv_dm_access_after_escalation_reset.59637946980343335453900180884290808069245850834845393021017514805329343893894","seed":59637946980343335453900180884290808069245850834845393021017514805329343893894,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_escalation_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.395s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_power_virus","qual_name":"2.chip_sw_power_virus.102245001195388207412337989737785131864760576080309604282660988132956443125465","seed":102245001195388207412337989737785131864760576080309604282660988132956443125465,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests:power_virus_systemtest_sim_dv' failed; build aborted: Target //sw/device/tests:power_virus_systemtest_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:power_virus_systemtest_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.418s, Critical Path: 0.06s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"base_rom_e2e_smoke","qual_name":"2.base_rom_e2e_smoke.69510739331919704595300360014619946645619468199725847304224384420826925829797","seed":69510739331919704595300360014619946645619468199725847304224384420826925829797,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.base_rom_e2e_smoke/latest/run.log","log_context":["    _deploy_software_collateral(args)\n","    ~~~~~~~~~~~~~~~~~~~~~~~~~~~^^^^^^\n","  File \"/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py\", line 324, in _deploy_software_collateral\n","    image_string = ImageString(image)\n","  File \"<string>\", line 4, in __init__\n","  File \"/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py\", line 256, in __post_init__\n","    assert flag in KNOWN_FLAGS, f\"Unknown flag '{flag}' used in sw_image '{self.raw}'\"\n","           ^^^^^^^^^^^^^^^^^^^\n","AssertionError: Unknown flag 'test_in_second_rom' used in sw_image '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom'\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_smoke","qual_name":"2.rom_e2e_smoke.27441090397445588567419064640326633311508993194201072190425950950661479616359","seed":27441090397445588567419064640326633311508993194201072190425950950661479616359,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_smoke/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=465151) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=465568) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_shutdown_exception_c","qual_name":"2.rom_e2e_shutdown_exception_c.107897485528539505539219165059738907600474090211338448440557445865276255256802","seed":107897485528539505539219165059738907600474090211338448440557445865276255256802,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_shutdown_exception_c/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=470480) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_shutdown_output","qual_name":"2.rom_e2e_shutdown_output.1005109908806129452871350425526341043015337192265566731167407811168135823291","seed":1005109908806129452871350425526341043015337192265566731167407811168135823291,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_shutdown_output/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"2.rom_e2e_asm_init_test_unlocked0.17774472390682914983910395523120484851344038454982034582404473823139153400086","seed":17774472390682914983910395523120484851344038454982034582404473823139153400086,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"2.rom_e2e_asm_init_dev.45607589275329666442170543925205190601619959829562025097338900554580834460594","seed":45607589275329666442170543925205190601619959829562025097338900554580834460594,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_asm_init_dev/latest/run.log","log_context":["cwd=/nightly/current_run/opentitan\n","\n","Waiting for it to complete...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"2.rom_e2e_asm_init_prod.74235647352422336983216408432305423868840040858174347770662041289130750862715","seed":74235647352422336983216408432305423868840040858174347770662041289130750862715,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"2.rom_e2e_asm_init_prod_end.47838608522965487797091867679247496855489009222898696233294888192774203205713","seed":47838608522965487797091867679247496855489009222898696233294888192774203205713,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"2.rom_e2e_asm_init_rma.110241392939621607774219795662385585888031138862504859533210910994402725724748","seed":110241392939621607774219795662385585888031138862504859533210910994402725724748,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_asm_init_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_static_critical","qual_name":"2.rom_e2e_static_critical.4647576522034205036310685015418301757087993228749577981920992631173033904078","seed":4647576522034205036310685015418301757087993228749577981920992631173033904078,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_static_critical/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_meas","qual_name":"2.rom_e2e_keymgr_init_rom_ext_meas.41959728367829248858349326223219805106760859040288016314020543072155815914556","seed":41959728367829248858349326223219805106760859040288016314020543072155815914556,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_no_meas","qual_name":"2.rom_e2e_keymgr_init_rom_ext_no_meas.30476043865897462666664174569615700396763996002316987105755249634912393329679","seed":30476043865897462666664174569615700396763996002316987105755249634912393329679,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_invalid_meas","qual_name":"2.rom_e2e_keymgr_init_rom_ext_invalid_meas.49951775638793884061520104814818132157709142437436955505301022240500741197195","seed":49951775638793884061520104814818132157709142437436955505301022240500741197195,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_test_unlocked0_otbn","qual_name":"2.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.56620762507982927530238950138767127917113227148871723851691648102910464411644","seed":56620762507982927530238950138767127917113227148871723851691648102910464411644,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=477115) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_test_unlocked0_sw","qual_name":"2.rom_e2e_sigverify_mod_exp_test_unlocked0_sw.20114904960675022550673461606118352390955152315472387424593710663710521172688","seed":20114904960675022550673461606118352390955152315472387424593710663710521172688,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_test_unlocked0_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_dev_otbn","qual_name":"2.rom_e2e_sigverify_mod_exp_dev_otbn.28055337804872802452912672198372146872062288224810927992625604899652718385778","seed":28055337804872802452912672198372146872062288224810927992625604899652718385778,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_dev_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_dev_sw","qual_name":"2.rom_e2e_sigverify_mod_exp_dev_sw.24168930795889662323987123092746347377850042000794489829312030391550578198327","seed":24168930795889662323987123092746347377850042000794489829312030391550578198327,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_dev_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_otbn","qual_name":"2.rom_e2e_sigverify_mod_exp_prod_otbn.61278810750777404182034465257774732337082113504389204439512286344882907993488","seed":61278810750777404182034465257774732337082113504389204439512286344882907993488,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_sw","qual_name":"2.rom_e2e_sigverify_mod_exp_prod_sw.26168386203307278462996994764824754398521617750095328472130548982754376490780","seed":26168386203307278462996994764824754398521617750095328472130548982754376490780,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_end_otbn","qual_name":"2.rom_e2e_sigverify_mod_exp_prod_end_otbn.10486027986192297103887193829727834700192551865767229397689714828172482708785","seed":10486027986192297103887193829727834700192551865767229397689714828172482708785,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_end_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_end_sw","qual_name":"2.rom_e2e_sigverify_mod_exp_prod_end_sw.96125362287333704755414370904553141675780275576041502508531052294279383667375","seed":96125362287333704755414370904553141675780275576041502508531052294279383667375,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_prod_end_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_rma_otbn","qual_name":"2.rom_e2e_sigverify_mod_exp_rma_otbn.41260453339670036535702199912678906062116223180281779409014765286215069479279","seed":41260453339670036535702199912678906062116223180281779409014765286215069479279,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_rma_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_rma_sw","qual_name":"2.rom_e2e_sigverify_mod_exp_rma_sw.79933544908863429040900019146079366349004287525523637374138368302475838032784","seed":79933544908863429040900019146079366349004287525523637374138368302475838032784,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_sigverify_mod_exp_rma_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"2.rom_volatile_raw_unlock.42169114538490260311981202100416398871151141040581392817990395602065859940914","seed":42169114538490260311981202100416398871151141040581392817990395602065859940914,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_volatile_raw_unlock/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"2.rom_raw_unlock.12561200069276291234214390812061713723525994679158558403224471768686448784603","seed":12561200069276291234214390812061713723525994679158558403224471768686448784603,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_raw_unlock/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"2.rom_e2e_self_hash.103781940772660392829436271970152750236263478480470493104422833369927322341585","seed":103781940772660392829436271970152750236263478480470493104422833369927322341585,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_e2e_self_hash/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_smoketest_signed","qual_name":"2.chip_sw_uart_smoketest_signed.89711841612747898935538037049431316006301286390240899753475961497334951752004","seed":89711841612747898935538037049431316006301286390240899753475961497334951752004,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_uart_smoketest_signed/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:uart_smoketest_signed_sim_dv': no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_keymgr_functest","qual_name":"2.rom_keymgr_functest.62684871657848013983701332663918371653278419338385416945441004247806330583190","seed":62684871657848013983701332663918371653278419338385416945441004247806330583190,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.rom_keymgr_functest/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv' failed; build aborted: Target //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.529s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_data_integrity_escalation","qual_name":"3.chip_sw_data_integrity_escalation.111130110729019808270231922195568551222298371161152257074612762438779953226952","seed":111130110729019808270231922195568551222298371161152257074612762438779953226952,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_data_integrity_escalation/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.361s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx","qual_name":"3.chip_sw_uart_tx_rx.55729891892665196223505707010625605158696156232078114051307658227640474177441","seed":55729891892665196223505707010625605158696156232078114051307658227640474177441,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_uart_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 12.216s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"3.chip_sw_uart_rand_baudrate.12844583091842770290051181902521892642497776024460488063023715733602912814429","seed":12844583091842770290051181902521892642497776024460488063023715733602912814429,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 6.263s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx_alt_clk_freq","qual_name":"3.chip_sw_uart_tx_rx_alt_clk_freq.21427705138566814284790240034451875447667477795366000240854692665889233541862","seed":21427705138566814284790240034451875447667477795366000240854692665889233541862,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.232s, Critical Path: 0.08s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"3.chip_sw_lc_ctrl_transition.93254338710652465160235623550257635512527566617733242275022997979906159108590","seed":93254338710652465160235623550257635512527566617733242275022997979906159108590,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 6.344s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"3.chip_sw_alert_handler_lpg_sleep_mode_alerts.31174401226358492561421030723667275702802161383434362742338371849164393308220","seed":31174401226358492561421030723667275702802161383434362742338371849164393308220,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Another command (pid=533477) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=557241) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=556314) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_data_integrity_escalation","qual_name":"4.chip_sw_data_integrity_escalation.107098671917473010268083042732228641654082216235756917877879826521946726152978","seed":107098671917473010268083042732228641654082216235756917877879826521946726152978,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_data_integrity_escalation/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.778s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx","qual_name":"4.chip_sw_uart_tx_rx.113465600696968529595311842315367862698052556401133158486574683509731849191798","seed":113465600696968529595311842315367862698052556401133158486574683509731849191798,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_uart_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.868s, Critical Path: 0.10s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"4.chip_sw_uart_rand_baudrate.37201648641975390240239970382764887787187782404005599356498362526290377161679","seed":37201648641975390240239970382764887787187782404005599356498362526290377161679,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.750s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx_alt_clk_freq","qual_name":"4.chip_sw_uart_tx_rx_alt_clk_freq.9108492036669084746609523266726964658275402607053871789070235594139610460556","seed":9108492036669084746609523266726964658275402607053871789070235594139610460556,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 4.000s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"4.chip_sw_lc_ctrl_transition.36304122662773986997592645929653557609242131373455317655877237766091406231820","seed":36304122662773986997592645929653557609242131373455317655877237766091406231820,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.572s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"4.chip_sw_alert_handler_lpg_sleep_mode_alerts.86959044676223370529228306783194591179212521130346282023731980703141701316763","seed":86959044676223370529228306783194591179212521130346282023731980703141701316763,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Another command (pid=573047) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=572825) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=549876) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_data_integrity_escalation","qual_name":"5.chip_sw_data_integrity_escalation.24547776431693110973762591885256581474855451586226350389632517748821102418821","seed":24547776431693110973762591885256581474855451586226350389632517748821102418821,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_data_integrity_escalation/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.282s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"5.chip_sw_uart_rand_baudrate.104322464776299651783403727569325807725095144607676729993094137025397809878232","seed":104322464776299651783403727569325807725095144607676729993094137025397809878232,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.736s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"5.chip_sw_lc_ctrl_transition.11128159470582713629740764592812637447531400016736210279770429991481726946846","seed":11128159470582713629740764592812637447531400016736210279770429991481726946846,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.540s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"5.chip_sw_alert_handler_lpg_sleep_mode_alerts.92946500211519794436594057565677955500336701098036233656630681328407375240223","seed":92946500211519794436594057565677955500336701098036233656630681328407375240223,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Another command (pid=594029) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=595390) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=596497) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"6.chip_sw_uart_rand_baudrate.10392006672553610992566780281798711511512667893519101129117660526856309787086","seed":10392006672553610992566780281798711511512667893519101129117660526856309787086,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.875s, Critical Path: 0.05s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"6.chip_sw_lc_ctrl_transition.52271987300917368739404897148330719084960012498316930206902915125878421454841","seed":52271987300917368739404897148330719084960012498316930206902915125878421454841,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 15.605s, Critical Path: 0.00s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"6.chip_sw_alert_handler_lpg_sleep_mode_alerts.90752051396636878713779324019569492635008888918852223611138242555473971880992","seed":90752051396636878713779324019569492635008888918852223611138242555473971880992,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Another command (pid=594344) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=596497) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=597225) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"7.chip_sw_uart_rand_baudrate.21979964161750979056836702377014829025501213664581969916317258479824593941380","seed":21979964161750979056836702377014829025501213664581969916317258479824593941380,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 9.787s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"7.chip_sw_lc_ctrl_transition.90670640851942334700881246494805233862071872997674441283847541422066451322236","seed":90670640851942334700881246494805233862071872997674441283847541422066451322236,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 20.751s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"7.chip_sw_alert_handler_lpg_sleep_mode_alerts.113935492320280225826471615938807966885559167674250395330870943195230747674370","seed":113935492320280225826471615938807966885559167674250395330870943195230747674370,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Another command (pid=605803) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=608419) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=601798) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"8.chip_sw_uart_rand_baudrate.79171332867107733659615235643869363496496286865064094527828795233099820469834","seed":79171332867107733659615235643869363496496286865064094527828795233099820469834,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 6.548s, Critical Path: 0.00s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"8.chip_sw_lc_ctrl_transition.82472233824075228696151663732913123134196516139363573691622080753924944385128","seed":82472233824075228696151663732913123134196516139363573691622080753924944385128,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.800s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"8.chip_sw_alert_handler_lpg_sleep_mode_alerts.44780063814594406427687297390232911847919816663597726336006654042411039565690","seed":44780063814594406427687297390232911847919816663597726336006654042411039565690,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Another command (pid=594029) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=595390) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=596497) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"9.chip_sw_uart_rand_baudrate.61980684656125882826067508386260132078006007342881447078295693348655585395921","seed":61980684656125882826067508386260132078006007342881447078295693348655585395921,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.894s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"9.chip_sw_lc_ctrl_transition.35910326866484152096857864796862008644345253293754204593358202706155427498794","seed":35910326866484152096857864796862008644345253293754204593358202706155427498794,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.371s, Critical Path: 0.05s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"9.chip_sw_alert_handler_lpg_sleep_mode_alerts.46557247432524597140658813541403299215380445838489936965612828651957677806132","seed":46557247432524597140658813541403299215380445838489936965612828651957677806132,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=610916) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"10.chip_sw_uart_rand_baudrate.99615767956649956599785664927558917262490616174394646048503439160578370050231","seed":99615767956649956599785664927558917262490616174394646048503439160578370050231,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.301s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"10.chip_sw_lc_ctrl_transition.21699685887091397028015330310423521434960621870207621579062462255395199078111","seed":21699685887091397028015330310423521434960621870207621579062462255395199078111,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 14.873s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2725745812845481965423349009637649650550155244166484803268459918403944895878","seed":2725745812845481965423349009637649650550155244166484803268459918403944895878,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Another command (pid=631591) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=633148) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=631745) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"11.chip_sw_uart_rand_baudrate.36581094487831090109773874158988481080815825002668574793172049760495227581007","seed":36581094487831090109773874158988481080815825002668574793172049760495227581007,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.829s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"11.chip_sw_lc_ctrl_transition.54147874587930741027929213880899772740690533913401807823455750860553753111663","seed":54147874587930741027929213880899772740690533913401807823455750860553753111663,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 7.297s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"11.chip_sw_alert_handler_lpg_sleep_mode_alerts.106509359247163916153583012153883370070466560828203108295392007402848011448456","seed":106509359247163916153583012153883370070466560828203108295392007402848011448456,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Another command (pid=625064) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=626987) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=628372) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"12.chip_sw_uart_rand_baudrate.67114868437137890633641535102548996389245963705522223531981631626689122107476","seed":67114868437137890633641535102548996389245963705522223531981631626689122107476,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.340s, Critical Path: 0.09s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"12.chip_sw_lc_ctrl_transition.8340636282005098960774297552218978495430665396874629690066503797154565594619","seed":8340636282005098960774297552218978495430665396874629690066503797154565594619,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 7.263s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"12.chip_sw_alert_handler_lpg_sleep_mode_alerts.49059258550876911598210995626369610637936026717303131994459688729384747607798","seed":49059258550876911598210995626369610637936026717303131994459688729384747607798,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=638707) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"13.chip_sw_uart_rand_baudrate.26486855003361503267992750260462849383452937896200497051994242820872622117677","seed":26486855003361503267992750260462849383452937896200497051994242820872622117677,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.072s, Critical Path: 0.00s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"13.chip_sw_lc_ctrl_transition.8707439650143936691069032726041124323016274854506706264796357022501523553491","seed":8707439650143936691069032726041124323016274854506706264796357022501523553491,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 4.659s, Critical Path: 0.05s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"13.chip_sw_alert_handler_lpg_sleep_mode_alerts.82250416136949364763643567120528794940315957096036293006981834837647913757096","seed":82250416136949364763643567120528794940315957096036293006981834837647913757096,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Another command (pid=667622) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=667212) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=665672) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"14.chip_sw_uart_rand_baudrate.53077045290142985232503159010898621363302217563635496860346568325019710867584","seed":53077045290142985232503159010898621363302217563635496860346568325019710867584,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.387s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"14.chip_sw_lc_ctrl_transition.16329516883371394508094536359130903299031697647743088951288611730990748356670","seed":16329516883371394508094536359130903299031697647743088951288611730990748356670,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 17.531s, Critical Path: 0.05s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"14.chip_sw_alert_handler_lpg_sleep_mode_alerts.65736413358107573727714486136652941225632329878215722072291986198678797059430","seed":65736413358107573727714486136652941225632329878215722072291986198678797059430,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=649947) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"15.chip_sw_uart_rand_baudrate.102822570989689266829259407086932451493305110693155172800355511437454618218497","seed":102822570989689266829259407086932451493305110693155172800355511437454618218497,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.196s, Critical Path: 0.10s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"15.chip_sw_alert_handler_lpg_sleep_mode_alerts.86004763367520685463453450371937442993781859159437704658212380930008674013984","seed":86004763367520685463453450371937442993781859159437704658212380930008674013984,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Another command (pid=666917) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=664030) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=662535) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"16.chip_sw_uart_rand_baudrate.15446000560785873601844249764845048384364725193326397556106125070713099516344","seed":15446000560785873601844249764845048384364725193326397556106125070713099516344,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 6.014s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"16.chip_sw_alert_handler_lpg_sleep_mode_alerts.104837987908566815655706095982646404840922300105867120047472485755565695923979","seed":104837987908566815655706095982646404840922300105867120047472485755565695923979,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Another command (pid=669556) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=672449) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=676034) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"17.chip_sw_uart_rand_baudrate.24594231404683659848790345156346917075648487602361897600661069734339368609414","seed":24594231404683659848790345156346917075648487602361897600661069734339368609414,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 8.983s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"17.chip_sw_alert_handler_lpg_sleep_mode_alerts.43519134669890366260246779959875287386051497768102104481151746622367028706874","seed":43519134669890366260246779959875287386051497768102104481151746622367028706874,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Another command (pid=672488) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=672745) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=680378) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"18.chip_sw_uart_rand_baudrate.105181194404507365038741818431423795560475314988421289090233320403042894897579","seed":105181194404507365038741818431423795560475314988421289090233320403042894897579,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.442s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"18.chip_sw_alert_handler_lpg_sleep_mode_alerts.67375239811462726743221662306827472324736374246402274073775619727145657128610","seed":67375239811462726743221662306827472324736374246402274073775619727145657128610,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Another command (pid=672745) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=680378) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=675350) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"19.chip_sw_uart_rand_baudrate.96308659632586169852938161113605167289245865152656491975319874500079039499235","seed":96308659632586169852938161113605167289245865152656491975319874500079039499235,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.119s, Critical Path: 0.00s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"19.chip_sw_alert_handler_lpg_sleep_mode_alerts.93378387778959855107857098140350196492552715140186534671365942318539126250563","seed":93378387778959855107857098140350196492552715140186534671365942318539126250563,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=690687) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3127915703184008832952176732573158471625584842450720163419382887870167304666","seed":3127915703184008832952176732573158471625584842450720163419382887870167304666,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Another command (pid=697139) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=695159) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=696975) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"21.chip_sw_alert_handler_lpg_sleep_mode_alerts.50499824003917965603902985973701646791399809492550308884443478576551584574480","seed":50499824003917965603902985973701646791399809492550308884443478576551584574480,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Another command (pid=707761) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=707197) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=709644) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"22.chip_sw_alert_handler_lpg_sleep_mode_alerts.40458308374606147105764283005318861501185469192225479310804249533950266562662","seed":40458308374606147105764283005318861501185469192225479310804249533950266562662,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Another command (pid=704097) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=707033) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=705952) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"23.chip_sw_alert_handler_lpg_sleep_mode_alerts.79250771920850132167999860620746413537802929937644486515935693254364179471133","seed":79250771920850132167999860620746413537802929937644486515935693254364179471133,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Another command (pid=710374) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=712177) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=711024) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"24.chip_sw_alert_handler_lpg_sleep_mode_alerts.29572297157721661750748854658482953212515157369965551434833790937196946209499","seed":29572297157721661750748854658482953212515157369965551434833790937196946209499,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=720456) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"25.chip_sw_alert_handler_lpg_sleep_mode_alerts.34718595526716610066899735861639077213009179185795228513767331668279018453494","seed":34718595526716610066899735861639077213009179185795228513767331668279018453494,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"26.chip_sw_alert_handler_lpg_sleep_mode_alerts.104316967990826644405092580683770023056520931631304805506973147586368715497912","seed":104316967990826644405092580683770023056520931631304805506973147586368715497912,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"27.chip_sw_alert_handler_lpg_sleep_mode_alerts.74927144818706636355006121697720809531133678709667084743612949195495119751630","seed":74927144818706636355006121697720809531133678709667084743612949195495119751630,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=745215) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"28.chip_sw_alert_handler_lpg_sleep_mode_alerts.18361398133635959476222355022436463991360804652577555969975561494628350104942","seed":18361398133635959476222355022436463991360804652577555969975561494628350104942,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=747330) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"29.chip_sw_alert_handler_lpg_sleep_mode_alerts.100105180228862354712270703622625416029116508568255839995674077147802311773116","seed":100105180228862354712270703622625416029116508568255839995674077147802311773116,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"30.chip_sw_alert_handler_lpg_sleep_mode_alerts.77939321791869898117122150790871893991069287812868121454779373578550131554067","seed":77939321791869898117122150790871893991069287812868121454779373578550131554067,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=758020) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"31.chip_sw_alert_handler_lpg_sleep_mode_alerts.98944799360287934897181586571250144807975355416772846454103883429989790711073","seed":98944799360287934897181586571250144807975355416772846454103883429989790711073,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=763335) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"32.chip_sw_alert_handler_lpg_sleep_mode_alerts.107582605185271053307510184068107472844580387179289095094418630769684556508171","seed":107582605185271053307510184068107472844580387179289095094418630769684556508171,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=764700) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"33.chip_sw_alert_handler_lpg_sleep_mode_alerts.80676571546753772635378950930802509411350317655826154908108706047012983041748","seed":80676571546753772635378950930802509411350317655826154908108706047012983041748,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=769025) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"34.chip_sw_alert_handler_lpg_sleep_mode_alerts.104215036377115517736976291293577953588845479554828778870764098355393192571809","seed":104215036377115517736976291293577953588845479554828778870764098355393192571809,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"35.chip_sw_alert_handler_lpg_sleep_mode_alerts.37810451034116025974698013618027409238694096553066719488471216909293105595948","seed":37810451034116025974698013618027409238694096553066719488471216909293105595948,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=781240) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"36.chip_sw_alert_handler_lpg_sleep_mode_alerts.112602196147576963559180361113752315344401031278234200848775270758248115562895","seed":112602196147576963559180361113752315344401031278234200848775270758248115562895,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=789531) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"37.chip_sw_alert_handler_lpg_sleep_mode_alerts.10111521916783904035700549290374268233350258694821439380274221721210391979276","seed":10111521916783904035700549290374268233350258694821439380274221721210391979276,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"38.chip_sw_alert_handler_lpg_sleep_mode_alerts.90709413147296187911968574061473826004061808207885718552946678508966355291651","seed":90709413147296187911968574061473826004061808207885718552946678508966355291651,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Another command (pid=796732) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=797290) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=798321) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"39.chip_sw_alert_handler_lpg_sleep_mode_alerts.35047239694777426306660328591812275233381262463574046726215220079418896312519","seed":35047239694777426306660328591812275233381262463574046726215220079418896312519,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=802308) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=802876) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"40.chip_sw_alert_handler_lpg_sleep_mode_alerts.9972424052945489930359141920706845301699643207442798327759253885729935562592","seed":9972424052945489930359141920706845301699643207442798327759253885729935562592,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=810817) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"41.chip_sw_alert_handler_lpg_sleep_mode_alerts.29572246796096615589442351968827660106888769708275787752266989368270389188804","seed":29572246796096615589442351968827660106888769708275787752266989368270389188804,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=815769) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"42.chip_sw_alert_handler_lpg_sleep_mode_alerts.30828377526853329163624451161900681021300202769951940732534394676956676818808","seed":30828377526853329163624451161900681021300202769951940732534394676956676818808,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=819648) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"43.chip_sw_alert_handler_lpg_sleep_mode_alerts.19886200996731953482616995432784593377030467956419299743415324827785137034142","seed":19886200996731953482616995432784593377030467956419299743415324827785137034142,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"44.chip_sw_alert_handler_lpg_sleep_mode_alerts.83303867472981759395699244772840343654323426370480159747052362769913838680214","seed":83303867472981759395699244772840343654323426370480159747052362769913838680214,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=830251) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"45.chip_sw_alert_handler_lpg_sleep_mode_alerts.76454526133250507197234397758376483870123934560777135151218834488171508158958","seed":76454526133250507197234397758376483870123934560777135151218834488171508158958,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"46.chip_sw_alert_handler_lpg_sleep_mode_alerts.90540085135608027492992270771287732510778345511996379479217442304140122049717","seed":90540085135608027492992270771287732510778345511996379479217442304140122049717,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=843139) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"47.chip_sw_alert_handler_lpg_sleep_mode_alerts.74952488536981533388332268626725551809816685360966100460698527755818289106067","seed":74952488536981533388332268626725551809816685360966100460698527755818289106067,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=848017) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"48.chip_sw_alert_handler_lpg_sleep_mode_alerts.79502025183778717889307805924969965615052857742440847056361188262607225362410","seed":79502025183778717889307805924969965615052857742440847056361188262607225362410,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=851601) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"49.chip_sw_alert_handler_lpg_sleep_mode_alerts.110237007951965958166214492089208088734655501361459716502437824987800595205960","seed":110237007951965958166214492089208088734655501361459716502437824987800595205960,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"50.chip_sw_alert_handler_lpg_sleep_mode_alerts.10346087613330690512705530985373440994614315230664884371952011440463063207781","seed":10346087613330690512705530985373440994614315230664884371952011440463063207781,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"51.chip_sw_alert_handler_lpg_sleep_mode_alerts.65250573203453463131260871063253355704984879777111316949301782232734382605898","seed":65250573203453463131260871063253355704984879777111316949301782232734382605898,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=867645) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"52.chip_sw_alert_handler_lpg_sleep_mode_alerts.70849803118429072367311706188010984403232229123727515902720068027695778235691","seed":70849803118429072367311706188010984403232229123727515902720068027695778235691,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=873633) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"53.chip_sw_alert_handler_lpg_sleep_mode_alerts.79609970927612031300102659131568213045773704154980427400695581702309697359663","seed":79609970927612031300102659131568213045773704154980427400695581702309697359663,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=877514) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"54.chip_sw_alert_handler_lpg_sleep_mode_alerts.104686707640221942183877643843249329841088133708843068689437147927031160135469","seed":104686707640221942183877643843249329841088133708843068689437147927031160135469,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"55.chip_sw_alert_handler_lpg_sleep_mode_alerts.66805466250341988369610829057238104317311649932928334158571129108487414732324","seed":66805466250341988369610829057238104317311649932928334158571129108487414732324,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"56.chip_sw_alert_handler_lpg_sleep_mode_alerts.77236577536733969771507324263817459175147484428260469304257205730274455207039","seed":77236577536733969771507324263817459175147484428260469304257205730274455207039,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=894599) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"57.chip_sw_alert_handler_lpg_sleep_mode_alerts.49252256020787150941748090445447723669474041348171975637916122743924588623417","seed":49252256020787150941748090445447723669474041348171975637916122743924588623417,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"58.chip_sw_alert_handler_lpg_sleep_mode_alerts.33629992784355798090751583545121837032255407017728045317728761608569866999829","seed":33629992784355798090751583545121837032255407017728045317728761608569866999829,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"59.chip_sw_alert_handler_lpg_sleep_mode_alerts.79865711227665807346681272575632973107005793951011840365870569369031001405479","seed":79865711227665807346681272575632973107005793951011840365870569369031001405479,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=908218) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"60.chip_sw_alert_handler_lpg_sleep_mode_alerts.53350222832075804000594308744873389106055759177476576141425919111938149878461","seed":53350222832075804000594308744873389106055759177476576141425919111938149878461,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"61.chip_sw_alert_handler_lpg_sleep_mode_alerts.87049101510343286036550844860772112179871087631415240392119791222340813807709","seed":87049101510343286036550844860772112179871087631415240392119791222340813807709,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"62.chip_sw_alert_handler_lpg_sleep_mode_alerts.76996952865632356722356719052650867209832806725386341244981218387771552010762","seed":76996952865632356722356719052650867209832806725386341244981218387771552010762,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=926484) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"63.chip_sw_alert_handler_lpg_sleep_mode_alerts.50841725033970269694752333765686782687993943319341654475151937488582565865978","seed":50841725033970269694752333765686782687993943319341654475151937488582565865978,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"64.chip_sw_alert_handler_lpg_sleep_mode_alerts.48767515381228323459064472150386803615163539667433270479418261243924774039455","seed":48767515381228323459064472150386803615163539667433270479418261243924774039455,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"65.chip_sw_alert_handler_lpg_sleep_mode_alerts.84125066761022430241324522833406522292824937442199500606188935481054479302473","seed":84125066761022430241324522833406522292824937442199500606188935481054479302473,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"66.chip_sw_alert_handler_lpg_sleep_mode_alerts.7273641817663636668177273351896356942815453568831964689227906479910557770841","seed":7273641817663636668177273351896356942815453568831964689227906479910557770841,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"67.chip_sw_alert_handler_lpg_sleep_mode_alerts.15244357016201866785191818458218772121362129699042123239294072947240898501449","seed":15244357016201866785191818458218772121362129699042123239294072947240898501449,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"68.chip_sw_alert_handler_lpg_sleep_mode_alerts.67229559751882298774159368901449832751502823322894678361136149511623162069228","seed":67229559751882298774159368901449832751502823322894678361136149511623162069228,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"69.chip_sw_alert_handler_lpg_sleep_mode_alerts.28951235570854141386333825914179152121754165471510789673856762338525627726965","seed":28951235570854141386333825914179152121754165471510789673856762338525627726965,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"70.chip_sw_alert_handler_lpg_sleep_mode_alerts.24245368068111285203390349309085172713553914596658368197977715715580088114736","seed":24245368068111285203390349309085172713553914596658368197977715715580088114736,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"71.chip_sw_alert_handler_lpg_sleep_mode_alerts.98679789152943771501509701056939986621591573756510190157992638496542028962303","seed":98679789152943771501509701056939986621591573756510190157992638496542028962303,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"72.chip_sw_alert_handler_lpg_sleep_mode_alerts.78689018430211891662480866999267577365388672275946466510222008133903809227276","seed":78689018430211891662480866999267577365388672275946466510222008133903809227276,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=982617) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"73.chip_sw_alert_handler_lpg_sleep_mode_alerts.51353979008572726695049889328022947467424999807548765702143390857493356208517","seed":51353979008572726695049889328022947467424999807548765702143390857493356208517,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"74.chip_sw_alert_handler_lpg_sleep_mode_alerts.34120990403080266323743813763074000905771727201430701039649456407195748851675","seed":34120990403080266323743813763074000905771727201430701039649456407195748851675,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1319648767558189862086530467208860940290973910003538609960219018524362199159","seed":1319648767558189862086530467208860940290973910003538609960219018524362199159,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"76.chip_sw_alert_handler_lpg_sleep_mode_alerts.104943338495599300760170756022467715913479644309879509240014466021640359303456","seed":104943338495599300760170756022467715913479644309879509240014466021640359303456,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=1000408) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"77.chip_sw_alert_handler_lpg_sleep_mode_alerts.42121962651696858626944064956657612479801100995858055401258371313156095545836","seed":42121962651696858626944064956657612479801100995858055401258371313156095545836,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=1006519) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"78.chip_sw_alert_handler_lpg_sleep_mode_alerts.95267572133861004697481739073802369888315975130233249837880222691395296262170","seed":95267572133861004697481739073802369888315975130233249837880222691395296262170,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"79.chip_sw_alert_handler_lpg_sleep_mode_alerts.14687806938416070912429428756597571547525942660679811145635155781001326177447","seed":14687806938416070912429428756597571547525942660679811145635155781001326177447,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"80.chip_sw_alert_handler_lpg_sleep_mode_alerts.31071191582679013219389124121621615968075059873189551640039694111729710318774","seed":31071191582679013219389124121621615968075059873189551640039694111729710318774,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"81.chip_sw_alert_handler_lpg_sleep_mode_alerts.7479540495225468258296928273794363508927477630514833675647723322768682885912","seed":7479540495225468258296928273794363508927477630514833675647723322768682885912,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=1030172) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"82.chip_sw_alert_handler_lpg_sleep_mode_alerts.72132681519329652312214820322363370091790125269332258795723152734460569026352","seed":72132681519329652312214820322363370091790125269332258795723152734460569026352,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=1031459) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"83.chip_sw_alert_handler_lpg_sleep_mode_alerts.83826387741225554598609540834778011893820963107923626316534316144237984119806","seed":83826387741225554598609540834778011893820963107923626316534316144237984119806,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=1039109) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"84.chip_sw_alert_handler_lpg_sleep_mode_alerts.89596953653845451215260819007946299502411717032218609226201736242525706972952","seed":89596953653845451215260819007946299502411717032218609226201736242525706972952,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"85.chip_sw_alert_handler_lpg_sleep_mode_alerts.32574556017761575984898138124639679827879769858460080110149561809306466417928","seed":32574556017761575984898138124639679827879769858460080110149561809306466417928,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=1049864) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"86.chip_sw_alert_handler_lpg_sleep_mode_alerts.28546565485095680618447922230409145191312445053219539345305533630670133689910","seed":28546565485095680618447922230409145191312445053219539345305533630670133689910,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Waiting for it to complete...\n","Another command (pid=1053327) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","Another command (pid=1053567) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"87.chip_sw_alert_handler_lpg_sleep_mode_alerts.68075786178484869503915452045669640171663451137255939784994686310024119948708","seed":68075786178484869503915452045669640171663451137255939784994686310024119948708,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=1057026) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3634950379930810625023609130035314744907687826851241528510576611827791583108","seed":3634950379930810625023609130035314744907687826851241528510576611827791583108,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=1066131) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"89.chip_sw_alert_handler_lpg_sleep_mode_alerts.18293416676614465857567820209608849708789454148831604696743564164774974462424","seed":18293416676614465857567820209608849708789454148831604696743564164774974462424,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=1070006) is running. Waiting for it to complete on the server (server_pid=3171772)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]}],"UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs":[{"name":"chip_sw_all_escalation_resets","qual_name":"0.chip_sw_all_escalation_resets.56464933244421516845326257380953327128499772039536523944837465066602915478958","seed":56464933244421516845326257380953327128499772039536523944837465066602915478958,"line":313,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_FATAL @  10.100001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs\n","UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"21.chip_sw_all_escalation_resets.74602888075009964944736106072454575050148202101545960915960267261825984288918","seed":74602888075009964944736106072454575050148202101545960915960267261825984288918,"line":313,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_FATAL @  10.360001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs\n","UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"22.chip_sw_all_escalation_resets.91217041769203869236967584264618623389796611296668171108136320661952321908549","seed":91217041769203869236967584264618623389796611296668171108136320661952321908549,"line":313,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_FATAL @  10.260001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs\n","UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"36.chip_sw_all_escalation_resets.101576893981068377582168521742268787778060302966007573961257590491026723209493","seed":101576893981068377582168521742268787778060302966007573961257590491026723209493,"line":313,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/36.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_FATAL @  10.400001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs\n","UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"54.chip_sw_all_escalation_resets.98403955072729800794333196714714104701140591628935809835413511084106127961547","seed":98403955072729800794333196714714104701140591628935809835413511084106127961547,"line":313,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/54.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_FATAL @  10.280001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs\n","UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"68.chip_sw_all_escalation_resets.13669342976868189996756568925444461943583804070007726825251402681017914236723","seed":13669342976868189996756568925444461943583804070007726825251402681017914236723,"line":313,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/68.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_FATAL @  10.400001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs\n","UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"91.chip_sw_all_escalation_resets.14005603648463292070833892951160834096025166351498582918039830373347114917202","seed":14005603648463292070833892951160834096025166351498582918039830373347114917202,"line":313,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/91.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_FATAL @  10.380001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs\n","UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size":[{"name":"chip_sw_rstmgr_rst_cnsty_escalation","qual_name":"0.chip_sw_rstmgr_rst_cnsty_escalation.21044689399445078350458201506903593498852375493166058465476060705739275907045","seed":21044689399445078350458201506903593498852375493166058465476060705739275907045,"line":348,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log","log_context":["UVM_ERROR @ 950.705000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.705000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"1.chip_sw_all_escalation_resets.102544745561621990089540450520514023816252887615839892563733653815127279081620","seed":102544745561621990089540450520514023816252887615839892563733653815127279081620,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.583000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.583000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rstmgr_rst_cnsty_escalation","qual_name":"1.chip_sw_rstmgr_rst_cnsty_escalation.93024782843273800226150832376029975584924052028099549689031122631701271688715","seed":93024782843273800226150832376029975584924052028099549689031122631701271688715,"line":348,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log","log_context":["UVM_ERROR @ 950.760000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.760000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"2.chip_sw_all_escalation_resets.90008086374782794473452640558105591692575204996364265298632689094372458757308","seed":90008086374782794473452640558105591692575204996364265298632689094372458757308,"line":349,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.571000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.571000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rstmgr_rst_cnsty_escalation","qual_name":"2.chip_sw_rstmgr_rst_cnsty_escalation.107307187455361210512877590305052580585251553695618706672264642562828769480295","seed":107307187455361210512877590305052580585251553695618706672264642562828769480295,"line":348,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log","log_context":["UVM_ERROR @ 950.674000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.674000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"3.chip_sw_all_escalation_resets.49019741965751819611693624829872216829478370552083947870578559517277333929418","seed":49019741965751819611693624829872216829478370552083947870578559517277333929418,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.587000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.587000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"4.chip_sw_all_escalation_resets.53989118834930676044453356072711218745305527306217643412628270732758122630578","seed":53989118834930676044453356072711218745305527306217643412628270732758122630578,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.635000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.635000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"5.chip_sw_all_escalation_resets.103313599030270024310184502168281829612241537558771824592293819562639460508033","seed":103313599030270024310184502168281829612241537558771824592293819562639460508033,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.586000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.586000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"6.chip_sw_all_escalation_resets.101116013565006165338577182841134661262388278201548473330730222858622567118578","seed":101116013565006165338577182841134661262388278201548473330730222858622567118578,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.713000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.713000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"7.chip_sw_all_escalation_resets.75889446513926912462382569340458044764518017230184661702043862245926019662502","seed":75889446513926912462382569340458044764518017230184661702043862245926019662502,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.669000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.669000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"8.chip_sw_all_escalation_resets.70755646368503903575621945454322087304656121686590105710715019440432125112798","seed":70755646368503903575621945454322087304656121686590105710715019440432125112798,"line":349,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.653000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.653000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"9.chip_sw_all_escalation_resets.88280023503184472153525235212863434539893818082003293332802074321838612534580","seed":88280023503184472153525235212863434539893818082003293332802074321838612534580,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.596000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.596000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"10.chip_sw_all_escalation_resets.8353328095302199562325960154448942469281214620567042891115388271364606348816","seed":8353328095302199562325960154448942469281214620567042891115388271364606348816,"line":352,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.854000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.854000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"11.chip_sw_all_escalation_resets.35468846980666335693202100017651716941903869623308691084017326791914882792197","seed":35468846980666335693202100017651716941903869623308691084017326791914882792197,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.817000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.817000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"12.chip_sw_all_escalation_resets.103818761068164763334770889711663652523157245603687770176346339736122021484890","seed":103818761068164763334770889711663652523157245603687770176346339736122021484890,"line":352,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/12.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.760000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.760000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"13.chip_sw_all_escalation_resets.34960253928066452040110846077729158880903792570362061820237371494474372935290","seed":34960253928066452040110846077729158880903792570362061820237371494474372935290,"line":349,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.667000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.667000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"14.chip_sw_all_escalation_resets.77363571325161516144324616505246144814441365403949729214013396012448298419542","seed":77363571325161516144324616505246144814441365403949729214013396012448298419542,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.676000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.676000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"15.chip_sw_all_escalation_resets.41517280057644374141627493209983422812402717959811901828366634604191813749021","seed":41517280057644374141627493209983422812402717959811901828366634604191813749021,"line":352,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.683000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.683000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"16.chip_sw_all_escalation_resets.94776281435330339857024688124533123119055871845545168176694884598824911186848","seed":94776281435330339857024688124533123119055871845545168176694884598824911186848,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.582000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.582000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"17.chip_sw_all_escalation_resets.41093510001397492333518721301723771354126182777475955945191931827301958029397","seed":41093510001397492333518721301723771354126182777475955945191931827301958029397,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.705000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.705000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"18.chip_sw_all_escalation_resets.51085865759282753647410379047229957319816219856230823797521292558887095486700","seed":51085865759282753647410379047229957319816219856230823797521292558887095486700,"line":352,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/18.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.822000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.822000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"19.chip_sw_all_escalation_resets.102204306152660215913729709813199068647174254660155444575647054881172941409548","seed":102204306152660215913729709813199068647174254660155444575647054881172941409548,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.692000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.692000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"23.chip_sw_all_escalation_resets.32312832631909535562965784129453468573477297806113414518812032752368078375100","seed":32312832631909535562965784129453468573477297806113414518812032752368078375100,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/23.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.684000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.684000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"24.chip_sw_all_escalation_resets.2911291524497750284851343477068643548703610544226705175655379104647945819636","seed":2911291524497750284851343477068643548703610544226705175655379104647945819636,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/24.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.639000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.639000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"25.chip_sw_all_escalation_resets.104606180443692890361596349963978173858304816020198191716441133216734046905740","seed":104606180443692890361596349963978173858304816020198191716441133216734046905740,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.619000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.619000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"26.chip_sw_all_escalation_resets.60514539389441975547791174081059453146847179870439705577049762577832635003020","seed":60514539389441975547791174081059453146847179870439705577049762577832635003020,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.543000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.543000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"27.chip_sw_all_escalation_resets.81953026691663389933989343446691496648584861510355185176034494650673093782851","seed":81953026691663389933989343446691496648584861510355185176034494650673093782851,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.779000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.779000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"28.chip_sw_all_escalation_resets.50218820848771585096695178846344859679901505560370459009870264132568488011484","seed":50218820848771585096695178846344859679901505560370459009870264132568488011484,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/28.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.587000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.587000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"29.chip_sw_all_escalation_resets.101595121540003023151330384761653299110842273449180328235910416060078097797895","seed":101595121540003023151330384761653299110842273449180328235910416060078097797895,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.651000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.651000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"30.chip_sw_all_escalation_resets.27505715921492941553841090506319564879324059728114790664036470567697500087600","seed":27505715921492941553841090506319564879324059728114790664036470567697500087600,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 951.126000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 951.126000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"31.chip_sw_all_escalation_resets.9065393265393145796681532784030217542232342324654982361957490283295978697385","seed":9065393265393145796681532784030217542232342324654982361957490283295978697385,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.681000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.681000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"32.chip_sw_all_escalation_resets.25772655997301600130098534281612455966400312946992131957278887807393278619455","seed":25772655997301600130098534281612455966400312946992131957278887807393278619455,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.681000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.681000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"33.chip_sw_all_escalation_resets.44367132552259243353428563559987999475776708573940982892607683909975566769347","seed":44367132552259243353428563559987999475776708573940982892607683909975566769347,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/33.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.741000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.741000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"35.chip_sw_all_escalation_resets.47956825756910622062891441436056331295857063977549006708578375190494051861972","seed":47956825756910622062891441436056331295857063977549006708578375190494051861972,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/35.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.612000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.612000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"37.chip_sw_all_escalation_resets.88556121660180867553626358137955134378137488502942934115638980546395383415681","seed":88556121660180867553626358137955134378137488502942934115638980546395383415681,"line":352,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.727000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.727000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"39.chip_sw_all_escalation_resets.67838210838406045950840594996015837648172565377496981494087099196117081629330","seed":67838210838406045950840594996015837648172565377496981494087099196117081629330,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.523000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.523000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"40.chip_sw_all_escalation_resets.11801193830235910662217376547025333345488813701438619835681736792093486520765","seed":11801193830235910662217376547025333345488813701438619835681736792093486520765,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.627000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.627000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"41.chip_sw_all_escalation_resets.65032427467058470938561352180353887502026492192780152251353518470769616886281","seed":65032427467058470938561352180353887502026492192780152251353518470769616886281,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/41.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.625000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.625000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"42.chip_sw_all_escalation_resets.160041079877475956535338341425117130409809684223089051959615558505472234958","seed":160041079877475956535338341425117130409809684223089051959615558505472234958,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/42.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.673000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.673000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"43.chip_sw_all_escalation_resets.3129698239315346607761258443308684772780107393390806896604055280058371612479","seed":3129698239315346607761258443308684772780107393390806896604055280058371612479,"line":352,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/43.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.790000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.790000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"44.chip_sw_all_escalation_resets.66693887793195728626892761048551091927215011026495956671067381670687711178512","seed":66693887793195728626892761048551091927215011026495956671067381670687711178512,"line":349,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.725000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.725000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"45.chip_sw_all_escalation_resets.96002727239455035350445155143680252597088671454385624267102596346073320038098","seed":96002727239455035350445155143680252597088671454385624267102596346073320038098,"line":349,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/45.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.725000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.725000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"48.chip_sw_all_escalation_resets.97536442595185760289295567427440949978911888408606378367462942328452982864981","seed":97536442595185760289295567427440949978911888408606378367462942328452982864981,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.531000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.531000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"49.chip_sw_all_escalation_resets.42030260982357264010307585123058042415595447850708989766134910307816952120575","seed":42030260982357264010307585123058042415595447850708989766134910307816952120575,"line":349,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.556000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.556000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"50.chip_sw_all_escalation_resets.23758889738069888295677835892146964899279238840374765821535482693001842264616","seed":23758889738069888295677835892146964899279238840374765821535482693001842264616,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/50.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.727000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.727000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"51.chip_sw_all_escalation_resets.27723401579236607312028877943145954217124047779836473463489509769168694607231","seed":27723401579236607312028877943145954217124047779836473463489509769168694607231,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/51.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.720000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.720000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"53.chip_sw_all_escalation_resets.70388398751717107096628169696628380670904843349674966179631052986449898164536","seed":70388398751717107096628169696628380670904843349674966179631052986449898164536,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/53.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.615000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.615000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"55.chip_sw_all_escalation_resets.32710455497270102893150354097185577327999515064618537312701866574986159927745","seed":32710455497270102893150354097185577327999515064618537312701866574986159927745,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/55.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.801000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.801000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"56.chip_sw_all_escalation_resets.88496824878367118257127378038630339888790396926497647922412965508773399704664","seed":88496824878367118257127378038630339888790396926497647922412965508773399704664,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/56.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.673000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.673000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"59.chip_sw_all_escalation_resets.8291499294487147779874078265524923097681928736814231730865605079165122899773","seed":8291499294487147779874078265524923097681928736814231730865605079165122899773,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/59.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.662000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.662000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"60.chip_sw_all_escalation_resets.109058406198028448426996326803616086369558652029092689121953727351726425971800","seed":109058406198028448426996326803616086369558652029092689121953727351726425971800,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/60.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.669000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.669000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"61.chip_sw_all_escalation_resets.35254165816138071114503558716954294990157347801625157386142608762206644442067","seed":35254165816138071114503558716954294990157347801625157386142608762206644442067,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/61.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.720000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.720000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"62.chip_sw_all_escalation_resets.42947034714961516619314459684968233088381319790706472086812265798205706360341","seed":42947034714961516619314459684968233088381319790706472086812265798205706360341,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/62.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.660000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.660000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"63.chip_sw_all_escalation_resets.16614842220012850429186527702336840540576692280801917817418144161336462485447","seed":16614842220012850429186527702336840540576692280801917817418144161336462485447,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/63.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.669000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.669000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"64.chip_sw_all_escalation_resets.61075743420107470330662900712310375130954919490496289289722560830462101695060","seed":61075743420107470330662900712310375130954919490496289289722560830462101695060,"line":349,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/64.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.624000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.624000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"65.chip_sw_all_escalation_resets.108504595389332447430252630575248985855865134339340243353989286567552783102452","seed":108504595389332447430252630575248985855865134339340243353989286567552783102452,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/65.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.677000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.677000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"66.chip_sw_all_escalation_resets.33411766427068120804887894910088041638292697246519310555724218631488781240584","seed":33411766427068120804887894910088041638292697246519310555724218631488781240584,"line":349,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/66.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.707000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.707000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"67.chip_sw_all_escalation_resets.62698258982168406071783388171299516471766698900175815039861261060179770799864","seed":62698258982168406071783388171299516471766698900175815039861261060179770799864,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/67.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.729000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.729000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"69.chip_sw_all_escalation_resets.20134640812547330187039634018515311203504519694832108485510616202207407846369","seed":20134640812547330187039634018515311203504519694832108485510616202207407846369,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/69.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.684000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.684000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"70.chip_sw_all_escalation_resets.82030654687987644350851509020626874241641947801520753423138516416057302406952","seed":82030654687987644350851509020626874241641947801520753423138516416057302406952,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/70.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.670000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.670000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"71.chip_sw_all_escalation_resets.64933987664266434948506488725497263911644141743446365737692596502641898702000","seed":64933987664266434948506488725497263911644141743446365737692596502641898702000,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/71.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.706000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.706000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"72.chip_sw_all_escalation_resets.15764069523048540356870873812703654510201114266108222028680908994060251723085","seed":15764069523048540356870873812703654510201114266108222028680908994060251723085,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/72.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.707000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.707000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"73.chip_sw_all_escalation_resets.47020704009476442959489105940275384492538969847367722758108783405652966357523","seed":47020704009476442959489105940275384492538969847367722758108783405652966357523,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/73.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.809000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.809000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"74.chip_sw_all_escalation_resets.93465655420100808620358920721139521511148138716206271239661096853867651024493","seed":93465655420100808620358920721139521511148138716206271239661096853867651024493,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/74.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.578000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.578000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"77.chip_sw_all_escalation_resets.102667547564909389840072161302777232669806073823909694547440534063028407851356","seed":102667547564909389840072161302777232669806073823909694547440534063028407851356,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/77.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.661000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.661000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"78.chip_sw_all_escalation_resets.18381338859060214508040776579058713375121649858311704202313381996795245211903","seed":18381338859060214508040776579058713375121649858311704202313381996795245211903,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/78.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.663000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.663000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"79.chip_sw_all_escalation_resets.11135340034409348394525187940877709910066882261486840990800648945606828289707","seed":11135340034409348394525187940877709910066882261486840990800648945606828289707,"line":349,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/79.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.619000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.619000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"80.chip_sw_all_escalation_resets.99769599829349149394910165329703055265894029875237478868697951252451836610524","seed":99769599829349149394910165329703055265894029875237478868697951252451836610524,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/80.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.403000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.403000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"81.chip_sw_all_escalation_resets.61229933438460366136213631901191273289609895099990551018149189534126269170891","seed":61229933438460366136213631901191273289609895099990551018149189534126269170891,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/81.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.674000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.674000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"82.chip_sw_all_escalation_resets.56276947979637566374416919977713082065099109032955675794865540550122613888789","seed":56276947979637566374416919977713082065099109032955675794865540550122613888789,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/82.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.692000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.692000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"83.chip_sw_all_escalation_resets.54694660113285392835493555026632041730963942148675966261006743689585755295867","seed":54694660113285392835493555026632041730963942148675966261006743689585755295867,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/83.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.451000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.451000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"84.chip_sw_all_escalation_resets.90107483813762557029672906437440208268188803440242976815042618418676178750831","seed":90107483813762557029672906437440208268188803440242976815042618418676178750831,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/84.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.756000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.756000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"85.chip_sw_all_escalation_resets.105509332602424292654194435885061311689271227779592733335345035159560663442750","seed":105509332602424292654194435885061311689271227779592733335345035159560663442750,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/85.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.612000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.612000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"86.chip_sw_all_escalation_resets.71209164474634809457276024919412888918196373153315988272381518075423318130020","seed":71209164474634809457276024919412888918196373153315988272381518075423318130020,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/86.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.532000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.532000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"87.chip_sw_all_escalation_resets.20452955323923785790932040646489708015775769924953086501342159107705830313193","seed":20452955323923785790932040646489708015775769924953086501342159107705830313193,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/87.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.776000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.776000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"88.chip_sw_all_escalation_resets.29598713739329418255211909080520753613693097481401438836315289993586484920777","seed":29598713739329418255211909080520753613693097481401438836315289993586484920777,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/88.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.800000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.800000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"89.chip_sw_all_escalation_resets.17848060692475262361886552848357867117564354408592684663769766105951911818400","seed":17848060692475262361886552848357867117564354408592684663769766105951911818400,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/89.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.633000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.633000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"90.chip_sw_all_escalation_resets.55124832862216330564194145709914533298065977063206755440194684369321242754017","seed":55124832862216330564194145709914533298065977063206755440194684369321242754017,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/90.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.645000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.645000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"93.chip_sw_all_escalation_resets.84492763928332672376938186958867699420163748769578510964646485608991408078806","seed":84492763928332672376938186958867699420163748769578510964646485608991408078806,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/93.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.637000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.637000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"94.chip_sw_all_escalation_resets.33034482516727328272990229555873347581118776749628333397021791028630020652652","seed":33034482516727328272990229555873347581118776749628333397021791028630020652652,"line":352,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/94.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.723000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.723000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"95.chip_sw_all_escalation_resets.111198566379451735272042129219991846538528370157561848485930321310984472469462","seed":111198566379451735272042129219991846538528370157561848485930321310984472469462,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/95.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.717000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.717000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"96.chip_sw_all_escalation_resets.61488412434224268148494076936177440583010838314455398333895503468782897388813","seed":61488412434224268148494076936177440583010838314455398333895503468782897388813,"line":355,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/96.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.609000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.609000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"97.chip_sw_all_escalation_resets.59067609527673930236812456306754461217474580047216466086509465735940588397770","seed":59067609527673930236812456306754461217474580047216466086509465735940588397770,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/97.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.602000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.602000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"98.chip_sw_all_escalation_resets.58969663650621746139350374637794469194952869082849141708769880797781075745003","seed":58969663650621746139350374637794469194952869082849141708769880797781075745003,"line":350,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/98.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.653000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.653000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"99.chip_sw_all_escalation_resets.108909268814791426381597482455393442439349821324698987123332805724068355831439","seed":108909268814791426381597482455393442439349821324698987123332805724068355831439,"line":349,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/99.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 950.685000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 950.685000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty":[{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"0.chip_sw_spi_device_pass_through_collision.36742123117060479949378116210052970227665897732184118569079679618005390992542","seed":36742123117060479949378116210052970227665897732184118569079679618005390992542,"line":332,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_ERROR @ 199.209000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty\n","UVM_INFO @ 199.209000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"1.chip_sw_spi_device_pass_through_collision.305766880371957930899032838058078083181318702556972218393082665675937022699","seed":305766880371957930899032838058078083181318702556972218393082665675937022699,"line":332,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_ERROR @ 289.761000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty\n","UVM_INFO @ 289.761000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"2.chip_sw_spi_device_pass_through_collision.44512355756391815786233441979847705947928929971242880395180543630562889863715","seed":44512355756391815786233441979847705947928929971242880395180543630562889863715,"line":332,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_ERROR @ 267.996000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty\n","UVM_INFO @ 267.996000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'":[{"name":"chip_sw_otp_ctrl_escalation","qual_name":"0.chip_sw_otp_ctrl_escalation.77057877470265886574590561738171494664993627585011277623589517104964796453118","seed":77057877470265886574590561738171494664993627585011277623589517104964796453118,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log","log_context":["\tOffending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'\n","UVM_ERROR @ 180.544000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 180.544000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"20.chip_sw_all_escalation_resets.44699533887687979198381722748669056919941535360475652077878960719233936222871","seed":44699533887687979198381722748669056919941535360475652077878960719233936222871,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.chip_sw_all_escalation_resets/latest/run.log","log_context":["\tOffending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'\n","UVM_ERROR @ 180.504000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 180.504000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"92.chip_sw_all_escalation_resets.39920069230986746475341459368623152386941611263329400044718079088674204661101","seed":39920069230986746475341459368623152386941611263329400044718079088674204661101,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/92.chip_sw_all_escalation_resets/latest/run.log","log_context":["\tOffending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'\n","UVM_ERROR @ 180.432000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 180.432000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size":[{"name":"chip_sw_rstmgr_alert_info","qual_name":"0.chip_sw_rstmgr_alert_info.30545742065579498733710097795118923998299921822105821182867080574479565215004","seed":30545742065579498733710097795118923998299921822105821182867080574479565215004,"line":342,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log","log_context":["UVM_ERROR @ 336.616000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 336.616000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rstmgr_alert_info","qual_name":"1.chip_sw_rstmgr_alert_info.11557490101663607903478427729616245268946970698757958719355611784347474760241","seed":11557490101663607903478427729616245268946970698757958719355611784347474760241,"line":342,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest/run.log","log_context":["UVM_ERROR @ 336.460000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 336.460000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rstmgr_alert_info","qual_name":"2.chip_sw_rstmgr_alert_info.58071885395174058659171794159798218878815753682103077960033835414946451043895","seed":58071885395174058659171794159798218878815753682103077960033835414946451043895,"line":342,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_alert_info/latest/run.log","log_context":["UVM_ERROR @ 336.469000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 336.469000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '((!rstreqs[*]) && (reset_cause != HwReq))'":[{"name":"chip_sw_rstmgr_cpu_info","qual_name":"0.chip_sw_rstmgr_cpu_info.113127797972041613445301870951723755471718918087200823346571836748483643093394","seed":113127797972041613445301870951723755471718918087200823346571836748483643093394,"line":346,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log","log_context":["\tOffending '((!rstreqs[0]) && (reset_cause != HwReq))'\n","UVM_ERROR @ 414.608000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 414.608000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_aes_trans","qual_name":"0.chip_sw_clkmgr_off_aes_trans.83198466922587421909425452043286391439398789177324677808305092336687656833589","seed":83198466922587421909425452043286391439398789177324677808305092336687656833589,"line":323,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log","log_context":["\tOffending '((!rstreqs[0]) && (reset_cause != HwReq))'\n","UVM_ERROR @ 185.216000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.216000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_hmac_trans","qual_name":"0.chip_sw_clkmgr_off_hmac_trans.38403817799570538390105160757316372262892300579982847924262107852345415151843","seed":38403817799570538390105160757316372262892300579982847924262107852345415151843,"line":323,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log","log_context":["\tOffending '((!rstreqs[0]) && (reset_cause != HwReq))'\n","UVM_ERROR @ 185.232000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.232000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_kmac_trans","qual_name":"0.chip_sw_clkmgr_off_kmac_trans.32922568900721343353853656721363515166083310573072603292887320401443806761712","seed":32922568900721343353853656721363515166083310573072603292887320401443806761712,"line":323,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log","log_context":["\tOffending '((!rstreqs[0]) && (reset_cause != HwReq))'\n","UVM_ERROR @ 185.200000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.200000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_otbn_trans","qual_name":"0.chip_sw_clkmgr_off_otbn_trans.1330718600602151339134126412124092787328116065889368705648844841671627618354","seed":1330718600602151339134126412124092787328116065889368705648844841671627618354,"line":323,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log","log_context":["\tOffending '((!rstreqs[0]) && (reset_cause != HwReq))'\n","UVM_ERROR @ 185.232000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.232000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_rstmgr_cpu_info","qual_name":"1.chip_sw_rstmgr_cpu_info.103656572393619306009180796226272802103540275563019976892435850904552273620447","seed":103656572393619306009180796226272802103540275563019976892435850904552273620447,"line":346,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log","log_context":["\tOffending '((!rstreqs[0]) && (reset_cause != HwReq))'\n","UVM_ERROR @ 414.640000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 414.640000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_aes_trans","qual_name":"1.chip_sw_clkmgr_off_aes_trans.75367022335889545497717199257191217422358115566403830601856921155821461875995","seed":75367022335889545497717199257191217422358115566403830601856921155821461875995,"line":323,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest/run.log","log_context":["\tOffending '((!rstreqs[0]) && (reset_cause != HwReq))'\n","UVM_ERROR @ 185.184000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.184000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_hmac_trans","qual_name":"1.chip_sw_clkmgr_off_hmac_trans.17188387656548549235897438564071633029309222959057184426845956785543583613700","seed":17188387656548549235897438564071633029309222959057184426845956785543583613700,"line":323,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest/run.log","log_context":["\tOffending '((!rstreqs[0]) && (reset_cause != HwReq))'\n","UVM_ERROR @ 185.264000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.264000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_kmac_trans","qual_name":"1.chip_sw_clkmgr_off_kmac_trans.44033201471400553388029968692193269989651018420430450386608835093934292749777","seed":44033201471400553388029968692193269989651018420430450386608835093934292749777,"line":323,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest/run.log","log_context":["\tOffending '((!rstreqs[0]) && (reset_cause != HwReq))'\n","UVM_ERROR @ 185.280000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.280000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_otbn_trans","qual_name":"1.chip_sw_clkmgr_off_otbn_trans.33012296238611108675697476627995510234396824889698744834712572015892299785148","seed":33012296238611108675697476627995510234396824889698744834712572015892299785148,"line":323,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_otbn_trans/latest/run.log","log_context":["\tOffending '((!rstreqs[0]) && (reset_cause != HwReq))'\n","UVM_ERROR @ 185.168000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.168000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_rstmgr_cpu_info","qual_name":"2.chip_sw_rstmgr_cpu_info.57706339225068854856708896928221580718006626726239033787256481407969810071622","seed":57706339225068854856708896928221580718006626726239033787256481407969810071622,"line":346,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_cpu_info/latest/run.log","log_context":["\tOffending '((!rstreqs[0]) && (reset_cause != HwReq))'\n","UVM_ERROR @ 414.480000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 414.480000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_aes_trans","qual_name":"2.chip_sw_clkmgr_off_aes_trans.83152974553626493413979964159113335658664307406057980027390706224701998822763","seed":83152974553626493413979964159113335658664307406057980027390706224701998822763,"line":323,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_aes_trans/latest/run.log","log_context":["\tOffending '((!rstreqs[0]) && (reset_cause != HwReq))'\n","UVM_ERROR @ 185.264000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.264000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_hmac_trans","qual_name":"2.chip_sw_clkmgr_off_hmac_trans.26470793107356368223023610062158868455844885050514804471168181369020089887120","seed":26470793107356368223023610062158868455844885050514804471168181369020089887120,"line":323,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_hmac_trans/latest/run.log","log_context":["\tOffending '((!rstreqs[0]) && (reset_cause != HwReq))'\n","UVM_ERROR @ 185.168000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.168000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_kmac_trans","qual_name":"2.chip_sw_clkmgr_off_kmac_trans.59551811412719125469668158800069804342291687133618042658803556578249917496135","seed":59551811412719125469668158800069804342291687133618042658803556578249917496135,"line":323,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_kmac_trans/latest/run.log","log_context":["\tOffending '((!rstreqs[0]) && (reset_cause != HwReq))'\n","UVM_ERROR @ 185.232000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.232000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_otbn_trans","qual_name":"2.chip_sw_clkmgr_off_otbn_trans.7605175898544492368462013986511633626070840258944250552826713130777043244579","seed":7605175898544492368462013986511633626070840258944250552826713130777043244579,"line":323,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_otbn_trans/latest/run.log","log_context":["\tOffending '((!rstreqs[0]) && (reset_cause != HwReq))'\n","UVM_ERROR @ 185.168000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.168000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!":[{"name":"chip_sw_soc_proxy_smoketest","qual_name":"0.chip_sw_soc_proxy_smoketest.32869287880113329150742005959735586541623004643352380684294940994020557864371","seed":32869287880113329150742005959735586541623004643352380684294940994020557864371,"line":321,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log","log_context":["UVM_ERROR @ 156.928000 us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!\n","UVM_INFO @ 156.928000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_soc_proxy_smoketest","qual_name":"1.chip_sw_soc_proxy_smoketest.93584513762857672930109967406553533117295612034337950719616684785671486392371","seed":93584513762857672930109967406553533117295612034337950719616684785671486392371,"line":321,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_smoketest/latest/run.log","log_context":["UVM_ERROR @ 156.864000 us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!\n","UVM_INFO @ 156.864000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_soc_proxy_smoketest","qual_name":"2.chip_sw_soc_proxy_smoketest.88764777797053514981926440856194815911146834949734855907137745558118274971747","seed":88764777797053514981926440856194815911146834949734855907137745558118274971747,"line":321,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_soc_proxy_smoketest/latest/run.log","log_context":["UVM_ERROR @ 156.944000 us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!\n","UVM_INFO @ 156.944000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns *":[{"name":"chip_sw_soc_proxy_external_wakeup","qual_name":"0.chip_sw_soc_proxy_external_wakeup.72621323168401352838177265814687353874437557095883088322984006193455063946194","seed":72621323168401352838177265814687353874437557095883088322984006193455063946194,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log","log_context":["UVM_ERROR @ 157.825000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3\n","UVM_INFO @ 157.825000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_soc_proxy_external_wakeup","qual_name":"1.chip_sw_soc_proxy_external_wakeup.3958471525494340495223874120948651081099748508445155012621155115756702601365","seed":3958471525494340495223874120948651081099748508445155012621155115756702601365,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_wakeup/latest/run.log","log_context":["UVM_ERROR @ 157.953000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3\n","UVM_INFO @ 157.953000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_soc_proxy_external_wakeup","qual_name":"2.chip_sw_soc_proxy_external_wakeup.108776062085708791084129918555851589514195617178938424101921451445313849158532","seed":108776062085708791084129918555851589514195617178938424101921451445313849158532,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_soc_proxy_external_wakeup/latest/run.log","log_context":["UVM_ERROR @ 158.012000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3\n","UVM_INFO @ 158.012000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec":[{"name":"chip_sw_aon_timer_irq","qual_name":"0.chip_sw_aon_timer_irq.55664498648205274592517414792787565031963251756294404179226924348347480152840","seed":55664498648205274592517414792787565031963251756294404179226924348347480152840,"line":320,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log","log_context":["UVM_ERROR @ 623.896000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 4669 usec which is not in the range 426 usec and 485 usec\n","UVM_INFO @ 623.896000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aon_timer_irq","qual_name":"1.chip_sw_aon_timer_irq.6658314575727685267711683083033487043853517742931023175563011333812833437133","seed":6658314575727685267711683083033487043853517742931023175563011333812833437133,"line":320,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest/run.log","log_context":["UVM_ERROR @ 528.921000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 3679 usec which is not in the range 336 usec and 385 usec\n","UVM_INFO @ 528.921000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aon_timer_irq","qual_name":"2.chip_sw_aon_timer_irq.49356130566119855905053750004800131656004963086579634382787785297564659351076","seed":49356130566119855905053750004800131656004963086579634382787785297564659351076,"line":320,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_irq/latest/run.log","log_context":["UVM_ERROR @ 488.016000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 3252 usec which is not in the range 297 usec and 342 usec\n","UVM_INFO @ 488.016000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds":[{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"0.chip_sw_aon_timer_wdog_bite_reset.80490438446907390652761502731788029660279636345866645412689417862295959873888","seed":80490438446907390652761502731788029660279636345866645412689417862295959873888,"line":321,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_ERROR @ 183.896000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds\n","UVM_INFO @ 183.896000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"1.chip_sw_aon_timer_wdog_bite_reset.20705424786578780181018458952187877643293184468337214220995824978985903767855","seed":20705424786578780181018458952187877643293184468337214220995824978985903767855,"line":321,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_ERROR @ 183.944000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds\n","UVM_INFO @ 183.944000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"2.chip_sw_aon_timer_wdog_bite_reset.57505464915156247507481940182280457234228447470132035953463276165327541201593","seed":57505464915156247507481940182280457234228447470132035953463276165327541201593,"line":321,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_ERROR @ 183.937000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds\n","UVM_INFO @ 183.937000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\"":[{"name":"chip_sw_otbn_ecdsa_op_irq_jitter_en","qual_name":"0.chip_sw_otbn_ecdsa_op_irq_jitter_en.28326095886384433108847880341120521541258632951904200834117456534310511043297","seed":28326095886384433108847880341120521541258632951904200834117456534310511043297,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log","log_context":["UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aes_enc_jitter_en","qual_name":"0.chip_sw_aes_enc_jitter_en.77694418655746900013061376946562873505354743696680566043143557612502662470038","seed":77694418655746900013061376946562873505354743696680566043143557612502662470038,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log","log_context":["UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_hmac_enc_jitter_en","qual_name":"0.chip_sw_hmac_enc_jitter_en.37374580363802621515206099326079465593490999257824484758974258365342368526458","seed":37374580363802621515206099326079465593490999257824484758974258365342368526458,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log","log_context":["UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation_jitter_en","qual_name":"0.chip_sw_keymgr_dpe_key_derivation_jitter_en.51457863560238047619778672756585140227766083534720034962269199669143903260653","seed":51457863560238047619778672756585140227766083534720034962269199669143903260653,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log","log_context":["UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_kmac_mode_kmac_jitter_en","qual_name":"0.chip_sw_kmac_mode_kmac_jitter_en.63635075815495919398996787640422911946814563079658745225989786533748865584607","seed":63635075815495919398996787640422911946814563079658745225989786533748865584607,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log","log_context":["UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq","qual_name":"0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.39268115353735864534756454297835766475397827937678310045400581899534967776383","seed":39268115353735864534756454297835766475397827937678310045400581899534967776383,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aes_enc_jitter_en_reduced_freq","qual_name":"0.chip_sw_aes_enc_jitter_en_reduced_freq.110304180315052227508011705295647644299921321163625898840433304221555470239129","seed":110304180315052227508011705295647644299921321163625898840433304221555470239129,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_hmac_enc_jitter_en_reduced_freq","qual_name":"0.chip_sw_hmac_enc_jitter_en_reduced_freq.54495222067661307372460403178931035218363348241384215984925108966846638606490","seed":54495222067661307372460403178931035218363348241384215984925108966846638606490,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq","qual_name":"0.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq.49305456588522267010237241589521267402437377952647242173472689270660224199117","seed":49305456588522267010237241589521267402437377952647242173472689270660224199117,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_kmac_mode_kmac_jitter_en_reduced_freq","qual_name":"0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.13527135173675625455733942012395152166746047324898333909079522654758205244442","seed":13527135173675625455733942012395152166746047324898333909079522654758205244442,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq","qual_name":"0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.35010692057807204549082946548959373898760021444119262995134519951113264736883","seed":35010692057807204549082946548959373898760021444119262995134519951113264736883,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_csrng_edn_concurrency_reduced_freq","qual_name":"0.chip_sw_csrng_edn_concurrency_reduced_freq.37070968645382731124485992279885451480816249871104734472082527495789287135997","seed":37070968645382731124485992279885451480816249871104734472082527495789287135997,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otbn_ecdsa_op_irq_jitter_en","qual_name":"1.chip_sw_otbn_ecdsa_op_irq_jitter_en.34419178661068220299512389229947265622090581997505385352326126879230730420139","seed":34419178661068220299512389229947265622090581997505385352326126879230730420139,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log","log_context":["UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aes_enc_jitter_en","qual_name":"1.chip_sw_aes_enc_jitter_en.16201645336417798730835762372849586822643899268180375551034376439649190867679","seed":16201645336417798730835762372849586822643899268180375551034376439649190867679,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest/run.log","log_context":["UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_hmac_enc_jitter_en","qual_name":"1.chip_sw_hmac_enc_jitter_en.98180253672040537321413925662669435184317466292342675069792239231778500509386","seed":98180253672040537321413925662669435184317466292342675069792239231778500509386,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest/run.log","log_context":["UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation_jitter_en","qual_name":"1.chip_sw_keymgr_dpe_key_derivation_jitter_en.26679077659290743745858783537596714622579114396520456791346887844786770041479","seed":26679077659290743745858783537596714622579114396520456791346887844786770041479,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log","log_context":["UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_kmac_mode_kmac_jitter_en","qual_name":"1.chip_sw_kmac_mode_kmac_jitter_en.80342058493444830809174832575576637509008794398773714828807628967115770007092","seed":80342058493444830809174832575576637509008794398773714828807628967115770007092,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log","log_context":["UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq","qual_name":"1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.38099463386963665081391284841699219548722534537886973114160108962727277245050","seed":38099463386963665081391284841699219548722534537886973114160108962727277245050,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aes_enc_jitter_en_reduced_freq","qual_name":"1.chip_sw_aes_enc_jitter_en_reduced_freq.50180124659457541330456103228798438978495653169044407269318934533774053495692","seed":50180124659457541330456103228798438978495653169044407269318934533774053495692,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_hmac_enc_jitter_en_reduced_freq","qual_name":"1.chip_sw_hmac_enc_jitter_en_reduced_freq.55099795732646558312790197034324742581008993745728601455991246881127494851461","seed":55099795732646558312790197034324742581008993745728601455991246881127494851461,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq","qual_name":"1.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq.76286158970179121890262669759469132576216014006073374063125948328110789057414","seed":76286158970179121890262669759469132576216014006073374063125948328110789057414,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_kmac_mode_kmac_jitter_en_reduced_freq","qual_name":"1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.11112110638888744625570432944556763138897065855351783014141812182663830395453","seed":11112110638888744625570432944556763138897065855351783014141812182663830395453,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq","qual_name":"1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.86438133105639194009884601173364829911810957007717276023370411268511629055752","seed":86438133105639194009884601173364829911810957007717276023370411268511629055752,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_csrng_edn_concurrency_reduced_freq","qual_name":"1.chip_sw_csrng_edn_concurrency_reduced_freq.8073640864720888694463617110315683507155229765123951422161252505864427654781","seed":8073640864720888694463617110315683507155229765123951422161252505864427654781,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otbn_ecdsa_op_irq_jitter_en","qual_name":"2.chip_sw_otbn_ecdsa_op_irq_jitter_en.59391577341308310371575412719994128392013385950572409122393180954261688719265","seed":59391577341308310371575412719994128392013385950572409122393180954261688719265,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log","log_context":["UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aes_enc_jitter_en","qual_name":"2.chip_sw_aes_enc_jitter_en.20182915640015533121108926370187601912747695137784800396613512839252819085903","seed":20182915640015533121108926370187601912747695137784800396613512839252819085903,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en/latest/run.log","log_context":["UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_hmac_enc_jitter_en","qual_name":"2.chip_sw_hmac_enc_jitter_en.83963865227189236398129681850392588029375334833601153237281573089036466879651","seed":83963865227189236398129681850392588029375334833601153237281573089036466879651,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_enc_jitter_en/latest/run.log","log_context":["UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation_jitter_en","qual_name":"2.chip_sw_keymgr_dpe_key_derivation_jitter_en.13998748160304630336130525643128492883249717163977247172389768802705384493847","seed":13998748160304630336130525643128492883249717163977247172389768802705384493847,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log","log_context":["UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_kmac_mode_kmac_jitter_en","qual_name":"2.chip_sw_kmac_mode_kmac_jitter_en.28638954043055465514770372445387235592012715995739492077834086614244858422550","seed":28638954043055465514770372445387235592012715995739492077834086614244858422550,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log","log_context":["UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq","qual_name":"2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.111887205256416912402255136313935343492770017618034801553417223396466857275822","seed":111887205256416912402255136313935343492770017618034801553417223396466857275822,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aes_enc_jitter_en_reduced_freq","qual_name":"2.chip_sw_aes_enc_jitter_en_reduced_freq.60433166840555208592265072413331124300145269645582207647813223375716960152453","seed":60433166840555208592265072413331124300145269645582207647813223375716960152453,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_hmac_enc_jitter_en_reduced_freq","qual_name":"2.chip_sw_hmac_enc_jitter_en_reduced_freq.58328850466059028903073673064652605240867820196142303402943098306671467605717","seed":58328850466059028903073673064652605240867820196142303402943098306671467605717,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq","qual_name":"2.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq.72628725174195266604818809997192109724376937345323545536975722331266170215993","seed":72628725174195266604818809997192109724376937345323545536975722331266170215993,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_kmac_mode_kmac_jitter_en_reduced_freq","qual_name":"2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.9210961838162742448758124629872075537082278510273472770840348170975729074384","seed":9210961838162742448758124629872075537082278510273472770840348170975729074384,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq","qual_name":"2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.5350079875429957423719633524613248183470771450657758718861144045890134729308","seed":5350079875429957423719633524613248183470771450657758718861144045890134729308,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_csrng_edn_concurrency_reduced_freq","qual_name":"2.chip_sw_csrng_edn_concurrency_reduced_freq.38681313023285928530452296757974271054658036866493369021889891829560533855420","seed":38681313023285928530452296757974271054658036866493369021889891829560533855420,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == *":[{"name":"chip_sw_rv_core_ibex_rnd","qual_name":"0.chip_sw_rv_core_ibex_rnd.101962509910950456298315969103094966656054256266061710727874588419790242893425","seed":101962509910950456298315969103094966656054256266061710727874588419790242893425,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_rnd/latest/run.log","log_context":["UVM_ERROR @ 173.896000 us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == 0\n","UVM_INFO @ 173.896000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rv_core_ibex_rnd","qual_name":"1.chip_sw_rv_core_ibex_rnd.103008630658441313126804014709356576622952600349159774920779310995276814814050","seed":103008630658441313126804014709356576622952600349159774920779310995276814814050,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_rnd/latest/run.log","log_context":["UVM_ERROR @ 195.563000 us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == 0\n","UVM_INFO @ 195.563000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired":[{"name":"chip_sw_rv_core_ibex_nmi_irq","qual_name":"0.chip_sw_rv_core_ibex_nmi_irq.85646758116919779971611512439958151100266740136179747412268499580691608999824","seed":85646758116919779971611512439958151100266740136179747412268499580691608999824,"line":322,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log","log_context":["UVM_ERROR @ 272.321000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired\n","UVM_INFO @ 272.321000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rv_core_ibex_nmi_irq","qual_name":"1.chip_sw_rv_core_ibex_nmi_irq.134259434233057110881886115828361913861125131065429201108259518904481226510","seed":134259434233057110881886115828361913861125131065429201108259518904481226510,"line":322,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log","log_context":["UVM_ERROR @ 272.188000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired\n","UVM_INFO @ 272.188000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rv_core_ibex_nmi_irq","qual_name":"2.chip_sw_rv_core_ibex_nmi_irq.82787564545261796185767007941494046463275430029597998196572470367219529118628","seed":82787564545261796185767007941494046463275430029597998196572470367219529118628,"line":322,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_nmi_irq/latest/run.log","log_context":["UVM_ERROR @ 272.225000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired\n","UVM_INFO @ 272.225000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP":[{"name":"chip_sw_keymgr_dpe_key_derivation","qual_name":"0.chip_sw_keymgr_dpe_key_derivation.19739653775660764294202350354188440296526557141065737793111093284443342762462","seed":19739653775660764294202350354188440296526557141065737793111093284443342762462,"line":340,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log","log_context":["UVM_ERROR @ 305.651000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (4788916985883488730794633841072276826227569273951571607365089250902394497490253670240111665610040498920876443646958123877570418713184744218999893759712348 [0x5b6fbd16aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3dd390de77f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP\n","UVM_INFO @ 305.651000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation_prod","qual_name":"0.chip_sw_keymgr_dpe_key_derivation_prod.73268669222367093096899884655511830163347036203258161449949634170974247271498","seed":73268669222367093096899884655511830163347036203258161449949634170974247271498,"line":340,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log","log_context":["UVM_ERROR @ 305.447000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (182329656446730462020322377011027811157065246084160926571456190642001140716848540251648893014291832485819164304027205456742784421381740712706939566775388 [0x37b3573aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3852d85827f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP\n","UVM_INFO @ 305.447000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation","qual_name":"1.chip_sw_keymgr_dpe_key_derivation.72725171019330576588242595127130630841552936330834205774258917520074722437383","seed":72725171019330576588242595127130630841552936330834205774258917520074722437383,"line":340,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation/latest/run.log","log_context":["UVM_ERROR @ 305.599000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (7265299802824746614487276169985007942558195866572173110488639060541775215451167767583092046795144067432639855464530945155105792127856302365203125160467548 [0x8ab80bb2aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd30ceebb437f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP\n","UVM_INFO @ 305.599000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation_prod","qual_name":"1.chip_sw_keymgr_dpe_key_derivation_prod.21851890352411087405745327864737773639521246849173443626975310419695940894473","seed":21851890352411087405745327864737773639521246849173443626975310419695940894473,"line":340,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log","log_context":["UVM_ERROR @ 305.592000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (3995036228599216421680315799431311996477858051048428823952365253957999436539752349435728865913164985459218987470196722013239425525322055220956904833768540 [0x4c47548faae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3ca11e47e7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP\n","UVM_INFO @ 305.592000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation","qual_name":"2.chip_sw_keymgr_dpe_key_derivation.62206714452408881424065935205118335164739937737124498405206632887547542794608","seed":62206714452408881424065935205118335164739937737124498405206632887547542794608,"line":340,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_keymgr_dpe_key_derivation/latest/run.log","log_context":["UVM_ERROR @ 305.664000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (11945456546839938937808631957074332153180873471992065074847272593474751488019082819948190808255521872976891845842811768411126674351294591993201361479359580 [0xe4142ce2aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd362429c137f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP\n","UVM_INFO @ 305.664000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation_prod","qual_name":"2.chip_sw_keymgr_dpe_key_derivation_prod.95938856813495705617574329084040502709801701393953095717798305045869123528796","seed":95938856813495705617574329084040502709801701393953095717798305045869123528796,"line":340,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log","log_context":["UVM_ERROR @ 305.700000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (6313088494969090788533995714309708607251557998586164282507420820960243635572982534773857222534224129292626382027896742547325534236988141979864462250040412 [0x7889bbd8aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3fedf0b297f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP\n","UVM_INFO @ 305.700000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for kSoftwareBarrier == *":[{"name":"chip_sw_dma_abort","qual_name":"0.chip_sw_dma_abort.78007423131445967249088897262283164269529123789892551398915279168361638839263","seed":78007423131445967249088897262283164269529123789892551398915279168361638839263,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log","log_context":["UVM_ERROR @ 212.076000 us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after 500 usec (50000 CPU cycles) waiting for kSoftwareBarrier == 1\n","UVM_INFO @ 212.076000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_dma_abort","qual_name":"1.chip_sw_dma_abort.40567336982764933187333585097211830692442875815355552263654206342724329463327","seed":40567336982764933187333585097211830692442875815355552263654206342724329463327,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest/run.log","log_context":["UVM_ERROR @ 212.201000 us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after 500 usec (50000 CPU cycles) waiting for kSoftwareBarrier == 1\n","UVM_INFO @ 212.201000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_dma_abort","qual_name":"2.chip_sw_dma_abort.14916296685631033077800682614418049037192964326700380630514455543452632780929","seed":14916296685631033077800682614418049037192964326700380630514455543452632780929,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_dma_abort/latest/run.log","log_context":["UVM_ERROR @ 212.134000 us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after 500 usec (50000 CPU cycles) waiting for kSoftwareBarrier == 1\n","UVM_INFO @ 212.134000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:695) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation.":[{"name":"chip_sw_rv_core_ibex_lockstep_glitch","qual_name":"1.chip_sw_rv_core_ibex_lockstep_glitch.99978004800659140150063483365411607416194259271226843371027326835553312576217","seed":99978004800659140150063483365411607416194259271226843371027326835553312576217,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log","log_context":["UVM_FATAL @ 136.882500 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:695) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.\n","UVM_INFO @ 136.882500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault":[{"name":"chip_sw_all_escalation_resets","qual_name":"34.chip_sw_all_escalation_resets.5937269507806940621310396409594249048038684981904908385038139770530120002705","seed":5937269507806940621310396409594249048038684981904908385038139770530120002705,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 182.564000 us: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault\n","UVM_INFO @ 182.564000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"46.chip_sw_all_escalation_resets.13484705832406715700952168640199981819354138080224764248302995936890478708147","seed":13484705832406715700952168640199981819354138080224764248302995936890478708147,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 182.536000 us: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault\n","UVM_INFO @ 182.536000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"57.chip_sw_all_escalation_resets.70476227684853538628045641783268046173714822851517974700663021582117031843826","seed":70476227684853538628045641783268046173714822851517974700663021582117031843826,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/57.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 182.552000 us: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault\n","UVM_INFO @ 182.552000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"76.chip_sw_all_escalation_resets.74354235092250529423175159506947103491750512683927772771613444226606803190943","seed":74354235092250529423175159506947103491750512683927772771613444226606803190943,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/76.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 184.692000 us: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault\n","UVM_INFO @ 184.692000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got *":[{"name":"chip_sw_all_escalation_resets","qual_name":"38.chip_sw_all_escalation_resets.29959099442466281279857872601639458783865041589523583435807223198366266548415","seed":29959099442466281279857872601639458783865041589523583435807223198366266548415,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 181.162000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804\n","UVM_INFO @ 181.162000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"47.chip_sw_all_escalation_resets.22375015178180528091336148050301183850399019093414780665645445108963451712271","seed":22375015178180528091336148050301183850399019093414780665645445108963451712271,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/47.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 181.119000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804\n","UVM_INFO @ 181.119000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"52.chip_sw_all_escalation_resets.54604438962052596289852187250397718261967249765396952103400113386497909698270","seed":54604438962052596289852187250397718261967249765396952103400113386497909698270,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/52.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 181.166000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804\n","UVM_INFO @ 181.166000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"58.chip_sw_all_escalation_resets.57454910986450581852109510013881631572139410892833314442282149295181487849417","seed":57454910986450581852109510013881631572139410892833314442282149295181487849417,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/58.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 181.271000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804\n","UVM_INFO @ 181.271000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"75.chip_sw_all_escalation_resets.10377213676436728595655043299020049991611410487720116738300373119744196885873","seed":10377213676436728595655043299020049991611410487720116738300373119744196885873,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/75.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 181.229000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804\n","UVM_INFO @ 181.229000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Error-[CNST-CIF] Constraints inconsistency failure":[{"name":"chip_padctrl_attributes","qual_name":"0.chip_padctrl_attributes.35127952879888545416955469168334929138849024806405769117469936478879408378765","seed":35127952879888545416955469168334929138849024806405769117469936478879408378765,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log","log_context":["Error-[CNST-CIF] Constraints inconsistency failure\n","src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 132\n","  Constraints are inconsistent and cannot be solved.\n","  Please check the inconsistent constraints being printed above and rewrite \n","  them.\n"]},{"name":"chip_padctrl_attributes","qual_name":"1.chip_padctrl_attributes.36947817122911212887874872773858120479244754411845486780300132141518640984157","seed":36947817122911212887874872773858120479244754411845486780300132141518640984157,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest/run.log","log_context":["Error-[CNST-CIF] Constraints inconsistency failure\n","src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 132\n","  Constraints are inconsistent and cannot be solved.\n","  Please check the inconsistent constraints being printed above and rewrite \n","  them.\n"]},{"name":"chip_padctrl_attributes","qual_name":"2.chip_padctrl_attributes.47187077839489395520296514942784301436732286079325372739344122790230805180907","seed":47187077839489395520296514942784301436732286079325372739344122790230805180907,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_padctrl_attributes/latest/run.log","log_context":["Error-[CNST-CIF] Constraints inconsistency failure\n","src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 132\n","  Constraints are inconsistent and cannot be solved.\n","  Please check the inconsistent constraints being printed above and rewrite \n","  them.\n"]},{"name":"chip_padctrl_attributes","qual_name":"3.chip_padctrl_attributes.81941976681370387906912327972972746005632030461177287774931125948315798991591","seed":81941976681370387906912327972972746005632030461177287774931125948315798991591,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_padctrl_attributes/latest/run.log","log_context":["Error-[CNST-CIF] Constraints inconsistency failure\n","src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 132\n","  Constraints are inconsistent and cannot be solved.\n","  Please check the inconsistent constraints being printed above and rewrite \n","  them.\n"]},{"name":"chip_padctrl_attributes","qual_name":"4.chip_padctrl_attributes.9443014790511077830014114436771052456583008980294831834189200777628115106485","seed":9443014790511077830014114436771052456583008980294831834189200777628115106485,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_padctrl_attributes/latest/run.log","log_context":["Error-[CNST-CIF] Constraints inconsistency failure\n","src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 132\n","  Constraints are inconsistent and cannot be solved.\n","  Please check the inconsistent constraints being printed above and rewrite \n","  them.\n"]},{"name":"chip_padctrl_attributes","qual_name":"5.chip_padctrl_attributes.91261141455607454159592735090563119577069356329761525840534530175823376444827","seed":91261141455607454159592735090563119577069356329761525840534530175823376444827,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_padctrl_attributes/latest/run.log","log_context":["Error-[CNST-CIF] Constraints inconsistency failure\n","src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 132\n","  Constraints are inconsistent and cannot be solved.\n","  Please check the inconsistent constraints being printed above and rewrite \n","  them.\n"]},{"name":"chip_padctrl_attributes","qual_name":"6.chip_padctrl_attributes.56315830033160748593288871242611312440793541956300015468968540163184385638126","seed":56315830033160748593288871242611312440793541956300015468968540163184385638126,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_padctrl_attributes/latest/run.log","log_context":["Error-[CNST-CIF] Constraints inconsistency failure\n","src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 132\n","  Constraints are inconsistent and cannot be solved.\n","  Please check the inconsistent constraints being printed above and rewrite \n","  them.\n"]},{"name":"chip_padctrl_attributes","qual_name":"7.chip_padctrl_attributes.57072896676804986789417000133851981335528064138216800200372143076412537966609","seed":57072896676804986789417000133851981335528064138216800200372143076412537966609,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_padctrl_attributes/latest/run.log","log_context":["Error-[CNST-CIF] Constraints inconsistency failure\n","src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 132\n","  Constraints are inconsistent and cannot be solved.\n","  Please check the inconsistent constraints being printed above and rewrite \n","  them.\n"]},{"name":"chip_padctrl_attributes","qual_name":"8.chip_padctrl_attributes.39083591543899270099937988191250870786892847083207379868549429132818822017712","seed":39083591543899270099937988191250870786892847083207379868549429132818822017712,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_padctrl_attributes/latest/run.log","log_context":["Error-[CNST-CIF] Constraints inconsistency failure\n","src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 132\n","  Constraints are inconsistent and cannot be solved.\n","  Please check the inconsistent constraints being printed above and rewrite \n","  them.\n"]},{"name":"chip_padctrl_attributes","qual_name":"9.chip_padctrl_attributes.110515402255099527235448266627698513106123787253807602252454699982970985854164","seed":110515402255099527235448266627698513106123787253807602252454699982970985854164,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_padctrl_attributes/latest/run.log","log_context":["Error-[CNST-CIF] Constraints inconsistency failure\n","src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 132\n","  Constraints are inconsistent and cannot be solved.\n","  Please check the inconsistent constraints being printed above and rewrite \n","  them.\n"]}]}},"passed":1944,"total":2642,"percent":73.58062074186222}