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---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"4.keymgr_stress_all_with_rand_reset.64202164907684478009665411886853982494362619465380729309315804324174535398820","seed":64202164907684478009665411886853982494362619465380729309315804324174535398820,"line":550,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 449837937 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 449837937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"9.keymgr_stress_all_with_rand_reset.25217910140512772062156708992541457936685071140726032692694324346174224263933","seed":25217910140512772062156708992541457936685071140726032692694324346174224263933,"line":890,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/9.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 800570998 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 800570998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"11.keymgr_stress_all_with_rand_reset.75152575584482470689730121647124330070868031023834243799938920641223327420328","seed":75152575584482470689730121647124330070868031023834243799938920641223327420328,"line":443,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2364254062 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2364254062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"15.keymgr_stress_all_with_rand_reset.77686370609318999604732430535319737890545984221239631092280871364250103725970","seed":77686370609318999604732430535319737890545984221239631092280871364250103725970,"line":163,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/15.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 106496992 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 106496992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"19.keymgr_stress_all_with_rand_reset.101276936123844284450584235081821323642622531858148654032787201138073246499065","seed":101276936123844284450584235081821323642622531858148654032787201138073246499065,"line":310,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/19.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 475788260 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 475788260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"21.keymgr_stress_all_with_rand_reset.17548698151159327143602553326285606459496717342154283581595141249563413499545","seed":17548698151159327143602553326285606459496717342154283581595141249563413499545,"line":527,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/21.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 410518774 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 410518774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"24.keymgr_stress_all_with_rand_reset.76938711782649052248699537557011079329157704355673566635405146531558836317149","seed":76938711782649052248699537557011079329157704355673566635405146531558836317149,"line":1047,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/24.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 307769449 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 307769449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"26.keymgr_stress_all_with_rand_reset.26620936421219833056526964948662095514033307249585752334230548164723584804761","seed":26620936421219833056526964948662095514033307249585752334230548164723584804761,"line":305,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/26.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 187264339 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 187264339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"27.keymgr_stress_all_with_rand_reset.59761783113972054110906695151080087995783314653859597568368839596737901225770","seed":59761783113972054110906695151080087995783314653859597568368839596737901225770,"line":536,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/27.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 472076515 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 472076515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"29.keymgr_stress_all_with_rand_reset.17354111640524216430443341544785138402391742248249412519429077736154092479890","seed":17354111640524216430443341544785138402391742248249412519429077736154092479890,"line":366,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/29.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 211088494 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 211088494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"32.keymgr_stress_all_with_rand_reset.19928268126564571515944060858051220738710346648447278826464921147702447812774","seed":19928268126564571515944060858051220738710346648447278826464921147702447812774,"line":757,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/32.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 957313566 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 957313566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"33.keymgr_stress_all_with_rand_reset.28786513863852071491428774340177246299121853388225100298759477353166131162029","seed":28786513863852071491428774340177246299121853388225100298759477353166131162029,"line":172,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/33.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 557584777 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 557584777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"35.keymgr_stress_all_with_rand_reset.68757064308552167045966996926488998909285112329806744322417732069525032111342","seed":68757064308552167045966996926488998909285112329806744322417732069525032111342,"line":494,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/35.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 267176038 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10008 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 267176038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"36.keymgr_stress_all_with_rand_reset.113646096201728543727029167976747674354949456628047629285408576282919318930288","seed":113646096201728543727029167976747674354949456628047629285408576282919318930288,"line":143,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/36.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 217520773 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 217520773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"38.keymgr_stress_all_with_rand_reset.113498391203557091116166212698029838905436741682646522005273440786781720692833","seed":113498391203557091116166212698029838905436741682646522005273440786781720692833,"line":106,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/38.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 468411400 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 468411400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"41.keymgr_stress_all_with_rand_reset.38957614213909061759242030091375427012687492223794965425820181076932767818601","seed":38957614213909061759242030091375427012687492223794965425820181076932767818601,"line":270,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/41.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 619729145 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 619729145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"42.keymgr_stress_all_with_rand_reset.42904952079349009986327059378238864187002556481192178217648766677645220249086","seed":42904952079349009986327059378238864187002556481192178217648766677645220249086,"line":603,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/42.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1245534303 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1245534303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"48.keymgr_stress_all_with_rand_reset.90151546063433330610134334633627862014089460946469174202835554950820413947730","seed":90151546063433330610134334633627862014089460946469174202835554950820413947730,"line":979,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/48.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 926208888 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 926208888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_*":[{"name":"keymgr_stress_all_with_rand_reset","qual_name":"2.keymgr_stress_all_with_rand_reset.111575293033593294998913338008513798071999844771452978578618097584562504875653","seed":111575293033593294998913338008513798071999844771452978578618097584562504875653,"line":245,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 119869418 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_4\n","UVM_INFO @ 119869418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*":[{"name":"keymgr_kmac_rsp_err","qual_name":"5.keymgr_kmac_rsp_err.86564365388620725076177531379798343133279105951705183766449734451612803793739","seed":86564365388620725076177531379798343133279105951705183766449734451612803793739,"line":128,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/5.keymgr_kmac_rsp_err/latest/run.log","log_context":["UVM_ERROR @   4260146 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @   4260146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_cfg_regwen","qual_name":"7.keymgr_cfg_regwen.17566317804196342487158080520500859376953888172067933542706703017417062489496","seed":17566317804196342487158080520500859376953888172067933542706703017417062489496,"line":134,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/7.keymgr_cfg_regwen/latest/run.log","log_context":["UVM_ERROR @  10325355 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @  10325355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all","qual_name":"8.keymgr_stress_all.57888386909455354768597864453145802447642997644503403359053680521134854476231","seed":57888386909455354768597864453145802447642997644503403359053680521134854476231,"line":817,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/8.keymgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 291073630 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @ 291073630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_custom_cm","qual_name":"19.keymgr_custom_cm.115043193789478573208601455781571002517241548513393273917049197061957377642225","seed":115043193789478573208601455781571002517241548513393273917049197061957377642225,"line":224,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/19.keymgr_custom_cm/latest/run.log","log_context":["UVM_ERROR @  55096622 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @  55096622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share0_output_*":[{"name":"keymgr_stress_all_with_rand_reset","qual_name":"45.keymgr_stress_all_with_rand_reset.75814757673626025003331199742632557834446497397949760346807385029908384314456","seed":75814757673626025003331199742632557834446497397949760346807385029908384314456,"line":1113,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/45.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 946222371 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_1\n","UVM_INFO @ 946222371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.start":[{"name":"keymgr_cfg_regwen","qual_name":"46.keymgr_cfg_regwen.97261137699004847902351470558298734773799378976465595900238944450792943660528","seed":97261137699004847902351470558298734773799378976465595900238944450792943660528,"line":86,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/46.keymgr_cfg_regwen/latest/run.log","log_context":["UVM_ERROR @   7278207 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start\n","UVM_INFO @   7278207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StCreatorRootKey for Attestation Aes":[{"name":"keymgr_lc_disable","qual_name":"47.keymgr_lc_disable.93613033750304446838526634744796918457631988602923011910980417232197021967389","seed":93613033750304446838526634744796918457631988602923011910980417232197021967389,"line":443,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/47.keymgr_lc_disable/latest/run.log","log_context":["UVM_ERROR @ 183875921 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (5408461793443109681400701245156756893308824820698790680695160414374153904712444635885312178785546360320940517458704303912478978526047908777165957705934455 [0x674402b46a565ae9799d6cc5f590c82309a327d7dc73a35f951ea8134816870dc906a7fd0e68eccc63822f54010fbe3dfb3f446188548456f10dacbe5ca6a677] vs 5408461793443109681400701245156756893308824820698790680695160414374153904712444635885312178785546360320940517458704303912478978526047908777165957705934455 [0x674402b46a565ae9799d6cc5f590c82309a327d7dc73a35f951ea8134816870dc906a7fd0e68eccc63822f54010fbe3dfb3f446188548456f10dacbe5ca6a677]) AES key at state StCreatorRootKey for Attestation Aes\n","UVM_INFO @ 183875921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (keymgr_sync_async_fault_cross_vseq.sv:38) [keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] || act_fault_status[keymgr_pkg::FaultKmacOut] == * (* [*] vs * [*])":[{"name":"keymgr_sync_async_fault_cross","qual_name":"48.keymgr_sync_async_fault_cross.99886050982724050203458121311065289844672377414664200022598560970179275468389","seed":99886050982724050203458121311065289844672377414664200022598560970179275468389,"line":150,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/48.keymgr_sync_async_fault_cross/latest/run.log","log_context":["UVM_ERROR @ 293087778 ps: (keymgr_sync_async_fault_cross_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] ||                 act_fault_status[keymgr_pkg::FaultKmacOut] == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 293087778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1082,"total":1110,"percent":97.47747747747748}