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---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"2.lc_ctrl_stress_all_with_rand_reset.10389704439464410524166186630445977563146354781225780858877675352529529635896","seed":10389704439464410524166186630445977563146354781225780858877675352529529635896,"line":194,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 217018923 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 217018923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"3.lc_ctrl_stress_all_with_rand_reset.110721483092921683001377908419243608651653927984958992740276069860354048652871","seed":110721483092921683001377908419243608651653927984958992740276069860354048652871,"line":150,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 209991986 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 209991986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"6.lc_ctrl_stress_all_with_rand_reset.12071817212255909388494372342222144466240874940879481443168493183662891796876","seed":12071817212255909388494372342222144466240874940879481443168493183662891796876,"line":1385,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 888865870 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 888865870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"8.lc_ctrl_stress_all_with_rand_reset.73816380616678760913051555870966234238920692988789444317625396492605588821145","seed":73816380616678760913051555870966234238920692988789444317625396492605588821145,"line":3445,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 17569361418 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 17569361418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"12.lc_ctrl_stress_all_with_rand_reset.106164253375886689359051846339498515332539896437464202790477934810631872678598","seed":106164253375886689359051846339498515332539896437464202790477934810631872678598,"line":468,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 633122830 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 633122830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"13.lc_ctrl_stress_all_with_rand_reset.380336758290659559258093785955609569605923012153534850852144059323319023119","seed":380336758290659559258093785955609569605923012153534850852144059323319023119,"line":1594,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3555976534 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3555976534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"14.lc_ctrl_stress_all_with_rand_reset.85328123367242077829853602396586338070369844665228557151467438693113584540886","seed":85328123367242077829853602396586338070369844665228557151467438693113584540886,"line":5478,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 699359871 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 699359871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"16.lc_ctrl_stress_all_with_rand_reset.99585218476431082904645306619444727598175817998594725645079629538110514141471","seed":99585218476431082904645306619444727598175817998594725645079629538110514141471,"line":6681,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2201647609 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2201647609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"18.lc_ctrl_stress_all_with_rand_reset.9437809604810369139848259330901225385704281856324473934682862187260411236375","seed":9437809604810369139848259330901225385704281856324473934682862187260411236375,"line":161,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 803417191 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 803417191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"19.lc_ctrl_stress_all_with_rand_reset.106847937495602563319381808761009038451434575214434005895238583421704179850331","seed":106847937495602563319381808761009038451434575214434005895238583421704179850331,"line":3649,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5085225193 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5085225193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"20.lc_ctrl_stress_all_with_rand_reset.96766480174858489287092929836409180108776475344290846250521132311648567055536","seed":96766480174858489287092929836409180108776475344290846250521132311648567055536,"line":152,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2077055703 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2077055703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"21.lc_ctrl_stress_all_with_rand_reset.111195508289261437239232862070774394247916692909463376566893047615931529448442","seed":111195508289261437239232862070774394247916692909463376566893047615931529448442,"line":8471,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1690563488 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1690563488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"28.lc_ctrl_stress_all_with_rand_reset.35953297005161970933158953132544500565365005731839494480856802518471991062488","seed":35953297005161970933158953132544500565365005731839494480856802518471991062488,"line":2532,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2648666002 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2648666002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"29.lc_ctrl_stress_all_with_rand_reset.42824592254808489637084550354171281656294430325967212149698887184221263619889","seed":42824592254808489637084550354171281656294430325967212149698887184221263619889,"line":204,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 812411184 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 812411184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"31.lc_ctrl_stress_all_with_rand_reset.86406132854266811750340200022052895074563375517855151369711308945895916573021","seed":86406132854266811750340200022052895074563375517855151369711308945895916573021,"line":151,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 109285347 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 109285347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"35.lc_ctrl_stress_all_with_rand_reset.92797679189387121150979320339903631059270321187400139075209441356762234039060","seed":92797679189387121150979320339903631059270321187400139075209441356762234039060,"line":8628,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3774752271 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3774752271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"39.lc_ctrl_stress_all_with_rand_reset.102316585779971017143281076212050565571995259627459641990859918053087065088145","seed":102316585779971017143281076212050565571995259627459641990859918053087065088145,"line":1298,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4813486806 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4813486806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"40.lc_ctrl_stress_all_with_rand_reset.53005663280501279192214082568341277083026495038994061683959342035930114789606","seed":53005663280501279192214082568341277083026495038994061683959342035930114789606,"line":1651,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2573184253 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2573184253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"41.lc_ctrl_stress_all_with_rand_reset.44351668618819349095567084125355305000944202718395943443180825654067125949971","seed":44351668618819349095567084125355305000944202718395943443180825654067125949971,"line":200,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 228373858 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 228373858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"42.lc_ctrl_stress_all_with_rand_reset.14564448618934300258587272081320668442237235641319497363804931450946929747371","seed":14564448618934300258587272081320668442237235641319497363804931450946929747371,"line":194,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 225290307 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 225290307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"43.lc_ctrl_stress_all_with_rand_reset.108826169888099003186436226557727483897099370652527863929194555853863637643441","seed":108826169888099003186436226557727483897099370652527863929194555853863637643441,"line":197,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 123795792 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 123795792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"45.lc_ctrl_stress_all_with_rand_reset.104838207805662933583020320504227049175422507347685746498058190827776544855760","seed":104838207805662933583020320504227049175422507347685746498058190827776544855760,"line":3938,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 14003072245 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 14003072245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"46.lc_ctrl_stress_all_with_rand_reset.103632784310208996694432107651726947897343516506498362842360488906232781829323","seed":103632784310208996694432107651726947897343516506498362842360488906232781829323,"line":630,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5798294356 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5798294356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"47.lc_ctrl_stress_all_with_rand_reset.108470692478963880984259900209953008235104103272086731996943252840092612556503","seed":108470692478963880984259900209953008235104103272086731996943252840092612556503,"line":2510,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 18258581416 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 18258581416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"49.lc_ctrl_stress_all_with_rand_reset.113260606637313512607088733608729206955193983764599248505287720215234006712616","seed":113260606637313512607088733608729206955193983764599248505287720215234006712616,"line":156,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1530255071 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1530255071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"11.lc_ctrl_stress_all_with_rand_reset.62388558129770237381735370100928724251032518460468054233667204801336709501289","seed":62388558129770237381735370100928724251032518460468054233667204801336709501289,"line":16950,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5395196098 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error\n","UVM_INFO @ 5395196098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"33.lc_ctrl_stress_all_with_rand_reset.115335626012459157136474619133500204941165995209304465880861503202568200096756","seed":115335626012459157136474619133500204941165995209304465880861503202568200096756,"line":1062,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 524185767 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error\n","UVM_INFO @ 524185767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job timed out after * minutes":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"25.lc_ctrl_stress_all_with_rand_reset.78173755800257912928206169794466420290991403747007427641261382451836926292982","seed":78173755800257912928206169794466420290991403747007427641261382451836926292982,"line":null,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["Job timed out after 180 minutes"]}],"UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:*":[{"name":"lc_ctrl_stress_all","qual_name":"39.lc_ctrl_stress_all.19666942256561738944391474751213611374974607373148987487746918124579238478501","seed":19666942256561738944391474751213611374974607373148987487746918124579238478501,"line":3903,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 26571775469 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000\n","UVM_INFO @ 26571775469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1000,"total":1030,"percent":97.0873786407767}