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---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"5.lc_ctrl_stress_all_with_rand_reset.42236641028043037829815815351746650028250106673146702552152302771977989814958","seed":42236641028043037829815815351746650028250106673146702552152302771977989814958,"line":465,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1193303796 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1193303796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"7.lc_ctrl_stress_all_with_rand_reset.81697434848862452251323491129848072655753508089857149015579876595791517569694","seed":81697434848862452251323491129848072655753508089857149015579876595791517569694,"line":4173,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2365437747 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2365437747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"8.lc_ctrl_stress_all_with_rand_reset.28149234759886792667851046677503821654625250355581376840763162296991546135257","seed":28149234759886792667851046677503821654625250355581376840763162296991546135257,"line":2506,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 300146635 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 300146635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"9.lc_ctrl_stress_all_with_rand_reset.38074123983460229638635029226701344250244829689289967529115626467107733410719","seed":38074123983460229638635029226701344250244829689289967529115626467107733410719,"line":2943,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3679069397 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3679069397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"11.lc_ctrl_stress_all_with_rand_reset.10615442117583774166718535949332284776130980030048253078952520112979896489742","seed":10615442117583774166718535949332284776130980030048253078952520112979896489742,"line":3013,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2653243123 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2653243123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"17.lc_ctrl_stress_all_with_rand_reset.98857476089776685371218546064673691572073717297455844241934115143633626367577","seed":98857476089776685371218546064673691572073717297455844241934115143633626367577,"line":740,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6925553073 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 6925553073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"21.lc_ctrl_stress_all_with_rand_reset.105701870231878899763640235749175410763601921044721555780565425754677217149717","seed":105701870231878899763640235749175410763601921044721555780565425754677217149717,"line":1207,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1816457241 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1816457241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"25.lc_ctrl_stress_all_with_rand_reset.13796757310165375343156159513930871582885978926008174569338403756596871464391","seed":13796757310165375343156159513930871582885978926008174569338403756596871464391,"line":2585,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 16590619273 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 16590619273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"26.lc_ctrl_stress_all_with_rand_reset.68406343500197278961759743776543886527879940374961309737938766990628172231341","seed":68406343500197278961759743776543886527879940374961309737938766990628172231341,"line":151,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 207468732 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 207468732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"27.lc_ctrl_stress_all_with_rand_reset.51654584764457901292631731933023750177847826264800637327345156035736168877664","seed":51654584764457901292631731933023750177847826264800637327345156035736168877664,"line":157,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3740932215 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3740932215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"29.lc_ctrl_stress_all_with_rand_reset.29165935204328564928643870074389090078899056290131236609950026865134934078797","seed":29165935204328564928643870074389090078899056290131236609950026865134934078797,"line":150,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 212469337 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 212469337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"30.lc_ctrl_stress_all_with_rand_reset.84702885225640844729521015207607593827706016069868300343319591564562065594087","seed":84702885225640844729521015207607593827706016069868300343319591564562065594087,"line":3356,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1628132462 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1628132462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"31.lc_ctrl_stress_all_with_rand_reset.9376054341416329443258611599479915555146850654245505238854142084754693899039","seed":9376054341416329443258611599479915555146850654245505238854142084754693899039,"line":2060,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5714894975 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5714894975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"32.lc_ctrl_stress_all_with_rand_reset.109725509596196156443745741882733090865998982550507159599875042457546788069655","seed":109725509596196156443745741882733090865998982550507159599875042457546788069655,"line":438,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1704984958 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1704984958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"37.lc_ctrl_stress_all_with_rand_reset.28704360094914035669255380806509924898037676664909199511713207978595277380209","seed":28704360094914035669255380806509924898037676664909199511713207978595277380209,"line":6437,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1516930330 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1516930330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"40.lc_ctrl_stress_all_with_rand_reset.26870835318157162611026026707901449646339001963799985417046026048056110408683","seed":26870835318157162611026026707901449646339001963799985417046026048056110408683,"line":1165,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4460412981 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4460412981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"41.lc_ctrl_stress_all_with_rand_reset.47965738618196400196316745165326671184300574463119067145791342711977947194927","seed":47965738618196400196316745165326671184300574463119067145791342711977947194927,"line":3636,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5611118941 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5611118941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"43.lc_ctrl_stress_all_with_rand_reset.69050718631442032228487301266502832387486093993718207017898852511178421679930","seed":69050718631442032228487301266502832387486093993718207017898852511178421679930,"line":208,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 568796179 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 568796179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"44.lc_ctrl_stress_all_with_rand_reset.6519908823706614997562237714615407920578649357084532174188454273249487633948","seed":6519908823706614997562237714615407920578649357084532174188454273249487633948,"line":1663,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7760270640 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 7760270640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"49.lc_ctrl_stress_all_with_rand_reset.69282471766384429881825417290070335092323394401889392263751730418847064008880","seed":69282471766384429881825417290070335092323394401889392263751730418847064008880,"line":9613,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 10900780426 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 10900780426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred!":[{"name":"lc_ctrl_jtag_priority","qual_name":"6.lc_ctrl_jtag_priority.63558543718758047264607681929891797187092567743481304619656008855691959176430","seed":63558543718758047264607681929891797187092567743481304619656008855691959176430,"line":148,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_priority/latest/run.log","log_context":["UVM_FATAL @ 10010275469 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!\n","UVM_INFO @ 10010275469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"13.lc_ctrl_stress_all_with_rand_reset.19556757318385749759707296358434183788788745914146034766671347631984672943718","seed":19556757318385749759707296358434183788788745914146034766671347631984672943718,"line":7693,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2196905019 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error\n","UVM_INFO @ 2196905019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"36.lc_ctrl_stress_all_with_rand_reset.16531400191852528911774224870875978278093601585852649419156059929394748294855","seed":16531400191852528911774224870875978278093601585852649419156059929394748294855,"line":3754,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1015125399 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error\n","UVM_INFO @ 1015125399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1006,"total":1030,"percent":97.66990291262135}