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---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"2.rv_dm_delayed_resp_sba_tl_access.19909840439109128864869973323329724615128522197711807446922478204613264044829","seed":19909840439109128864869973323329724615128522197711807446922478204613264044829,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"2.rv_dm_bad_sba_tl_access.94120593485085871566911465538485982893880968728476152813626653774892724333471","seed":94120593485085871566911465538485982893880968728476152813626653774892724333471,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"2.rv_dm_autoincr_sba_tl_access.79755811888424578512742587975348202211074233600616897232316097350668348572032","seed":79755811888424578512742587975348202211074233600616897232316097350668348572032,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"3.rv_dm_sba_tl_access.71967748918264419465914870395625575832966357805376251483348069511499042501009","seed":71967748918264419465914870395625575832966357805376251483348069511499042501009,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"3.rv_dm_delayed_resp_sba_tl_access.32622178424168927669898203118894752623414736861937173340145314731703218352217","seed":32622178424168927669898203118894752623414736861937173340145314731703218352217,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"3.rv_dm_bad_sba_tl_access.18454212372031979750172524126574913951176615435487431296093039370754817427279","seed":18454212372031979750172524126574913951176615435487431296093039370754817427279,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"3.rv_dm_autoincr_sba_tl_access.15779360760733200317658846890614674472220301773500519484403779272116962733538","seed":15779360760733200317658846890614674472220301773500519484403779272116962733538,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"4.rv_dm_sba_tl_access.46364818600042484193561748240884865712947952759838990368065705817573736937434","seed":46364818600042484193561748240884865712947952759838990368065705817573736937434,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"4.rv_dm_delayed_resp_sba_tl_access.76818186444382875595518331059115015952233270604263744435714857192919674211655","seed":76818186444382875595518331059115015952233270604263744435714857192919674211655,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"4.rv_dm_bad_sba_tl_access.5687321668567118819961600139154672384845137529808209153357836105483260886834","seed":5687321668567118819961600139154672384845137529808209153357836105483260886834,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"4.rv_dm_autoincr_sba_tl_access.56014580809127889070288838694841409356562125807040145129621885073118946600826","seed":56014580809127889070288838694841409356562125807040145129621885073118946600826,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"5.rv_dm_sba_tl_access.48015989991174654193240587444787306076235199284436839715447108272074198608936","seed":48015989991174654193240587444787306076235199284436839715447108272074198608936,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"5.rv_dm_delayed_resp_sba_tl_access.17098479981562618360869664112546825552851277857457967370767500469594998785040","seed":17098479981562618360869664112546825552851277857457967370767500469594998785040,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"5.rv_dm_bad_sba_tl_access.35979524397896232122160902190596905423506831870357157069058936722044113617420","seed":35979524397896232122160902190596905423506831870357157069058936722044113617420,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"5.rv_dm_autoincr_sba_tl_access.42957071657388827258492497642400149852332262546563828879775405612100232751323","seed":42957071657388827258492497642400149852332262546563828879775405612100232751323,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"6.rv_dm_sba_tl_access.22607103060643217836133968422023026903901124707866367128829403900935578586902","seed":22607103060643217836133968422023026903901124707866367128829403900935578586902,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"6.rv_dm_delayed_resp_sba_tl_access.95864598798231542041254595895582497624238579636107927234272231151879838436750","seed":95864598798231542041254595895582497624238579636107927234272231151879838436750,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"6.rv_dm_bad_sba_tl_access.16115982442906995668218727198059903867971040915687550957819788464735723265814","seed":16115982442906995668218727198059903867971040915687550957819788464735723265814,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"6.rv_dm_autoincr_sba_tl_access.28120708459286631016867815040737884573354972160560822947303793921915639375421","seed":28120708459286631016867815040737884573354972160560822947303793921915639375421,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"7.rv_dm_sba_tl_access.52058084248506651365097622273347130993939594340340524045665239798884648252179","seed":52058084248506651365097622273347130993939594340340524045665239798884648252179,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"7.rv_dm_delayed_resp_sba_tl_access.49889982505799671099801158739431250798079764790758628714900633550402370278856","seed":49889982505799671099801158739431250798079764790758628714900633550402370278856,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"7.rv_dm_bad_sba_tl_access.56318578389843368276513723982929864593496502206799052267967054362305487282460","seed":56318578389843368276513723982929864593496502206799052267967054362305487282460,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"7.rv_dm_autoincr_sba_tl_access.87845974877044765670176828889094052273925955242363171564009115206916430115071","seed":87845974877044765670176828889094052273925955242363171564009115206916430115071,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"8.rv_dm_sba_tl_access.41974977613696424934651344217665293300249073638026700378509088229374558196737","seed":41974977613696424934651344217665293300249073638026700378509088229374558196737,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"8.rv_dm_delayed_resp_sba_tl_access.88819656544211067603862468126923007357885271336822954051052963453068351429403","seed":88819656544211067603862468126923007357885271336822954051052963453068351429403,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"8.rv_dm_bad_sba_tl_access.66641982715566859571212709380560310804754652548414082249078955737797354552150","seed":66641982715566859571212709380560310804754652548414082249078955737797354552150,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"8.rv_dm_autoincr_sba_tl_access.8149632216327635320824523666548259367706774930747043471817626962666965877186","seed":8149632216327635320824523666548259367706774930747043471817626962666965877186,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"9.rv_dm_sba_tl_access.1806380731109497172238902590271284058615454221023488893798440501863315512414","seed":1806380731109497172238902590271284058615454221023488893798440501863315512414,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"9.rv_dm_delayed_resp_sba_tl_access.103665662803909478785054514365775499890053143948088854403311343361050315065668","seed":103665662803909478785054514365775499890053143948088854403311343361050315065668,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"9.rv_dm_bad_sba_tl_access.93117586008954585932575689807510848367184589182278756210324065928629459549104","seed":93117586008954585932575689807510848367184589182278756210324065928629459549104,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"9.rv_dm_autoincr_sba_tl_access.1842419208094424023901974780459149436045080125805106348007231778754496398254","seed":1842419208094424023901974780459149436045080125805106348007231778754496398254,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"10.rv_dm_sba_tl_access.63958938405528331194723703327014714704825596758333297744212397745595429731525","seed":63958938405528331194723703327014714704825596758333297744212397745595429731525,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/10.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"10.rv_dm_delayed_resp_sba_tl_access.6838263372291841091183295450761280090750628689933945395326193528445793162420","seed":6838263372291841091183295450761280090750628689933945395326193528445793162420,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/10.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"10.rv_dm_bad_sba_tl_access.17626871672938712124722342324172533135444610638218328150562667704402850488150","seed":17626871672938712124722342324172533135444610638218328150562667704402850488150,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/10.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"10.rv_dm_autoincr_sba_tl_access.69546521987198669896369159734209420847347746632203397798949605787476027075787","seed":69546521987198669896369159734209420847347746632203397798949605787476027075787,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"11.rv_dm_sba_tl_access.102750251179187758071916639552922972033467047500515828183303133269346107640985","seed":102750251179187758071916639552922972033467047500515828183303133269346107640985,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"11.rv_dm_delayed_resp_sba_tl_access.87695249279999606987950261839181979225262074243151700782011545163183803838130","seed":87695249279999606987950261839181979225262074243151700782011545163183803838130,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/11.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"11.rv_dm_bad_sba_tl_access.24891978751523027345664670425001093314621678623067854828608112139875365174714","seed":24891978751523027345664670425001093314621678623067854828608112139875365174714,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/11.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"11.rv_dm_autoincr_sba_tl_access.46433285161134686393706394100685659959445366490254280704535843351115333884511","seed":46433285161134686393706394100685659959445366490254280704535843351115333884511,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"12.rv_dm_sba_tl_access.16667641210856636240617432069547337250847384127823458957596567954568383232851","seed":16667641210856636240617432069547337250847384127823458957596567954568383232851,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/12.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"12.rv_dm_delayed_resp_sba_tl_access.108639002459663409897902688314471610297894250750095447623301799383153833845311","seed":108639002459663409897902688314471610297894250750095447623301799383153833845311,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/12.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"12.rv_dm_bad_sba_tl_access.64021512160220453061441169462650293855646762058356717978789492720814551356335","seed":64021512160220453061441169462650293855646762058356717978789492720814551356335,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"12.rv_dm_autoincr_sba_tl_access.46736768523864209439586143887256900875534356507293982021207450312681810300767","seed":46736768523864209439586143887256900875534356507293982021207450312681810300767,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"13.rv_dm_sba_tl_access.62797495692991020863437344099183867523153342593047847810365611761443882608991","seed":62797495692991020863437344099183867523153342593047847810365611761443882608991,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/13.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"13.rv_dm_delayed_resp_sba_tl_access.90609190050177454660895447197257045421765090926109219768398604908184016644288","seed":90609190050177454660895447197257045421765090926109219768398604908184016644288,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/13.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"13.rv_dm_bad_sba_tl_access.55006561662635910472928962928576185749004900211523919502992477828637098561059","seed":55006561662635910472928962928576185749004900211523919502992477828637098561059,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/13.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"13.rv_dm_autoincr_sba_tl_access.72084069820560052772818166919984967118873046171392788528165090016421735216339","seed":72084069820560052772818166919984967118873046171392788528165090016421735216339,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"14.rv_dm_sba_tl_access.90320625266429898888386844003125628648691281725183528137998478621541919519833","seed":90320625266429898888386844003125628648691281725183528137998478621541919519833,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/14.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"14.rv_dm_delayed_resp_sba_tl_access.33196491211208949283892092046670796673186218675899485351215438191759190918692","seed":33196491211208949283892092046670796673186218675899485351215438191759190918692,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/14.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"14.rv_dm_bad_sba_tl_access.25848807418491558988899094848959181568455190654589967791010595585621575691001","seed":25848807418491558988899094848959181568455190654589967791010595585621575691001,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/14.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"14.rv_dm_autoincr_sba_tl_access.91457799635903402657673349714265279664708375921062018707520660218860920728672","seed":91457799635903402657673349714265279664708375921062018707520660218860920728672,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"15.rv_dm_sba_tl_access.82699984877801899888749486728894244131961157058245420990268631366626401141479","seed":82699984877801899888749486728894244131961157058245420990268631366626401141479,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/15.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"15.rv_dm_delayed_resp_sba_tl_access.80760001143187867353648423083733667283463757813256618534944695146987711382630","seed":80760001143187867353648423083733667283463757813256618534944695146987711382630,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/15.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"15.rv_dm_bad_sba_tl_access.40403449261657576018616054944393880406421945315843380401606398322151154011717","seed":40403449261657576018616054944393880406421945315843380401606398322151154011717,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"15.rv_dm_autoincr_sba_tl_access.91310102606359649491398686568006910608672200384598212426462011588404118775198","seed":91310102606359649491398686568006910608672200384598212426462011588404118775198,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"15.rv_dm_stress_all.95203020997343564982886368988790941166019121435742639859237534866439814381152","seed":95203020997343564982886368988790941166019121435742639859237534866439814381152,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/15.rv_dm_stress_all/latest/run.log","log_context":["UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"16.rv_dm_sba_tl_access.66310919313123190706579147598419200021853585809819836395161512075218128019524","seed":66310919313123190706579147598419200021853585809819836395161512075218128019524,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/16.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"16.rv_dm_delayed_resp_sba_tl_access.112277589844701466850481300413816424736724660566501025465408596324959076481707","seed":112277589844701466850481300413816424736724660566501025465408596324959076481707,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/16.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"16.rv_dm_bad_sba_tl_access.111324359806105150430586952081569826420953773956784015485439707510852069818283","seed":111324359806105150430586952081569826420953773956784015485439707510852069818283,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/16.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"16.rv_dm_autoincr_sba_tl_access.71664712845491792737220740100386974132212874993278162774739832053361052787132","seed":71664712845491792737220740100386974132212874993278162774739832053361052787132,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/16.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"17.rv_dm_sba_tl_access.105547634312518657070811166664092319777397985439168781672799620297673261178836","seed":105547634312518657070811166664092319777397985439168781672799620297673261178836,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/17.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"17.rv_dm_delayed_resp_sba_tl_access.87936256537706868582159520956884412924921114874429299730454545050067666362664","seed":87936256537706868582159520956884412924921114874429299730454545050067666362664,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/17.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"17.rv_dm_bad_sba_tl_access.96392082253400339063323420645357391151523842053030658997161290329967495441164","seed":96392082253400339063323420645357391151523842053030658997161290329967495441164,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/17.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"17.rv_dm_autoincr_sba_tl_access.36306260902671296218973424794473387718174008026913401237595512894047041755702","seed":36306260902671296218973424794473387718174008026913401237595512894047041755702,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"17.rv_dm_stress_all.11092217590783224012774022387955855675455672710348379304724148539951378525928","seed":11092217590783224012774022387955855675455672710348379304724148539951378525928,"line":81,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/17.rv_dm_stress_all/latest/run.log","log_context":["UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"18.rv_dm_sba_tl_access.50244727997876445757290013922671531011080345209173307916679231469273434758600","seed":50244727997876445757290013922671531011080345209173307916679231469273434758600,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/18.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"18.rv_dm_delayed_resp_sba_tl_access.70671802223645755211674059773294287342133053063598962791505827780771436510246","seed":70671802223645755211674059773294287342133053063598962791505827780771436510246,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/18.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"18.rv_dm_bad_sba_tl_access.47815710801352033931710260888059895824729458109324909722474871961208239580729","seed":47815710801352033931710260888059895824729458109324909722474871961208239580729,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/18.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"18.rv_dm_autoincr_sba_tl_access.26068808082543548744485645029722341907888992383877759038014018295537570522559","seed":26068808082543548744485645029722341907888992383877759038014018295537570522559,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"19.rv_dm_sba_tl_access.57669333524995311727710742129576735769985944223486036230222773213718438245365","seed":57669333524995311727710742129576735769985944223486036230222773213718438245365,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/19.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"19.rv_dm_delayed_resp_sba_tl_access.3761779715591171966822070617484354677760157633933893686766202780699618540538","seed":3761779715591171966822070617484354677760157633933893686766202780699618540538,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/19.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"19.rv_dm_bad_sba_tl_access.67227312424663824373533678455480378739693863763292561860985934836772074949497","seed":67227312424663824373533678455480378739693863763292561860985934836772074949497,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/19.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"19.rv_dm_autoincr_sba_tl_access.82573398127936674833729937337769737977708270056780763203130344471748754926137","seed":82573398127936674833729937337769737977708270056780763203130344471748754926137,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/19.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == *'b* (* [*] vs * [*])":[{"name":"rv_dm_mem_tl_access_resuming","qual_name":"0.rv_dm_mem_tl_access_resuming.53409045160823616402967092250360913292331335505278339064810158777572716701065","seed":53409045160823616402967092250360913292331335505278339064810158777572716701065,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest/run.log","log_context":["UVM_ERROR @ 427888092 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 427888092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"0.rv_dm_stress_all.80597666361431902454181087901331460822422579383001517396557905118628982900146","seed":80597666361431902454181087901331460822422579383001517396557905118628982900146,"line":81,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 2698019840 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 2698019840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_mem_tl_access_resuming","qual_name":"1.rv_dm_mem_tl_access_resuming.50824833033582536996159571764826472741808928994753836576520955411138124202779","seed":50824833033582536996159571764826472741808928994753836576520955411138124202779,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest/run.log","log_context":["UVM_ERROR @ 516066521 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 516066521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"5.rv_dm_stress_all.90626974053141143659513573557865361735569522651667557914790411200878451210061","seed":90626974053141143659513573557865361735569522651667557914790411200878451210061,"line":84,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 3026438595 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 3026438595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"7.rv_dm_stress_all_with_rand_reset.85691202240420176841125235289635650984472997824062065576511508746215650839014","seed":85691202240420176841125235289635650984472997824062065576511508746215650839014,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 143450150 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 143450150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"10.rv_dm_stress_all.23482041938879629827610035868710708323437326399529961778539476162697458786319","seed":23482041938879629827610035868710708323437326399529961778539476162697458786319,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/10.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 678665209 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 678665209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"14.rv_dm_stress_all.99309229045255741644404676325196633106957319033919950691412060710888563190947","seed":99309229045255741644404676325196633106957319033919950691412060710888563190947,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/14.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 4414304168 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 4414304168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"16.rv_dm_stress_all.69009180666499558778371935968811713098500563638320420066584438132877939914343","seed":69009180666499558778371935968811713098500563638320420066584438132877939914343,"line":82,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/16.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1414319391 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1414319391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"32.rv_dm_stress_all.12473211486845460717314513246521719337608020205076448432866731448999176015641","seed":12473211486845460717314513246521719337608020205076448432866731448999176015641,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/32.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @  83944369 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  83944369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"38.rv_dm_stress_all.43766602547293139634770614702733358862354491535134800838729538558816198057920","seed":43766602547293139634770614702733358862354491535134800838729538558816198057920,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/38.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 110128649 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 110128649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"40.rv_dm_stress_all.90173422433033839290033565409033951332319465459840852238645221225182275772223","seed":90173422433033839290033565409033951332319465459840852238645221225182275772223,"line":95,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/40.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 6871576935 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 6871576935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"45.rv_dm_stress_all.73217205219081889363593668355417898380584960300138009552067568374308084074186","seed":73217205219081889363593668355417898380584960300138009552067568374308084074186,"line":82,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/45.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1616812847 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1616812847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"46.rv_dm_stress_all.112684273660182997691633320012841294814963920643088199303766025474099766986613","seed":112684273660182997691633320012841294814963920643088199303766025474099766986613,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/46.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 442907476 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 442907476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"47.rv_dm_stress_all.97224894096108609646134368073663778170999480626542110589771110766830955487427","seed":97224894096108609646134368073663778170999480626542110589771110766830955487427,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/47.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1957198560 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1957198560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [*] vs * [*])":[{"name":"rv_dm_hart_unavail","qual_name":"0.rv_dm_hart_unavail.90607295759210821715798458764331682204367532760836344571663839897480570495082","seed":90607295759210821715798458764331682204367532760836344571663839897480570495082,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest/run.log","log_context":["UVM_ERROR @ 102971322 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 102971322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_hart_unavail","qual_name":"1.rv_dm_hart_unavail.38314766915515682023948311091637774939743362898902616021086694933445227087020","seed":38314766915515682023948311091637774939743362898902616021086694933445227087020,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_hart_unavail/latest/run.log","log_context":["UVM_ERROR @ 282871784 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 282871784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"1.rv_dm_stress_all_with_rand_reset.13637157555897939647264894600077156091404406192969324586658832172167094288676","seed":13637157555897939647264894600077156091404406192969324586658832172167094288676,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 284538876 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 284538876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_hart_unavail","qual_name":"2.rv_dm_hart_unavail.40166598275649934218700528960590719754789193520769697208718111881899852146148","seed":40166598275649934218700528960590719754789193520769697208718111881899852146148,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_hart_unavail/latest/run.log","log_context":["UVM_ERROR @ 167422916 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 167422916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_hart_unavail","qual_name":"3.rv_dm_hart_unavail.23580249774217012117388830723687555092296956991005822158840413710627443878471","seed":23580249774217012117388830723687555092296956991005822158840413710627443878471,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_hart_unavail/latest/run.log","log_context":["UVM_ERROR @  90092590 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  90092590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_hart_unavail","qual_name":"4.rv_dm_hart_unavail.39412911653583388353823267880235349073484016252362731998987709404976424018773","seed":39412911653583388353823267880235349073484016252362731998987709404976424018773,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_hart_unavail/latest/run.log","log_context":["UVM_ERROR @ 216553001 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 216553001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"4.rv_dm_stress_all_with_rand_reset.33744308422046213629061887745148122672277051712412990754754348050552415329608","seed":33744308422046213629061887745148122672277051712412990754754348050552415329608,"line":92,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1031600231 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1031600231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"5.rv_dm_stress_all_with_rand_reset.77884304293215004416561692687247286710432733765065107856646448761491255000305","seed":77884304293215004416561692687247286710432733765065107856646448761491255000305,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 486725385 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 486725385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"6.rv_dm_stress_all.57654999837033750101635322378363161803343862493211397926832873600407319466243","seed":57654999837033750101635322378363161803343862493211397926832873600407319466243,"line":82,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1155707859 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1155707859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"8.rv_dm_stress_all_with_rand_reset.17850909269909142268802458001046995269693439834139084796545499716609642776565","seed":17850909269909142268802458001046995269693439834139084796545499716609642776565,"line":112,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1800609970 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1800609970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"9.rv_dm_stress_all.54181304461562362361626231017614285720477380757490780507243888038105013306518","seed":54181304461562362361626231017614285720477380757490780507243888038105013306518,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 546133326 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 546133326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"9.rv_dm_stress_all_with_rand_reset.56419341011490752196815355905907276103300001380724278610541406360903187492035","seed":56419341011490752196815355905907276103300001380724278610541406360903187492035,"line":143,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2248388843 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 2248388843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"19.rv_dm_stress_all.47797453322252625894705127171547230749229259071722517496751819363599199565777","seed":47797453322252625894705127171547230749229259071722517496751819363599199565777,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/19.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 204655890 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 204655890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"20.rv_dm_stress_all.13825740674716924877816204329699429582092979046942092031637697911717934043698","seed":13825740674716924877816204329699429582092979046942092031637697911717934043698,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/20.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1838110827 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1838110827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"21.rv_dm_stress_all.14743947024896604001181597232315634178785266135778058763876672671219486608035","seed":14743947024896604001181597232315634178785266135778058763876672671219486608035,"line":84,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/21.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1529814831 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1529814831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"23.rv_dm_stress_all.18191680401136031904257199316042668537109897073022688288932425845491210156599","seed":18191680401136031904257199316042668537109897073022688288932425845491210156599,"line":83,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/23.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 2148849924 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 2148849924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"30.rv_dm_stress_all.99654609279588667382703237783487376006247080171205180628729764299209071476141","seed":99654609279588667382703237783487376006247080171205180628729764299209071476141,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/30.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @  62736942 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  62736942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"34.rv_dm_stress_all.60105008533944530715668826587935711097531807477998090875003463626979838860175","seed":60105008533944530715668826587935711097531807477998090875003463626979838860175,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/34.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 739917226 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 739917226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"39.rv_dm_stress_all.34597309506156051211674176432162294704613054682403776480675578522469376390857","seed":34597309506156051211674176432162294704613054682403776480675578522469376390857,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/39.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 329547571 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 329547571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"43.rv_dm_stress_all.13145038187204601297027911100653803393599502113366557761089215422621812506358","seed":13145038187204601297027911100653803393599502113366557761089215422621812506358,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/43.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 453836933 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 453836933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"44.rv_dm_stress_all.46245461344537462833076869287987391249269383629007365031974390391974355520446","seed":46245461344537462833076869287987391249269383629007365031974390391974355520446,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/44.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 294060158 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 294060158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*])":[{"name":"rv_dm_jtag_dmi_debug_disabled","qual_name":"0.rv_dm_jtag_dmi_debug_disabled.65589607128786087233986877870571634948798959661398671825964723471551309187686","seed":65589607128786087233986877870571634948798959661398671825964723471551309187686,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log","log_context":["UVM_ERROR @ 452059723 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (4126085723 [0xf5ef125b] vs 0 [0x0]) \n","UVM_INFO @ 452059723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_jtag_dmi_debug_disabled","qual_name":"1.rv_dm_jtag_dmi_debug_disabled.12729533449195627982637791845536599827069816744213162091316483475122317772720","seed":12729533449195627982637791845536599827069816744213162091316483475122317772720,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest/run.log","log_context":["UVM_ERROR @ 103131058 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (469369777 [0x1bfa03b1] vs 0 [0x0]) \n","UVM_INFO @ 103131058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"3.rv_dm_stress_all.15468442986821716186349122814654322348407005705286289045282156776528497232530","seed":15468442986821716186349122814654322348407005705286289045282156776528497232530,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1669788771 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3964795463 [0xec51fa47] vs 0 [0x0]) \n","UVM_INFO @ 1669788771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"3.rv_dm_stress_all_with_rand_reset.28542231306756670687627802217275762495542242260710855358855517628704036292591","seed":28542231306756670687627802217275762495542242260710855358855517628704036292591,"line":105,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1933721617 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1280164569 [0x4c4dc2d9] vs 0 [0x0]) \n","UVM_INFO @ 1933721617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"4.rv_dm_stress_all.40685018087311328316117210234282344882470518611587233362680327389373499443736","seed":40685018087311328316117210234282344882470518611587233362680327389373499443736,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 231680283 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3483247662 [0xcf9e242e] vs 0 [0x0]) \n","UVM_INFO @ 231680283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"7.rv_dm_stress_all.61308903364597282432270987771653776280989714075066433428474210231729291727262","seed":61308903364597282432270987771653776280989714075066433428474210231729291727262,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 196968875 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1855199746 [0x6e941a02] vs 0 [0x0]) \n","UVM_INFO @ 196968875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"12.rv_dm_stress_all.66768164054217675365973538411859027807593916270263335050252437822082776913743","seed":66768164054217675365973538411859027807593916270263335050252437822082776913743,"line":84,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/12.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 4143436631 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1097203121 [0x4165fdb1] vs 0 [0x0]) \n","UVM_INFO @ 4143436631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"13.rv_dm_stress_all.1742274467541833997522644032117360569275456205805534044791131717159281196435","seed":1742274467541833997522644032117360569275456205805534044791131717159281196435,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/13.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 594685796 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (717478334 [0x2ac3d9be] vs 0 [0x0]) \n","UVM_INFO @ 594685796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"22.rv_dm_stress_all.101799838036254033415907350631887025696557515501136151832878617723611923866768","seed":101799838036254033415907350631887025696557515501136151832878617723611923866768,"line":81,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/22.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 877321117 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (4277491083 [0xfef5558b] vs 0 [0x0]) \n","UVM_INFO @ 877321117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"24.rv_dm_stress_all.109718048683684703166319581054908025120179282594301486967641985334853028866756","seed":109718048683684703166319581054908025120179282594301486967641985334853028866756,"line":81,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/24.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 2404839552 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (929869596 [0x376caf1c] vs 0 [0x0]) \n","UVM_INFO @ 2404839552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"25.rv_dm_stress_all.55121298738196013565958290373554032998911782320857777644864580618771891796119","seed":55121298738196013565958290373554032998911782320857777644864580618771891796119,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/25.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1329627131 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3556700449 [0xd3fef121] vs 0 [0x0]) \n","UVM_INFO @ 1329627131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"27.rv_dm_stress_all.52057900300844235611896434155338194339835113878024355559306811156459191453226","seed":52057900300844235611896434155338194339835113878024355559306811156459191453226,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/27.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 262567796 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2773107455 [0xa54a42ff] vs 0 [0x0]) \n","UVM_INFO @ 262567796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"28.rv_dm_stress_all.33824011107492608351056470819369340408652324567490890794594690306056744685290","seed":33824011107492608351056470819369340408652324567490890794594690306056744685290,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/28.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 131100515 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (388074371 [0x17218b83] vs 0 [0x0]) \n","UVM_INFO @ 131100515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"29.rv_dm_stress_all.115400347311988001970549843727607254561937177614462939864695985983718249432703","seed":115400347311988001970549843727607254561937177614462939864695985983718249432703,"line":84,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/29.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1288594476 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2937853250 [0xaf1c1542] vs 0 [0x0]) \n","UVM_INFO @ 1288594476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"31.rv_dm_stress_all.86596870368654959256641244368573746798877997264819691557443770534528653976529","seed":86596870368654959256641244368573746798877997264819691557443770534528653976529,"line":82,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/31.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1275756866 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1802518032 [0x6b703e10] vs 0 [0x0]) \n","UVM_INFO @ 1275756866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"36.rv_dm_stress_all.111987222912290969415915476825701384963847529131445805633255792558658293729837","seed":111987222912290969415915476825701384963847529131445805633255792558658293729837,"line":82,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/36.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1079146483 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3320849288 [0xc5f02388] vs 0 [0x0]) \n","UVM_INFO @ 1079146483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"41.rv_dm_stress_all.27791724334488180339267974288448763281406252078939837784765186538190381334282","seed":27791724334488180339267974288448763281406252078939837784765186538190381334282,"line":121,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/41.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 12551719936 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1999792509 [0x7732697d] vs 0 [0x0]) \n","UVM_INFO @ 12551719936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"49.rv_dm_stress_all.75989182084150968405054491169726827015128490708687568444618050842148101615102","seed":75989182084150968405054491169726827015128490708687568444618050842148101615102,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/49.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 700209900 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (481253418 [0x1caf582a] vs 0 [0x0]) \n","UVM_INFO @ 700209900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (cip_base_vseq.sv:1170) [rv_dm_common_vseq] Check failed (vseq_done)":[{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"0.rv_dm_stress_all_with_rand_reset.102527332739619632092908587321600147459873353856895592142401787140302396617923","seed":102527332739619632092908587321600147459873353856895592142401787140302396617923,"line":91,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 4393536311 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)  \n","UVM_INFO @ 4393536311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"2.rv_dm_stress_all_with_rand_reset.84907844260210916957865502826675822137367746247854975431345080036680024181350","seed":84907844260210916957865502826675822137367746247854975431345080036680024181350,"line":98,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 2908428143 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)  \n","UVM_INFO @ 2908428143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"6.rv_dm_stress_all_with_rand_reset.99527599396301054974849050568856156114732559740485070657157604027516434354205","seed":99527599396301054974849050568856156114732559740485070657157604027516434354205,"line":83,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 195362204 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)  \n","UVM_INFO @ 195362204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job timed out after * minutes":[{"name":"rv_dm_stress_all","qual_name":"1.rv_dm_stress_all.103347252013479814768531009964191993217265389090298735087435278052965076523329","seed":103347252013479814768531009964191993217265389090298735087435278052965076523329,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"rv_dm_stress_all","qual_name":"2.rv_dm_stress_all.112722869091310708040363063966768513728712355824764079642045627246884610009661","seed":112722869091310708040363063966768513728712355824764079642045627246884610009661,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log","log_context":["Job timed out after 180 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