{"block":{"name":"sram_ctrl","variant":"main","commit":"75f7d2fe44f2e3da01511f8d4f0a4c6e0cbbdd64","commit_short":"75f7d2f","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/75f7d2fe44f2e3da01511f8d4f0a4c6e0cbbdd64","revision_info":"GitHub Revision: [`75f7d2f`](https://github.com/lowrisc/opentitan/tree/75f7d2fe44f2e3da01511f8d4f0a4c6e0cbbdd64)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-04-18T10:17:21Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sram_ctrl_main/data/sram_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sram_ctrl_smoke":{"max_time":9.0,"sim_time":1445.837744,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_hw_reset":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":2.0,"sim_time":14.449768,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"sram_ctrl_csr_rw":{"max_time":2.0,"sim_time":84.05601399999999,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"sram_ctrl_csr_bit_bash":{"max_time":2.0,"sim_time":54.807778,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":80.22111,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sram_ctrl_csr_mem_rw_with_rand_reset":{"max_time":5.0,"sim_time":353.53798700000004,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sram_ctrl_csr_rw":{"max_time":2.0,"sim_time":84.05601399999999,"passed":20,"total":20,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":80.22111,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"mem_walk":{"tests":{"sram_ctrl_mem_walk":{"max_time":292.0,"sim_time":21104.566576,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"mem_partial_access":{"tests":{"sram_ctrl_mem_partial_access":{"max_time":118.0,"sim_time":4379.597672,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0}},"passed":70,"total":70,"percent":100.0},"V2":{"testpoints":{"multiple_keys":{"tests":{"sram_ctrl_multiple_keys":{"max_time":48.0,"sim_time":7721.257189,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"stress_pipeline":{"tests":{"sram_ctrl_stress_pipeline":{"max_time":330.0,"sim_time":51569.035561,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"bijection":{"tests":{"sram_ctrl_bijection":{"max_time":178.0,"sim_time":17977.492795000002,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"access_during_key_req":{"tests":{"sram_ctrl_access_during_key_req":{"max_time":82.0,"sim_time":69398.64778300001,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"lc_escalation":{"tests":{"sram_ctrl_lc_escalation":{"max_time":71.0,"sim_time":28189.683022,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"executable":{"tests":{"sram_ctrl_executable":{"max_time":45.0,"sim_time":75578.338983,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"partial_access":{"tests":{"sram_ctrl_partial_access":{"max_time":7.0,"sim_time":2792.060795,"passed":5,"total":5,"percent":100.0},"sram_ctrl_partial_access_b2b":{"max_time":419.0,"sim_time":24354.450463,"passed":5,"total":5,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"max_throughput":{"tests":{"sram_ctrl_max_throughput":{"max_time":8.0,"sim_time":4103.884217,"passed":0,"total":5,"percent":0.0},"sram_ctrl_throughput_w_partial_write":{"max_time":7.0,"sim_time":706.5844549999999,"passed":5,"total":5,"percent":100.0},"sram_ctrl_throughput_w_readback":{"max_time":7.0,"sim_time":2739.415218,"passed":0,"total":5,"percent":0.0}},"passed":5,"total":15,"percent":33.333333333333336},"regwen":{"tests":{"sram_ctrl_regwen":{"max_time":19.0,"sim_time":11955.144832,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"ram_cfg":{"tests":{"sram_ctrl_ram_cfg":{"max_time":5.0,"sim_time":993.876441,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"stress_all":{"tests":{"sram_ctrl_stress_all":{"max_time":772.0,"sim_time":1420492.55533,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"alert_test":{"tests":{"sram_ctrl_alert_test":{"max_time":2.0,"sim_time":24.949464,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sram_ctrl_tl_errors":{"max_time":5.0,"sim_time":1565.205111,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"sram_ctrl_tl_errors":{"max_time":5.0,"sim_time":1565.205111,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":2.0,"sim_time":14.449768,"passed":5,"total":5,"percent":100.0},"sram_ctrl_csr_rw":{"max_time":2.0,"sim_time":84.05601399999999,"passed":20,"total":20,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":80.22111,"passed":5,"total":5,"percent":100.0},"sram_ctrl_same_csr_outstanding":{"max_time":2.0,"sim_time":12.859221999999999,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":2.0,"sim_time":14.449768,"passed":5,"total":5,"percent":100.0},"sram_ctrl_csr_rw":{"max_time":2.0,"sim_time":84.05601399999999,"passed":20,"total":20,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":80.22111,"passed":5,"total":5,"percent":100.0},"sram_ctrl_same_csr_outstanding":{"max_time":2.0,"sim_time":12.859221999999999,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":180,"total":190,"percent":94.73684210526316},"V2S":{"testpoints":{"passthru_mem_tl_intg_err":{"tests":{"sram_ctrl_passthru_mem_tl_intg_err":{"max_time":40.0,"sim_time":7083.854837,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_intg_err":{"tests":{"sram_ctrl_tl_intg_err":{"max_time":3.0,"sim_time":285.478937,"passed":20,"total":20,"percent":100.0},"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":3441.632697,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"prim_count_check":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":3441.632697,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"sram_ctrl_tl_intg_err":{"max_time":3.0,"sim_time":285.478937,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_ctrl_config_regwen":{"tests":{"sram_ctrl_regwen":{"max_time":19.0,"sim_time":11955.144832,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_readback_config_regwen":{"tests":{"sram_ctrl_regwen":{"max_time":19.0,"sim_time":11955.144832,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_exec_config_regwen":{"tests":{"sram_ctrl_csr_rw":{"max_time":2.0,"sim_time":84.05601399999999,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_exec_config_mubi":{"tests":{"sram_ctrl_executable":{"max_time":45.0,"sim_time":75578.338983,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_exec_intersig_mubi":{"tests":{"sram_ctrl_executable":{"max_time":45.0,"sim_time":75578.338983,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_lc_hw_debug_en_intersig_mubi":{"tests":{"sram_ctrl_executable":{"max_time":45.0,"sim_time":75578.338983,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_lc_escalate_en_intersig_mubi":{"tests":{"sram_ctrl_lc_escalation":{"max_time":71.0,"sim_time":28189.683022,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_prim_ram_ctrl_mubi":{"tests":{"sram_ctrl_mubi_enc_err":{"max_time":6.0,"sim_time":4146.153598,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_mem_integrity":{"tests":{"sram_ctrl_passthru_mem_tl_intg_err":{"max_time":40.0,"sim_time":7083.854837,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_mem_readback":{"tests":{"sram_ctrl_readback_err":{"max_time":7.0,"sim_time":2895.905139,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_mem_scramble":{"tests":{"sram_ctrl_smoke":{"max_time":9.0,"sim_time":1445.837744,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_addr_scramble":{"tests":{"sram_ctrl_smoke":{"max_time":9.0,"sim_time":1445.837744,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_instr_bus_lc_gated":{"tests":{"sram_ctrl_executable":{"max_time":45.0,"sim_time":75578.338983,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ram_tl_lc_gate_fsm_sparse":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":3441.632697,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_key_global_esc":{"tests":{"sram_ctrl_lc_escalation":{"max_time":71.0,"sim_time":28189.683022,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_key_local_esc":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":3441.632697,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_init_ctr_redun":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":3441.632697,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_scramble_key_sideload":{"tests":{"sram_ctrl_smoke":{"max_time":9.0,"sim_time":1445.837744,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_tlul_fifo_ctr_redun":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":3441.632697,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0}},"passed":95,"total":95,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sram_ctrl_stress_all_with_rand_reset":{"max_time":38.0,"sim_time":6801.24186,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0}},"coverage":{"code":{"block":96.35,"line_statement":97.11,"branch":94.65,"condition_expression":null,"toggle":96.09,"fsm":100.0},"assertion":96.46,"functional":96.6},"cov_report_page":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cov_report/index.html","failed_jobs":{"buckets":{"UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!":[{"name":"sram_ctrl_max_throughput","qual_name":"0.sram_ctrl_max_throughput.68696206746037333552235636427782865837207682467628898499322153427761100992557","seed":68696206746037333552235636427782865837207682467628898499322153427761100992557,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_FATAL @ 1369273442 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2;         mask dist {'1 :/ 100 - partial_access_pct,                    [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! \n","UVM_INFO @ 1369273442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"0.sram_ctrl_throughput_w_readback.111317058899185940837463097816145041347180416012759260224361072772855305252374","seed":111317058899185940837463097816145041347180416012759260224361072772855305252374,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_FATAL @ 3886343922 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2;         mask dist {'1 :/ 100 - partial_access_pct,                    [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! \n","UVM_INFO @ 3886343922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_max_throughput","qual_name":"1.sram_ctrl_max_throughput.32146395185037174974999658602264770343394750623162272493063872316601371127509","seed":32146395185037174974999658602264770343394750623162272493063872316601371127509,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_FATAL @ 1340591347 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2;         mask dist {'1 :/ 100 - partial_access_pct,                    [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! \n","UVM_INFO @ 1340591347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"1.sram_ctrl_throughput_w_readback.31305682703482349512768294129300123264096649076858756817503544957163975260289","seed":31305682703482349512768294129300123264096649076858756817503544957163975260289,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_FATAL @ 2739415218 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2;         mask dist {'1 :/ 100 - partial_access_pct,                    [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! \n","UVM_INFO @ 2739415218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_max_throughput","qual_name":"2.sram_ctrl_max_throughput.91126330623625549167117158551795103161360891936955803205939341611052084013049","seed":91126330623625549167117158551795103161360891936955803205939341611052084013049,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_FATAL @ 666462141 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2;         mask dist {'1 :/ 100 - partial_access_pct,                    [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! \n","UVM_INFO @ 666462141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"2.sram_ctrl_throughput_w_readback.39435353262625792835129411224653547861584895827626829542854101015522419108396","seed":39435353262625792835129411224653547861584895827626829542854101015522419108396,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_FATAL @ 691230649 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2;         mask dist {'1 :/ 100 - partial_access_pct,                    [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! \n","UVM_INFO @ 691230649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_max_throughput","qual_name":"3.sram_ctrl_max_throughput.13555968893095654353227868329831578158288335611180988645562736956029306264538","seed":13555968893095654353227868329831578158288335611180988645562736956029306264538,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_FATAL @ 4103884217 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2;         mask dist {'1 :/ 100 - partial_access_pct,                    [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! \n","UVM_INFO @ 4103884217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"3.sram_ctrl_throughput_w_readback.22807898178077311874336869280982688939957663818531106812821933141049306368181","seed":22807898178077311874336869280982688939957663818531106812821933141049306368181,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_FATAL @ 670398863 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2;         mask dist {'1 :/ 100 - partial_access_pct,                    [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! \n","UVM_INFO @ 670398863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_max_throughput","qual_name":"4.sram_ctrl_max_throughput.4129916231614638388679743369285232454121322037174740211217183959443108207590","seed":4129916231614638388679743369285232454121322037174740211217183959443108207590,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_FATAL @ 691712006 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2;         mask dist {'1 :/ 100 - partial_access_pct,                    [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! \n","UVM_INFO @ 691712006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"4.sram_ctrl_throughput_w_readback.46909314072438252679967591884223606215135730735897976303113995989801016465386","seed":46909314072438252679967591884223606215135730735897976303113995989801016465386,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_FATAL @ 925507466 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2;         mask dist {'1 :/ 100 - partial_access_pct,                    [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! \n","UVM_INFO @ 925507466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":280,"total":290,"percent":96.55172413793103}