{"block":{"name":"alert_handler","variant":null,"commit":"5b8f6746131e231116e685585432b70359d2c727","commit_short":"5b8f674","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/5b8f6746131e231116e685585432b70359d2c727","revision_info":"GitHub Revision: [`5b8f674`](https://github.com/lowrisc/opentitan/tree/5b8f6746131e231116e685585432b70359d2c727)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-19T03:35:48Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_darjeeling/ip_autogen/alert_handler/data/alert_handler_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"alert_handler_smoke":{"max_time":83.33,"sim_time":4970.081999,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"alert_handler_csr_hw_reset":{"max_time":10.89,"sim_time":132.35547,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"alert_handler_csr_rw":{"max_time":10.59,"sim_time":211.458463,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"alert_handler_csr_bit_bash":{"max_time":405.63,"sim_time":40447.342257,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"alert_handler_csr_aliasing":{"max_time":286.76,"sim_time":19074.297838,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"alert_handler_csr_mem_rw_with_rand_reset":{"max_time":12.9,"sim_time":145.091272,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"alert_handler_csr_rw":{"max_time":10.59,"sim_time":211.458463,"passed":20,"total":20,"percent":100.0},"alert_handler_csr_aliasing":{"max_time":286.76,"sim_time":19074.297838,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":105,"total":105,"percent":100.0},"V2":{"testpoints":{"esc_accum":{"tests":{"alert_handler_esc_alert_accum":{"max_time":400.23,"sim_time":22897.695263999998,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"esc_timeout":{"tests":{"alert_handler_esc_intr_timeout":{"max_time":80.43,"sim_time":1206.218623,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"entropy":{"tests":{"alert_handler_entropy":{"max_time":3264.96,"sim_time":937775.670326,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sig_int_fail":{"tests":{"alert_handler_sig_int_fail":{"max_time":73.52,"sim_time":4285.876892,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0},"clk_skew":{"tests":{"alert_handler_smoke":{"max_time":83.33,"sim_time":4970.081999,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"random_alerts":{"tests":{"alert_handler_random_alerts":{"max_time":86.49,"sim_time":2607.120381,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"random_classes":{"tests":{"alert_handler_random_classes":{"max_time":98.16,"sim_time":1491.043551,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"ping_timeout":{"tests":{"alert_handler_ping_timeout":{"max_time":600.28,"sim_time":56998.48521,"passed":18,"total":50,"percent":36.0}},"passed":18,"total":50,"percent":36.0},"lpg":{"tests":{"alert_handler_lpg":{"max_time":3091.02,"sim_time":66004.24686,"passed":49,"total":50,"percent":98.0},"alert_handler_lpg_stub_clk":{"max_time":2928.95,"sim_time":438246.474461,"passed":49,"total":50,"percent":98.0}},"passed":98,"total":100,"percent":98.0},"stress_all":{"tests":{"alert_handler_stress_all":{"max_time":3653.28,"sim_time":375509.84128,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"alert_handler_entropy_stress_test":{"tests":{"alert_handler_entropy_stress":{"max_time":105.98,"sim_time":11410.513154999999,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"alert_handler_alert_accum_saturation":{"tests":{"alert_handler_alert_accum_saturation":{"max_time":6.4,"sim_time":63.583434000000004,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"intr_test":{"tests":{"alert_handler_intr_test":{"max_time":3.36,"sim_time":72.44471,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"alert_handler_tl_errors":{"max_time":24.28,"sim_time":297.54125,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"alert_handler_tl_errors":{"max_time":24.28,"sim_time":297.54125,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"alert_handler_csr_hw_reset":{"max_time":10.89,"sim_time":132.35547,"passed":5,"total":5,"percent":100.0},"alert_handler_csr_rw":{"max_time":10.59,"sim_time":211.458463,"passed":20,"total":20,"percent":100.0},"alert_handler_csr_aliasing":{"max_time":286.76,"sim_time":19074.297838,"passed":5,"total":5,"percent":100.0},"alert_handler_same_csr_outstanding":{"max_time":50.45,"sim_time":1152.276139,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"alert_handler_csr_hw_reset":{"max_time":10.89,"sim_time":132.35547,"passed":5,"total":5,"percent":100.0},"alert_handler_csr_rw":{"max_time":10.59,"sim_time":211.458463,"passed":20,"total":20,"percent":100.0},"alert_handler_csr_aliasing":{"max_time":286.76,"sim_time":19074.297838,"passed":5,"total":5,"percent":100.0},"alert_handler_same_csr_outstanding":{"max_time":50.45,"sim_time":1152.276139,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":675,"total":710,"percent":95.07042253521126},"V2S":{"testpoints":{"shadow_reg_update_error":{"tests":{"alert_handler_shadow_reg_errors":{"max_time":354.1,"sim_time":29036.352199999998,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_read_clear_staged_value":{"tests":{"alert_handler_shadow_reg_errors":{"max_time":354.1,"sim_time":29036.352199999998,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_storage_error":{"tests":{"alert_handler_shadow_reg_errors":{"max_time":354.1,"sim_time":29036.352199999998,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadowed_reset_glitch":{"tests":{"alert_handler_shadow_reg_errors":{"max_time":354.1,"sim_time":29036.352199999998,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_update_error_with_csr_rw":{"tests":{"alert_handler_shadow_reg_errors_with_csr_rw":{"max_time":1478.86,"sim_time":19104.634021,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_intg_err":{"tests":{"alert_handler_tl_intg_err":{"max_time":100.72,"sim_time":3035.5667599999997,"passed":20,"total":20,"percent":100.0},"alert_handler_sec_cm":{"max_time":30.56,"sim_time":484.241757,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"alert_handler_tl_intg_err":{"max_time":100.72,"sim_time":3035.5667599999997,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_config_shadow":{"tests":{"alert_handler_shadow_reg_errors":{"max_time":354.1,"sim_time":29036.352199999998,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_ping_timer_config_regwen":{"tests":{"alert_handler_smoke":{"max_time":83.33,"sim_time":4970.081999,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_alert_config_regwen":{"tests":{"alert_handler_smoke":{"max_time":83.33,"sim_time":4970.081999,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_alert_loc_config_regwen":{"tests":{"alert_handler_smoke":{"max_time":83.33,"sim_time":4970.081999,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_class_config_regwen":{"tests":{"alert_handler_smoke":{"max_time":83.33,"sim_time":4970.081999,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_alert_intersig_diff":{"tests":{"alert_handler_sig_int_fail":{"max_time":73.52,"sim_time":4285.876892,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0},"sec_cm_lpg_intersig_mubi":{"tests":{"alert_handler_lpg":{"max_time":3091.02,"sim_time":66004.24686,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0},"sec_cm_esc_intersig_diff":{"tests":{"alert_handler_sig_int_fail":{"max_time":73.52,"sim_time":4285.876892,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0},"sec_cm_alert_rx_intersig_bkgn_chk":{"tests":{"alert_handler_entropy":{"max_time":3264.96,"sim_time":937775.670326,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_esc_tx_intersig_bkgn_chk":{"tests":{"alert_handler_entropy":{"max_time":3264.96,"sim_time":937775.670326,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_esc_timer_fsm_sparse":{"tests":{"alert_handler_sec_cm":{"max_time":30.56,"sim_time":484.241757,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ping_timer_fsm_sparse":{"tests":{"alert_handler_sec_cm":{"max_time":30.56,"sim_time":484.241757,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_esc_timer_fsm_local_esc":{"tests":{"alert_handler_sec_cm":{"max_time":30.56,"sim_time":484.241757,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ping_timer_fsm_local_esc":{"tests":{"alert_handler_sec_cm":{"max_time":30.56,"sim_time":484.241757,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_esc_timer_fsm_global_esc":{"tests":{"alert_handler_sec_cm":{"max_time":30.56,"sim_time":484.241757,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_accu_ctr_redun":{"tests":{"alert_handler_sec_cm":{"max_time":30.56,"sim_time":484.241757,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_esc_timer_ctr_redun":{"tests":{"alert_handler_sec_cm":{"max_time":30.56,"sim_time":484.241757,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ping_timer_ctr_redun":{"tests":{"alert_handler_sec_cm":{"max_time":30.56,"sim_time":484.241757,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ping_timer_lfsr_redun":{"tests":{"alert_handler_sec_cm":{"max_time":30.56,"sim_time":484.241757,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0}},"passed":263,"total":265,"percent":99.24528301886792},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"alert_handler_stress_all_with_rand_reset":{"max_time":735.93,"sim_time":69905.05275300001,"passed":31,"total":50,"percent":62.0}},"passed":31,"total":50,"percent":62.0}},"passed":31,"total":50,"percent":62.0}},"coverage":{"code":{"block":null,"line_statement":99.99,"branch":99.99,"condition_expression":97.49,"toggle":97.37,"fsm":100.0},"assertion":98.92,"functional":99.32},"cov_report_page":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state":[{"name":"alert_handler_ping_timeout","qual_name":"0.alert_handler_ping_timeout.107352205367229785883013639479530037799022046125014118611405355118070403254070","seed":107352205367229785883013639479530037799022046125014118611405355118070403254070,"line":167,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 22106490346 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 22106490346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"1.alert_handler_ping_timeout.91541990429826168740007922972147189099008584526161381922823952441630685467527","seed":91541990429826168740007922972147189099008584526161381922823952441630685467527,"line":87,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 825868027 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 825868027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"3.alert_handler_ping_timeout.51313779389554698659924765598801943606762070232075530183682409102464951876386","seed":51313779389554698659924765598801943606762070232075530183682409102464951876386,"line":108,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 86102634223 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 86102634223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"4.alert_handler_ping_timeout.76697781135487089344089949498453615789066183248944301259242259896091659995733","seed":76697781135487089344089949498453615789066183248944301259242259896091659995733,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 2234918794 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 2234918794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"5.alert_handler_ping_timeout.20891288792436931557304212760193645370971125139246486105074204325582659800320","seed":20891288792436931557304212760193645370971125139246486105074204325582659800320,"line":87,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 5873405482 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 5873405482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"6.alert_handler_ping_timeout.109256528863831247051932814558601068303414719040550633270950925754515894296461","seed":109256528863831247051932814558601068303414719040550633270950925754515894296461,"line":114,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 6408917601 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 6408917601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"11.alert_handler_ping_timeout.23306744016532895987286024375726013327644721709603790854419039331823849260612","seed":23306744016532895987286024375726013327644721709603790854419039331823849260612,"line":87,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 2616494273 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 2616494273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"14.alert_handler_ping_timeout.111987398716392230080036496510098159647281066292871000478077445498631635917992","seed":111987398716392230080036496510098159647281066292871000478077445498631635917992,"line":96,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 5624690459 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 5624690459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"15.alert_handler_ping_timeout.94631040345441264327021608787449410333458231944814770394600972705861892476898","seed":94631040345441264327021608787449410333458231944814770394600972705861892476898,"line":97,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 15151558314 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 15151558314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"20.alert_handler_ping_timeout.106187133455432329175682050531643989131667959704385375710481136801022797701144","seed":106187133455432329175682050531643989131667959704385375710481136801022797701144,"line":90,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 2568849644 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 2568849644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"22.alert_handler_ping_timeout.51580459104615618550784275711208804243151897074431869455192638950731734238864","seed":51580459104615618550784275711208804243151897074431869455192638950731734238864,"line":93,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 2223231841 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 2223231841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"23.alert_handler_ping_timeout.53503044879870996152226287645024110984132318008195243142707242333265931972307","seed":53503044879870996152226287645024110984132318008195243142707242333265931972307,"line":116,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 23155104164 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 23155104164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"24.alert_handler_ping_timeout.68609247590294464084010904897903701665532083648091709926505302745178845042540","seed":68609247590294464084010904897903701665532083648091709926505302745178845042540,"line":102,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 15034961401 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 15034961401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"26.alert_handler_ping_timeout.87082658366871709416707334201000376367439625639026507710830512430001956576441","seed":87082658366871709416707334201000376367439625639026507710830512430001956576441,"line":102,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 2853271319 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 2853271319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"27.alert_handler_ping_timeout.75318341232250303692933362758870540225426969715788237765342755914463239343488","seed":75318341232250303692933362758870540225426969715788237765342755914463239343488,"line":94,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 2830514088 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 2830514088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"28.alert_handler_ping_timeout.10557199710195882229299822951317838633106185085440144306884842971596360494086","seed":10557199710195882229299822951317838633106185085440144306884842971596360494086,"line":123,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 6277769655 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 6277769655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"31.alert_handler_ping_timeout.80926629388377774111416546472702643672316449782452279322203097203952379720065","seed":80926629388377774111416546472702643672316449782452279322203097203952379720065,"line":111,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/31.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 10571143982 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 10571143982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"33.alert_handler_ping_timeout.41922428001099411901689854657577491209642374760113394937751721682193457718051","seed":41922428001099411901689854657577491209642374760113394937751721682193457718051,"line":103,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 14175039037 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 14175039037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"34.alert_handler_ping_timeout.76055863398469296557123422454643016514768124129244056636174162534400483541325","seed":76055863398469296557123422454643016514768124129244056636174162534400483541325,"line":96,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 4858355164 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 4858355164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"36.alert_handler_ping_timeout.115670032534221394471783397336890292092165179703889396674757204233668662618517","seed":115670032534221394471783397336890292092165179703889396674757204233668662618517,"line":135,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/36.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 15463494889 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 15463494889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"38.alert_handler_ping_timeout.79582671170288572362329472188636742377951614543467657538074902781418141312406","seed":79582671170288572362329472188636742377951614543467657538074902781418141312406,"line":142,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 30520903356 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 30520903356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"40.alert_handler_ping_timeout.115533004253857944302539283378198486822512927349486653616315229977565212499415","seed":115533004253857944302539283378198486822512927349486653616315229977565212499415,"line":90,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 2247643485 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 2247643485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"41.alert_handler_ping_timeout.104476404678097559800937551616938322114095531309956680622609386634655662221988","seed":104476404678097559800937551616938322114095531309956680622609386634655662221988,"line":108,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 3457092887 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 3457092887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"43.alert_handler_ping_timeout.30944786661634610389473027932039205313789624169999625813135733568055096394960","seed":30944786661634610389473027932039205313789624169999625813135733568055096394960,"line":90,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/43.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 4267369203 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 4267369203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"47.alert_handler_ping_timeout.50553832127076313675684020216180918153104578643950128622836465483882505185352","seed":50553832127076313675684020216180918153104578643950128622836465483882505185352,"line":131,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 6974485425 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 6974485425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"49.alert_handler_ping_timeout.80334754574264973340772189581790814464207936098138296014434585951754700467829","seed":80334754574264973340772189581790814464207936098138296014434585951754700467829,"line":87,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 1106475491 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 1106475491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"0.alert_handler_stress_all_with_rand_reset.89335039485161048987474050753155158737089122805353679342766426652657005580975","seed":89335039485161048987474050753155158737089122805353679342766426652657005580975,"line":119,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3950549649 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3950549649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"6.alert_handler_stress_all_with_rand_reset.11585270969297407574451060510194396229318749567261350167923480701032976078643","seed":11585270969297407574451060510194396229318749567261350167923480701032976078643,"line":93,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 874933712 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 874933712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"11.alert_handler_stress_all_with_rand_reset.43621276091670095576977320985325424929967935703311564721557698774361524895690","seed":43621276091670095576977320985325424929967935703311564721557698774361524895690,"line":177,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2731788789 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2731788789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"17.alert_handler_stress_all_with_rand_reset.113761492513159894916932831254096302671244754935537421414464769127260322577894","seed":113761492513159894916932831254096302671244754935537421414464769127260322577894,"line":83,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 163230039 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 163230039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"18.alert_handler_stress_all_with_rand_reset.111482821891150765636943263626675438950227611022354252333453648350712009272630","seed":111482821891150765636943263626675438950227611022354252333453648350712009272630,"line":201,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 15996635117 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 15996635117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"19.alert_handler_stress_all_with_rand_reset.42591330055339865241573211396452605800293095289609481926947460852441746627926","seed":42591330055339865241573211396452605800293095289609481926947460852441746627926,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 219561868 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 219561868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"22.alert_handler_stress_all_with_rand_reset.53571953825181106110349933363523833832523039897012342164106010117372674861564","seed":53571953825181106110349933363523833832523039897012342164106010117372674861564,"line":87,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 923534622 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 923534622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"28.alert_handler_stress_all_with_rand_reset.78458411835758088734895838447935778373146617254029457994143392776669215761792","seed":78458411835758088734895838447935778373146617254029457994143392776669215761792,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/28.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 124129992 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 124129992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"31.alert_handler_stress_all_with_rand_reset.92642162128842340197351189357488979441456151366074070445022473206226106862157","seed":92642162128842340197351189357488979441456151366074070445022473206226106862157,"line":116,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1116232514 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1116232514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"37.alert_handler_stress_all_with_rand_reset.81442311877767568470606849409912181774596389405594077111462362554323979676267","seed":81442311877767568470606849409912181774596389405594077111462362554323979676267,"line":164,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/37.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 10237588880 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 10237588880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"40.alert_handler_stress_all_with_rand_reset.68969117140070983719685433313890625315948983777197798447320386930092967505264","seed":68969117140070983719685433313890625315948983777197798447320386930092967505264,"line":155,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 11225316597 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 11225316597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"43.alert_handler_stress_all_with_rand_reset.99707186285209477377560367951410017032715077059084300082694213268991750923878","seed":99707186285209477377560367951410017032715077059084300082694213268991750923878,"line":118,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/43.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4902916066 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4902916066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"44.alert_handler_stress_all_with_rand_reset.22937577088058835601552350685675470935607581135288276545886600331595521350244","seed":22937577088058835601552350685675470935607581135288276545886600331595521350244,"line":101,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/44.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 882326418 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 882326418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"46.alert_handler_stress_all_with_rand_reset.64513583751210421397460325060374681064516769623921081904100149148051407944651","seed":64513583751210421397460325060374681064516769623921081904100149148051407944651,"line":114,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3057170756 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3057170756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"47.alert_handler_stress_all_with_rand_reset.98044321657132052429120977178916170588869561679850697679786204386331147718186","seed":98044321657132052429120977178916170588869561679850697679786204386331147718186,"line":103,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/47.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1058708408 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1058708408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"48.alert_handler_stress_all_with_rand_reset.34524606273609472166033766270821993843404053035937847480027522152737496119027","seed":34524606273609472166033766270821993843404053035937847480027522152737496119027,"line":145,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/48.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5049919367 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5049919367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:847) [alert_handler_sig_int_fail_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])":[{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"8.alert_handler_stress_all_with_rand_reset.31960950975565016307770445431860375989863763008131427270371395493148309494677","seed":31960950975565016307770445431860375989863763008131427270371395493148309494677,"line":109,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1111675195 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.alert_handler_sig_int_fail_vseq] Check failed data & ~ro_mask == 0 (2 [0x2] vs 0 [0x0]) \n","UVM_INFO @ 1111675195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1149) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.":[{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"10.alert_handler_stress_all_with_rand_reset.104760074806496056007158068286043477313519037976327129926897797721093356319826","seed":104760074806496056007158068286043477313519037976327129926897797721093356319826,"line":124,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1965281672 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1965281672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"34.alert_handler_stress_all_with_rand_reset.68358381836887597703461029774878438143669678965270051106232817825803570435568","seed":68358381836887597703461029774878438143669678965270051106232817825803570435568,"line":359,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/34.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 90194008451 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 90194008451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model.":[{"name":"alert_handler_ping_timeout","qual_name":"16.alert_handler_ping_timeout.111050984528499767969201803650816718197942191466184579836460897808145724436922","seed":111050984528499767969201803650816718197942191466184579836460897808145724436922,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 1259327176 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 1259327176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"17.alert_handler_ping_timeout.101088845129824463174937017948947376854874400961703626224201098379926198536565","seed":101088845129824463174937017948947376854874400961703626224201098379926198536565,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 3441886726 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 3441886726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"18.alert_handler_ping_timeout.102646955932146080879034473249900164512553489563200420476963495952086873969939","seed":102646955932146080879034473249900164512553489563200420476963495952086873969939,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 410301590 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 410301590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_lpg","qual_name":"19.alert_handler_lpg.26183014514739391557773168915922145385768487609797715213695097253429330473839","seed":26183014514739391557773168915922145385768487609797715213695097253429330473839,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_lpg/latest/run.log","log_context":["UVM_ERROR @ 16650627771 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 16650627771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"32.alert_handler_ping_timeout.108599567197991420728717891016737804721530564486291150613979691746348726510813","seed":108599567197991420728717891016737804721530564486291150613979691746348726510813,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 923486261 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 923486261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"35.alert_handler_ping_timeout.16916553410638321027771311042183047376911547327777386728526393033745396371723","seed":16916553410638321027771311042183047376911547327777386728526393033745396371723,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 740089281 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 740089281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"48.alert_handler_ping_timeout.62002193688715575904910970272845440581137744572544517933035878336746767688105","seed":62002193688715575904910970272845440581137744572544517933035878336746767688105,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/48.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @  98452329 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @  98452329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalEscIntFail)":[{"name":"alert_handler_sig_int_fail","qual_name":"27.alert_handler_sig_int_fail.31463645161332753541385725418889743410951009118841408566607013902629098792094","seed":31463645161332753541385725418889743410951009118841408566607013902629098792094,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_sig_int_fail/latest/run.log","log_context":["UVM_ERROR @ 178581010 ps: (alert_handler_scoreboard.sv:258) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[3]: saw 0, but expected 1. (is_int_err = 1, local_alert_type = LocalEscIntFail)\n","UVM_INFO @ 178581010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalAlertIntFail)":[{"name":"alert_handler_lpg_stub_clk","qual_name":"36.alert_handler_lpg_stub_clk.102220123053266207154030553269693171425724342615708940575518789151511848532207","seed":102220123053266207154030553269693171425724342615708940575518789151511848532207,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/36.alert_handler_lpg_stub_clk/latest/run.log","log_context":["UVM_ERROR @ 33861897939 ps: (alert_handler_scoreboard.sv:258) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[3]: saw 0, but expected 1. (is_int_err = 0, local_alert_type = LocalAlertIntFail)\n","UVM_INFO @ 33861897939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":796,"total":850,"percent":93.6470588235294}