{"block":{"name":"edn","variant":"edn0","commit":"5b8f6746131e231116e685585432b70359d2c727","commit_short":"5b8f674","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/5b8f6746131e231116e685585432b70359d2c727","revision_info":"GitHub Revision: [`5b8f674`](https://github.com/lowrisc/opentitan/tree/5b8f6746131e231116e685585432b70359d2c727)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-19T03:35:48Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/edn_edn0/data/edn_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"edn_smoke":{"max_time":1.39,"sim_time":29.574721,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"edn_csr_hw_reset":{"max_time":1.2,"sim_time":27.687199,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"edn_csr_rw":{"max_time":1.24,"sim_time":13.121243,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"edn_csr_bit_bash":{"max_time":6.37,"sim_time":1043.7164930000001,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"edn_csr_aliasing":{"max_time":1.89,"sim_time":38.056506,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"edn_csr_mem_rw_with_rand_reset":{"max_time":2.03,"sim_time":111.388075,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"edn_csr_rw":{"max_time":1.24,"sim_time":13.121243,"passed":20,"total":20,"percent":100.0},"edn_csr_aliasing":{"max_time":1.89,"sim_time":38.056506,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":105,"total":105,"percent":100.0},"V2":{"testpoints":{"firmware":{"tests":{"edn_genbits":{"max_time":4.42,"sim_time":881.466508,"passed":300,"total":300,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"csrng_commands":{"tests":{"edn_genbits":{"max_time":4.42,"sim_time":881.466508,"passed":300,"total":300,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"genbits":{"tests":{"edn_genbits":{"max_time":4.42,"sim_time":881.466508,"passed":300,"total":300,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"interrupts":{"tests":{"edn_intr":{"max_time":1.61,"sim_time":20.764155,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"alerts":{"tests":{"edn_alert":{"max_time":1.77,"sim_time":58.458375,"passed":200,"total":200,"percent":100.0}},"passed":200,"total":200,"percent":100.0},"errs":{"tests":{"edn_err":{"max_time":1.57,"sim_time":21.847082999999998,"passed":100,"total":100,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"disable":{"tests":{"edn_disable":{"max_time":1.34,"sim_time":15.404050999999999,"passed":50,"total":50,"percent":100.0},"edn_disable_auto_req_mode":{"max_time":8.72,"sim_time":500.0,"passed":40,"total":50,"percent":80.0}},"passed":90,"total":100,"percent":90.0},"stress_all":{"tests":{"edn_stress_all":{"max_time":5.77,"sim_time":308.92805400000003,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"edn_intr_test":{"max_time":1.25,"sim_time":12.000029,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"alert_test":{"tests":{"edn_alert_test":{"max_time":1.4,"sim_time":71.308624,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"edn_tl_errors":{"max_time":4.01,"sim_time":165.980403,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"edn_tl_errors":{"max_time":4.01,"sim_time":165.980403,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"edn_csr_hw_reset":{"max_time":1.2,"sim_time":27.687199,"passed":5,"total":5,"percent":100.0},"edn_csr_rw":{"max_time":1.24,"sim_time":13.121243,"passed":20,"total":20,"percent":100.0},"edn_csr_aliasing":{"max_time":1.89,"sim_time":38.056506,"passed":5,"total":5,"percent":100.0},"edn_same_csr_outstanding":{"max_time":1.79,"sim_time":31.514892,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"edn_csr_hw_reset":{"max_time":1.2,"sim_time":27.687199,"passed":5,"total":5,"percent":100.0},"edn_csr_rw":{"max_time":1.24,"sim_time":13.121243,"passed":20,"total":20,"percent":100.0},"edn_csr_aliasing":{"max_time":1.89,"sim_time":38.056506,"passed":5,"total":5,"percent":100.0},"edn_same_csr_outstanding":{"max_time":1.79,"sim_time":31.514892,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":960,"total":970,"percent":98.96907216494846},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"edn_tl_intg_err":{"max_time":3.75,"sim_time":430.39941,"passed":20,"total":20,"percent":100.0},"edn_sec_cm":{"max_time":8.45,"sim_time":741.1515949999999,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_config_regwen":{"tests":{"edn_regwen":{"max_time":1.07,"sim_time":16.084421,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sec_cm_config_mubi":{"tests":{"edn_alert":{"max_time":1.77,"sim_time":58.458375,"passed":200,"total":200,"percent":100.0}},"passed":200,"total":200,"percent":100.0},"sec_cm_main_sm_fsm_sparse":{"tests":{"edn_sec_cm":{"max_time":8.45,"sim_time":741.1515949999999,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ack_sm_fsm_sparse":{"tests":{"edn_sec_cm":{"max_time":8.45,"sim_time":741.1515949999999,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_fifo_ctr_redun":{"tests":{"edn_sec_cm":{"max_time":8.45,"sim_time":741.1515949999999,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ctr_redun":{"tests":{"edn_sec_cm":{"max_time":8.45,"sim_time":741.1515949999999,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_main_sm_ctr_local_esc":{"tests":{"edn_alert":{"max_time":1.77,"sim_time":58.458375,"passed":200,"total":200,"percent":100.0},"edn_sec_cm":{"max_time":8.45,"sim_time":741.1515949999999,"passed":5,"total":5,"percent":100.0}},"passed":205,"total":205,"percent":100.0},"sec_cm_cs_rdata_bus_consistency":{"tests":{"edn_alert":{"max_time":1.77,"sim_time":58.458375,"passed":200,"total":200,"percent":100.0}},"passed":200,"total":200,"percent":100.0},"sec_cm_tile_link_bus_integrity":{"tests":{"edn_tl_intg_err":{"max_time":3.75,"sim_time":430.39941,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0}},"passed":235,"total":235,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"edn_stress_all_with_rand_reset":{"max_time":109.36,"sim_time":10175.952051,"passed":44,"total":50,"percent":88.0}},"passed":44,"total":50,"percent":88.0}},"passed":44,"total":50,"percent":88.0}},"coverage":{"code":{"block":null,"line_statement":98.91,"branch":96.51,"condition_expression":94.08,"toggle":97.12,"fsm":91.94},"assertion":97.61,"functional":92.66},"cov_report_page":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"edn_disable_auto_req_mode","qual_name":"1.edn_disable_auto_req_mode.30087658006659625948243067963260123888902666699267363361309687687329482919529","seed":30087658006659625948243067963260123888902666699267363361309687687329482919529,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/1.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"27.edn_disable_auto_req_mode.50044308550790896346593206957884839803948734957098285223623318561744942964581","seed":50044308550790896346593206957884839803948734957098285223623318561744942964581,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/27.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"28.edn_disable_auto_req_mode.31108439995625838217237171507501531054662243182297230600832709620903092355094","seed":31108439995625838217237171507501531054662243182297230600832709620903092355094,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/28.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"29.edn_disable_auto_req_mode.41316267921579777814197161659013678783479982016687234175332467898888229115224","seed":41316267921579777814197161659013678783479982016687234175332467898888229115224,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/29.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"32.edn_disable_auto_req_mode.70429737055900596047683251075445131192383350850286557814269510078455493212539","seed":70429737055900596047683251075445131192383350850286557814269510078455493212539,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/32.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"43.edn_disable_auto_req_mode.75283345910979505767444769830779721390269925922200978306744333820367700339777","seed":75283345910979505767444769830779721390269925922200978306744333820367700339777,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/43.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.":[{"name":"edn_disable_auto_req_mode","qual_name":"2.edn_disable_auto_req_mode.47510603427245436813421754030764456603191834851420339589529076546418602159365","seed":47510603427245436813421754030764456603191834851420339589529076546418602159365,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/2.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  11360265 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00fca9b2 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  11360265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"16.edn_disable_auto_req_mode.39486483220907615042969392222785395614031723682950357366662733668129443314196","seed":39486483220907615042969392222785395614031723682950357366662733668129443314196,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/16.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  18302262 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00001603 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  18302262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"18.edn_disable_auto_req_mode.66550178683500023251868399212509578305958629399511933143645545213813992306220","seed":66550178683500023251868399212509578305958629399511933143645545213813992306220,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/18.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  41055900 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x004fa902 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  41055900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"26.edn_disable_auto_req_mode.98709710505614344207915967700475626000576170889294334073350534866757588155517","seed":98709710505614344207915967700475626000576170889294334073350534866757588155517,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/26.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  55623350 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00e7c6b2 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  55623350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"edn_stress_all_with_rand_reset","qual_name":"17.edn_stress_all_with_rand_reset.79624087709338105281709221958722427578193103044207820191673577535139920285914","seed":79624087709338105281709221958722427578193103044207820191673577535139920285914,"line":334,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/17.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4171922795 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4171922795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"27.edn_stress_all_with_rand_reset.72358285214559788677354336974298001338356758493250769689030154231340273562739","seed":72358285214559788677354336974298001338356758493250769689030154231340273562739,"line":258,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/27.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1780107488 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1780107488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"35.edn_stress_all_with_rand_reset.104382023416398181208387207362369575288032430419058571051418486784896962393759","seed":104382023416398181208387207362369575288032430419058571051418486784896962393759,"line":161,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/35.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 993005307 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 993005307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"43.edn_stress_all_with_rand_reset.20827910404232850360253752655217346183976871137656757015001574929793749358178","seed":20827910404232850360253752655217346183976871137656757015001574929793749358178,"line":160,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/43.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1293338933 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1293338933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"47.edn_stress_all_with_rand_reset.91495973587837647774658998764075123093762076408685172356880860542323957948496","seed":91495973587837647774658998764075123093762076408685172356880860542323957948496,"line":342,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/47.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4001988776 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4001988776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Error-[FCIBH] Illegal bin hit":[{"name":"edn_stress_all_with_rand_reset","qual_name":"36.edn_stress_all_with_rand_reset.75722217429245453772660760521827283882120209786589688804250433708063103769652","seed":75722217429245453772660760521827283882120209786589688804250433708063103769652,"line":174,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/36.edn_stress_all_with_rand_reset/latest/run.log","log_context":["Error-[FCIBH] Illegal bin hit\n","/nightly/current_run/scratch/master/edn_edn0-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25\n","csrng_agent_pkg, \"csrng_agent_pkg::device_cmd_cg\"\n","  VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 195959251 ps, Illegal \n","  state bin il of coverpoint csrng_cmd_cp in covergroup \n"]}]}},"passed":1114,"total":1130,"percent":98.58407079646018}