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(uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"edn_disable_auto_req_mode","qual_name":"0.edn_disable_auto_req_mode.108520504742415988801538636411058194216629730683038348921558585691587026707468","seed":108520504742415988801538636411058194216629730683038348921558585691587026707468,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"15.edn_disable_auto_req_mode.49053862065891549027325336002064248422505893970938710233302992293941842644773","seed":49053862065891549027325336002064248422505893970938710233302992293941842644773,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"26.edn_disable_auto_req_mode.51242792611634827634250661090291732798149982461411344002041703236661480320619","seed":51242792611634827634250661090291732798149982461411344002041703236661480320619,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"32.edn_disable_auto_req_mode.109311599236220880592476580859962700875754024865295856331568788394393478858842","seed":109311599236220880592476580859962700875754024865295856331568788394393478858842,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/32.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"40.edn_disable_auto_req_mode.66412567637021511354734252756402479065102110008641667717210439598912040112755","seed":66412567637021511354734252756402479065102110008641667717210439598912040112755,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/40.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"43.edn_disable_auto_req_mode.37046372238062792026549862563128393609772152633897135095569312196456097005747","seed":37046372238062792026549862563128393609772152633897135095569312196456097005747,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/43.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"edn_stress_all_with_rand_reset","qual_name":"1.edn_stress_all_with_rand_reset.72793628020778766350098371191689019778547915569285351841835488611806452754667","seed":72793628020778766350098371191689019778547915569285351841835488611806452754667,"line":207,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 755705069 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 755705069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"5.edn_stress_all_with_rand_reset.52361461457218735332650920586207567761880932265754175344039690870861089007850","seed":52361461457218735332650920586207567761880932265754175344039690870861089007850,"line":153,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/5.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1180018521 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1180018521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"7.edn_stress_all_with_rand_reset.16247388619242804711157631602626205785895946764049283754355341247516653721688","seed":16247388619242804711157631602626205785895946764049283754355341247516653721688,"line":185,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 603316850 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 603316850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"13.edn_stress_all_with_rand_reset.43272511179204497166117069097242257622892155139093265366289686911916353372721","seed":43272511179204497166117069097242257622892155139093265366289686911916353372721,"line":318,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4556544593 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4556544593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"19.edn_stress_all_with_rand_reset.67202800655627745858735831502022698187850910842664168975323950307850060722245","seed":67202800655627745858735831502022698187850910842664168975323950307850060722245,"line":186,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1800507580 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1800507580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"26.edn_stress_all_with_rand_reset.35252659188833789913737981749485860044416478474653213839369146187525018736846","seed":35252659188833789913737981749485860044416478474653213839369146187525018736846,"line":185,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1613484224 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1613484224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"32.edn_stress_all_with_rand_reset.88494956302285529343405585539426666535628071818467169412790183362358559065315","seed":88494956302285529343405585539426666535628071818467169412790183362358559065315,"line":142,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/32.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 848600942 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 848600942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"34.edn_stress_all_with_rand_reset.53280762860196266380883355860507884685430675029205424267200596668844128875769","seed":53280762860196266380883355860507884685430675029205424267200596668844128875769,"line":140,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/34.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 924142125 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 924142125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"43.edn_stress_all_with_rand_reset.76136993405369430129619476779928460965493167189990928628337491875560159716585","seed":76136993405369430129619476779928460965493167189990928628337491875560159716585,"line":132,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/43.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 163296589 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 163296589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"46.edn_stress_all_with_rand_reset.49047699248775336028345852582661635741679251108202489648743001179924448720769","seed":49047699248775336028345852582661635741679251108202489648743001179924448720769,"line":117,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/46.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 781740541 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 781740541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Error-[FCIBH] Illegal bin hit":[{"name":"edn_disable_auto_req_mode","qual_name":"8.edn_disable_auto_req_mode.40292285900808585753976157867169035567755912656624255463031611453342377523385","seed":40292285900808585753976157867169035567755912656624255463031611453342377523385,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/8.edn_disable_auto_req_mode/latest/run.log","log_context":["Error-[FCIBH] Illegal bin hit\n","/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25\n","csrng_agent_pkg, \"csrng_agent_pkg::device_cmd_cg\"\n","  VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 62140242 ps, Illegal \n","  state bin il of coverpoint csrng_cmd_cp in covergroup \n"]}],"UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.":[{"name":"edn_disable_auto_req_mode","qual_name":"37.edn_disable_auto_req_mode.1854519597792442219843054952115963359418395742080904692912682884467905817134","seed":1854519597792442219843054952115963359418395742080904692912682884467905817134,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/37.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  28697445 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x001fd962 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  28697445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1112,"total":1130,"percent":98.40707964601769}