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---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"8.keymgr_stress_all_with_rand_reset.48093764557945918034164910966263069007588119614285953406593486570078546235683","seed":48093764557945918034164910966263069007588119614285953406593486570078546235683,"line":1058,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/8.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 364400782 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 364400782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"9.keymgr_stress_all_with_rand_reset.35041346413108650165274595075778341624972952674102147588389834552168374005760","seed":35041346413108650165274595075778341624972952674102147588389834552168374005760,"line":1366,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/9.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 710472154 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 710472154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"12.keymgr_stress_all_with_rand_reset.6132064917835027025029353775584038357988866247435889947348286546227230210221","seed":6132064917835027025029353775584038357988866247435889947348286546227230210221,"line":245,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/12.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 141676004 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 141676004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"14.keymgr_stress_all_with_rand_reset.50411406769356526660183343568958439169527910647915283261012343780484210123232","seed":50411406769356526660183343568958439169527910647915283261012343780484210123232,"line":800,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/14.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1287977917 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1287977917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"18.keymgr_stress_all_with_rand_reset.29240874712399484827973692469390301330203104172963273158295401246523417969283","seed":29240874712399484827973692469390301330203104172963273158295401246523417969283,"line":283,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/18.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 302852951 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 302852951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"19.keymgr_stress_all_with_rand_reset.3424297541245159800754323919272361099446737718574372776218457439393424476565","seed":3424297541245159800754323919272361099446737718574372776218457439393424476565,"line":655,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/19.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1197177017 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1197177017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"20.keymgr_stress_all_with_rand_reset.95466156837251764667061377434597834340254457816723771903225518642122646727108","seed":95466156837251764667061377434597834340254457816723771903225518642122646727108,"line":158,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/20.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 461344841 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 461344841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"21.keymgr_stress_all_with_rand_reset.107572318855155546532179290912372071769331143731801163918929362554623779879558","seed":107572318855155546532179290912372071769331143731801163918929362554623779879558,"line":488,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/21.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 644711933 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 644711933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"25.keymgr_stress_all_with_rand_reset.78204541257346463752103158687656668432974292201469487419958075437662304814669","seed":78204541257346463752103158687656668432974292201469487419958075437662304814669,"line":878,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/25.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 545371341 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 545371341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"30.keymgr_stress_all_with_rand_reset.12547220424076732027466024448397297338422782842588270936531029098620266010599","seed":12547220424076732027466024448397297338422782842588270936531029098620266010599,"line":286,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/30.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 534349614 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 534349614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"33.keymgr_stress_all_with_rand_reset.34797269620154668611197170460142280589820053018197102008845417310358858784530","seed":34797269620154668611197170460142280589820053018197102008845417310358858784530,"line":872,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/33.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3741766409 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3741766409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"35.keymgr_stress_all_with_rand_reset.17463861705160417290812329694222074068955035686817985376749714659561654685302","seed":17463861705160417290812329694222074068955035686817985376749714659561654685302,"line":1283,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/35.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1422403168 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1422403168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"37.keymgr_stress_all_with_rand_reset.108016220793239604975567026042627037083463072785830805869648200831315433943732","seed":108016220793239604975567026042627037083463072785830805869648200831315433943732,"line":365,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/37.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 165925377 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10008 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 165925377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"40.keymgr_stress_all_with_rand_reset.93853657190879384170277774606821000246038479643160172294558132031806023928622","seed":93853657190879384170277774606821000246038479643160172294558132031806023928622,"line":633,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/40.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 246770417 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 246770417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"41.keymgr_stress_all_with_rand_reset.43835325072204432914146461162512044457894840989880949031979975526314049947299","seed":43835325072204432914146461162512044457894840989880949031979975526314049947299,"line":233,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/41.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 586849076 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 586849076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"44.keymgr_stress_all_with_rand_reset.50333136150802417673416202978172326057844838992864187788502522238817612225192","seed":50333136150802417673416202978172326057844838992864187788502522238817612225192,"line":1044,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/44.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 324155125 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 324155125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"46.keymgr_stress_all_with_rand_reset.108428805752387413888606635651721625577478191511339572374250583480750652795870","seed":108428805752387413888606635651721625577478191511339572374250583480750652795870,"line":102,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/46.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 106081665 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 106081665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StCreatorRootKey for Attestation Kmac":[{"name":"keymgr_lc_disable","qual_name":"1.keymgr_lc_disable.97270094756461345802624241015377521223638608220632636467354555802661083855810","seed":97270094756461345802624241015377521223638608220632636467354555802661083855810,"line":249,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_lc_disable/latest/run.log","log_context":["UVM_ERROR @  26849983 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (9941408910649659374519188707195760638686311306577988539176511476502911168277025875211151363036104301896015918801587641340336534573453775027782140359676404 [0xbdd0983391feb4957ea9199ff7e9a7d88e71ee5f005a5bce88e1352527f6a1a1a53c499036ff98d141332494f438cd5107a4e3e9bc04508fd54f6af19d1911f4] vs 9941408910649659374519188707195760638686311306577988539176511476502911168277025875211151363036104301896015918801587641340336534573453775027782140359676404 [0xbdd0983391feb4957ea9199ff7e9a7d88e71ee5f005a5bce88e1352527f6a1a1a53c499036ff98d141332494f438cd5107a4e3e9bc04508fd54f6af19d1911f4]) KMAC key at state StCreatorRootKey for Attestation Kmac\n","UVM_INFO @  26849983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*":[{"name":"keymgr_random","qual_name":"3.keymgr_random.85470761628644527538563442497292444280294243022314083383253454146971287526551","seed":85470761628644527538563442497292444280294243022314083383253454146971287526551,"line":94,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/3.keymgr_random/latest/run.log","log_context":["UVM_ERROR @   6555904 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @   6555904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"24.keymgr_stress_all_with_rand_reset.35720925341562475735191352861638194991717117324702236626737879790886831251387","seed":35720925341562475735191352861638194991717117324702236626737879790886831251387,"line":101,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/24.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  12273415 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @  12273415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_*":[{"name":"keymgr_lc_disable","qual_name":"13.keymgr_lc_disable.14711504100106706756963071650319306834755157149756740107952767403994258944604","seed":14711504100106706756963071650319306834755157149756740107952767403994258944604,"line":178,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/13.keymgr_lc_disable/latest/run.log","log_context":["UVM_ERROR @  23635562 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_0\n","UVM_INFO @  23635562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all","qual_name":"24.keymgr_stress_all.100071643685870409328577153297430239662689135837693211979425252878358388455141","seed":100071643685870409328577153297430239662689135837693211979425252878358388455141,"line":2139,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/24.keymgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1473819960 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_7\n","UVM_INFO @ 1473819960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share0_output_*":[{"name":"keymgr_stress_all_with_rand_reset","qual_name":"38.keymgr_stress_all_with_rand_reset.79630419330010778782825665067110148924183167571270598939647107027702820054766","seed":79630419330010778782825665067110148924183167571270598939647107027702820054766,"line":1106,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/38.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3692962123 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3983337306 [0xed6ce75a] vs 3983337306 [0xed6ce75a]) reg name: keymgr_reg_block.sw_share0_output_1\n","UVM_INFO @ 3692962123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1149) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.":[{"name":"keymgr_stress_all_with_rand_reset","qual_name":"45.keymgr_stress_all_with_rand_reset.87016636318153018410006362499073952351504820771607982339206615550703265376449","seed":87016636318153018410006362499073952351504820771607982339206615550703265376449,"line":275,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/45.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 308534225 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 308534225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1085,"total":1110,"percent":97.74774774774775}