{"block":{"name":"rv_dm","variant":"use_dmi_interface","commit":"5b8f6746131e231116e685585432b70359d2c727","commit_short":"5b8f674","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/5b8f6746131e231116e685585432b70359d2c727","revision_info":"GitHub Revision: [`5b8f674`](https://github.com/lowrisc/opentitan/tree/5b8f6746131e231116e685585432b70359d2c727)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-19T03:35:48Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/rv_dm/data/rv_dm_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"rv_dm_smoke":{"max_time":2.63,"sim_time":3342.911639,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"jtag_dtm_csr_hw_reset":{"tests":{"rv_dm_jtag_dtm_csr_hw_reset":{"max_time":1.7,"sim_time":270.56436099999996,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"jtag_dtm_csr_rw":{"tests":{"rv_dm_jtag_dtm_csr_rw":{"max_time":3.4,"sim_time":770.965073,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"jtag_dtm_csr_bit_bash":{"tests":{"rv_dm_jtag_dtm_csr_bit_bash":{"max_time":57.88,"sim_time":33411.432532,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"jtag_dtm_csr_aliasing":{"tests":{"rv_dm_jtag_dtm_csr_aliasing":{"max_time":4.08,"sim_time":1546.775965,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"jtag_dmi_csr_hw_reset":{"tests":{"rv_dm_jtag_dmi_csr_hw_reset":{"max_time":61.53,"sim_time":24321.814799,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"jtag_dmi_csr_rw":{"tests":{"rv_dm_jtag_dmi_csr_rw":{"max_time":15.65,"sim_time":10983.85154,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"jtag_dmi_csr_bit_bash":{"tests":{"rv_dm_jtag_dmi_csr_bit_bash":{"max_time":162.66,"sim_time":62324.151898000004,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"jtag_dmi_csr_aliasing":{"tests":{"rv_dm_jtag_dmi_csr_aliasing":{"max_time":139.46,"sim_time":233057.158998,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"jtag_dmi_cmderr_busy":{"tests":{"rv_dm_cmderr_busy":{"max_time":2.71,"sim_time":935.393131,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"jtag_dmi_cmderr_not_supported":{"tests":{"rv_dm_cmderr_not_supported":{"max_time":1.22,"sim_time":381.323421,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"cmderr_exception":{"tests":{"rv_dm_cmderr_exception":{"max_time":1.09,"sim_time":311.545239,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"mem_tl_access_resuming":{"tests":{"rv_dm_mem_tl_access_resuming":{"max_time":0.87,"sim_time":270.102962,"passed":0,"total":2,"percent":0.0}},"passed":0,"total":2,"percent":0.0},"mem_tl_access_halted":{"tests":{"rv_dm_mem_tl_access_halted":{"max_time":1.05,"sim_time":278.72222,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"cmderr_halt_resume":{"tests":{"rv_dm_cmderr_halt_resume":{"max_time":1.52,"sim_time":451.12973900000003,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"dataaddr_rw_access":{"tests":{"rv_dm_dataaddr_rw_access":{"max_time":0.87,"sim_time":80.45142299999999,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"halt_resume":{"tests":{"rv_dm_halt_resume_whereto":{"max_time":5.43,"sim_time":1200.7530889999998,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"progbuf_busy":{"tests":{"rv_dm_cmderr_busy":{"max_time":2.71,"sim_time":935.393131,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"abstractcmd_status":{"tests":{"rv_dm_abstractcmd_status":{"max_time":1.12,"sim_time":239.685656,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"progbuf_read_write_execute":{"tests":{"rv_dm_progbuf_read_write_execute":{"max_time":3.81,"sim_time":1529.497793,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"progbuf_exception":{"tests":{"rv_dm_cmderr_exception":{"max_time":1.09,"sim_time":311.545239,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"rom_read_access":{"tests":{"rv_dm_rom_read_access":{"max_time":0.83,"sim_time":49.510368,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"csr_hw_reset":{"tests":{"rv_dm_csr_hw_reset":{"max_time":2.91,"sim_time":1029.164525,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"rv_dm_csr_rw":{"max_time":3.17,"sim_time":439.00307699999996,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"rv_dm_csr_bit_bash":{"max_time":48.63,"sim_time":5881.898219,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"rv_dm_csr_aliasing":{"max_time":60.64999999999999,"sim_time":16710.198689,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"rv_dm_csr_mem_rw_with_rand_reset":{"max_time":4.88,"sim_time":310.54812,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"rv_dm_csr_aliasing":{"max_time":60.64999999999999,"sim_time":16710.198689,"passed":5,"total":5,"percent":100.0},"rv_dm_csr_rw":{"max_time":3.17,"sim_time":439.00307699999996,"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"mem_walk":{"tests":{"rv_dm_mem_walk":{"max_time":1.17,"sim_time":81.34160899999999,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"mem_partial_access":{"tests":{"rv_dm_mem_partial_access":{"max_time":1.19,"sim_time":46.446889000000006,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0}},"passed":178,"total":180,"percent":98.88888888888889},"V2":{"testpoints":{"idcode":{"tests":{"rv_dm_smoke":{"max_time":2.63,"sim_time":3342.911639,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"jtag_dtm_hard_reset":{"tests":{"rv_dm_jtag_dtm_hard_reset":{"max_time":1.51,"sim_time":196.92948199999998,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"jtag_dtm_idle_hint":{"tests":{"rv_dm_jtag_dtm_idle_hint":{"max_time":1.0,"sim_time":202.67803700000002,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"jtag_dmi_failed_op":{"tests":{"rv_dm_dmi_failed_op":{"max_time":1.02,"sim_time":644.219689,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"jtag_dmi_dm_inactive":{"tests":{"rv_dm_jtag_dmi_dm_inactive":{"max_time":2.02,"sim_time":526.222935,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"sba":{"tests":{"rv_dm_sba_tl_access":{"max_time":835.17,"sim_time":300000.0,"passed":0,"total":20,"percent":0.0},"rv_dm_delayed_resp_sba_tl_access":{"max_time":963.8300000000002,"sim_time":300000.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":40,"percent":0.0},"bad_sba":{"tests":{"rv_dm_bad_sba_tl_access":{"max_time":821.01,"sim_time":300000.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"sba_autoincrement":{"tests":{"rv_dm_autoincr_sba_tl_access":{"max_time":940.66,"sim_time":300000.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"jtag_dmi_debug_disabled":{"tests":{"rv_dm_jtag_dmi_debug_disabled":{"max_time":1.11,"sim_time":201.708458,"passed":0,"total":2,"percent":0.0}},"passed":0,"total":2,"percent":0.0},"sba_debug_disabled":{"tests":{"rv_dm_sba_debug_disabled":{"max_time":1.86,"sim_time":1781.8820560000001,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"ndmreset_req":{"tests":{"rv_dm_ndmreset_req":{"max_time":1.12,"sim_time":160.50868400000002,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"hart_unavail":{"tests":{"rv_dm_hart_unavail":{"max_time":1.26,"sim_time":103.232803,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"tap_ctrl_transitions":{"tests":{"rv_dm_tap_fsm":{"max_time":22.25,"sim_time":9907.922177999999,"passed":1,"total":1,"percent":100.0},"rv_dm_tap_fsm_rand_reset":{"max_time":75.89,"sim_time":5979.390904,"passed":10,"total":10,"percent":100.0}},"passed":11,"total":11,"percent":100.0},"hartsel_warl":{"tests":{"rv_dm_hartsel_warl":{"max_time":0.83,"sim_time":60.854912,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"stress_all":{"tests":{"rv_dm_stress_all":{"max_time":8582.4,"sim_time":10000000.0,"passed":5,"total":50,"percent":10.0}},"passed":5,"total":50,"percent":10.0},"alert_test":{"tests":{"rv_dm_alert_test":{"max_time":1.53,"sim_time":144.59658100000001,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"rv_dm_tl_errors":{"max_time":6.67,"sim_time":1001.3834459999999,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"rv_dm_tl_errors":{"max_time":6.67,"sim_time":1001.3834459999999,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"rv_dm_csr_aliasing":{"max_time":60.64999999999999,"sim_time":16710.198689,"passed":5,"total":5,"percent":100.0},"rv_dm_csr_hw_reset":{"max_time":2.91,"sim_time":1029.164525,"passed":5,"total":5,"percent":100.0},"rv_dm_csr_rw":{"max_time":3.17,"sim_time":439.00307699999996,"passed":20,"total":20,"percent":100.0},"rv_dm_same_csr_outstanding":{"max_time":9.63,"sim_time":1060.737918,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"rv_dm_csr_aliasing":{"max_time":60.64999999999999,"sim_time":16710.198689,"passed":5,"total":5,"percent":100.0},"rv_dm_csr_hw_reset":{"max_time":2.91,"sim_time":1029.164525,"passed":5,"total":5,"percent":100.0},"rv_dm_csr_rw":{"max_time":3.17,"sim_time":439.00307699999996,"passed":20,"total":20,"percent":100.0},"rv_dm_same_csr_outstanding":{"max_time":9.63,"sim_time":1060.737918,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":151,"total":283,"percent":53.35689045936396},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"rv_dm_sec_cm":{"max_time":4.82,"sim_time":1729.643882,"passed":5,"total":5,"percent":100.0},"rv_dm_tl_intg_err":{"max_time":28.19,"sim_time":5894.06512,"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"rv_dm_tl_intg_err":{"max_time":28.19,"sim_time":5894.06512,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_lc_hw_debug_en_intersig_mubi":{"tests":{"rv_dm_sba_debug_disabled":{"max_time":1.86,"sim_time":1781.8820560000001,"passed":2,"total":2,"percent":100.0},"rv_dm_debug_disabled":{"max_time":0.89,"sim_time":60.911646999999995,"passed":1,"total":2,"percent":50.0}},"passed":3,"total":4,"percent":75.0},"sec_cm_lc_dft_en_intersig_mubi":{"tests":{"rv_dm_sba_debug_disabled":{"max_time":1.86,"sim_time":1781.8820560000001,"passed":2,"total":2,"percent":100.0},"rv_dm_debug_disabled":{"max_time":0.89,"sim_time":60.911646999999995,"passed":1,"total":2,"percent":50.0}},"passed":3,"total":4,"percent":75.0},"sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi":{"tests":{"rv_dm_smoke":{"max_time":2.63,"sim_time":3342.911639,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"sec_cm_dm_en_ctrl_lc_gated":{"tests":{"rv_dm_buffered_enable":{"max_time":2.11,"sim_time":661.713524,"passed":9,"total":10,"percent":90.0}},"passed":9,"total":10,"percent":90.0},"sec_cm_sba_tl_lc_gate_fsm_sparse":{"tests":{"rv_dm_sparse_lc_gate_fsm":{"max_time":1.36,"sim_time":138.5789,"passed":4,"total":4,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"sec_cm_mem_tl_lc_gate_fsm_sparse":{"tests":{"rv_dm_sparse_lc_gate_fsm":{"max_time":1.36,"sim_time":138.5789,"passed":4,"total":4,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"sec_cm_exec_ctrl_mubi":{"tests":{"rv_dm_buffered_enable":{"max_time":2.11,"sim_time":661.713524,"passed":9,"total":10,"percent":90.0}},"passed":9,"total":10,"percent":90.0}},"passed":43,"total":45,"percent":95.55555555555556},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"rv_dm_stress_all_with_rand_reset":{"max_time":61.71,"sim_time":3797.299077,"passed":1,"total":10,"percent":10.0}},"passed":1,"total":10,"percent":10.0}},"passed":1,"total":10,"percent":10.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"rv_dm_scanmode":{"max_time":144.87,"sim_time":300000.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"coverage":{"code":{"block":null,"line_statement":91.22,"branch":77.14,"condition_expression":78.27,"toggle":73.92,"fsm":56.25},"assertion":96.24,"functional":75.22},"cov_report_page":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"rv_dm_sba_tl_access","qual_name":"0.rv_dm_sba_tl_access.44189010590607071476319707915374149641365096155731569685021347219334468529892","seed":44189010590607071476319707915374149641365096155731569685021347219334468529892,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"0.rv_dm_delayed_resp_sba_tl_access.63782090516169274814930761105850772795852776957126090318455839868629715632814","seed":63782090516169274814930761105850772795852776957126090318455839868629715632814,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"0.rv_dm_bad_sba_tl_access.14974847103427036463516441957869957212458497759581434482961120935862469588316","seed":14974847103427036463516441957869957212458497759581434482961120935862469588316,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"0.rv_dm_autoincr_sba_tl_access.4859724876616793904642655720959943645621457912186828164453353028302262957042","seed":4859724876616793904642655720959943645621457912186828164453353028302262957042,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_scanmode","qual_name":"0.rv_dm_scanmode.60453947398359330825353529851006146580424961248126931575782712835637431352231","seed":60453947398359330825353529851006146580424961248126931575782712835637431352231,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_scanmode/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"1.rv_dm_sba_tl_access.87208917251897818396519739861552255401072835132363035707701321408882030279479","seed":87208917251897818396519739861552255401072835132363035707701321408882030279479,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"1.rv_dm_delayed_resp_sba_tl_access.86146528618258423520319055731989971702252806374242503690619698827664993645752","seed":86146528618258423520319055731989971702252806374242503690619698827664993645752,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"1.rv_dm_bad_sba_tl_access.92223961218013499859554790231887477287840200118271485218685443617790464033379","seed":92223961218013499859554790231887477287840200118271485218685443617790464033379,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"1.rv_dm_autoincr_sba_tl_access.43394150007890907105775045520122387397070465810628589434718290010559909515775","seed":43394150007890907105775045520122387397070465810628589434718290010559909515775,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"2.rv_dm_sba_tl_access.90436961905439707736210646139890814606784471050531398594801246778228008069418","seed":90436961905439707736210646139890814606784471050531398594801246778228008069418,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"2.rv_dm_delayed_resp_sba_tl_access.73458928348511375058390892087564249196309784162362961929998737544481369534377","seed":73458928348511375058390892087564249196309784162362961929998737544481369534377,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"2.rv_dm_bad_sba_tl_access.80997165925887978458811863232948692595869488963299935312392271620379451518081","seed":80997165925887978458811863232948692595869488963299935312392271620379451518081,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"2.rv_dm_autoincr_sba_tl_access.54055728862837322496365266196414301478922674449089229705893605672594780544003","seed":54055728862837322496365266196414301478922674449089229705893605672594780544003,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"3.rv_dm_sba_tl_access.70944832712491789232413774827157563877299727257194579452923343159763660417344","seed":70944832712491789232413774827157563877299727257194579452923343159763660417344,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"3.rv_dm_delayed_resp_sba_tl_access.60431490723444733187137446338950918660841446585191803440420067400476684013145","seed":60431490723444733187137446338950918660841446585191803440420067400476684013145,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"3.rv_dm_bad_sba_tl_access.44896303796561961504702812150097179524871295719936000233765245250511018582830","seed":44896303796561961504702812150097179524871295719936000233765245250511018582830,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"3.rv_dm_autoincr_sba_tl_access.17739057098620819835255228395534997809728529584838998243022037344136231044328","seed":17739057098620819835255228395534997809728529584838998243022037344136231044328,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"4.rv_dm_sba_tl_access.91397626480229526916055190094042349813962004334518101893022721351071541287457","seed":91397626480229526916055190094042349813962004334518101893022721351071541287457,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"4.rv_dm_delayed_resp_sba_tl_access.27107383810303639044215124492369650545121598819380527810689071030687448549536","seed":27107383810303639044215124492369650545121598819380527810689071030687448549536,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"4.rv_dm_bad_sba_tl_access.96042173994841412289526398959447057956223196561058228727613556391803426736757","seed":96042173994841412289526398959447057956223196561058228727613556391803426736757,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"4.rv_dm_autoincr_sba_tl_access.104428433851119670051008868922368102277811152095510881834466298179174822110629","seed":104428433851119670051008868922368102277811152095510881834466298179174822110629,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"5.rv_dm_sba_tl_access.52445044535764220590378774875875409805921558794260345084380958113134044816453","seed":52445044535764220590378774875875409805921558794260345084380958113134044816453,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"5.rv_dm_delayed_resp_sba_tl_access.57351522339352456660017223864529363034176129728901180371293529676037882139458","seed":57351522339352456660017223864529363034176129728901180371293529676037882139458,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"5.rv_dm_bad_sba_tl_access.22082498805068466212123399354450992929928765364390189899986136237961220138539","seed":22082498805068466212123399354450992929928765364390189899986136237961220138539,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"5.rv_dm_autoincr_sba_tl_access.29409001678571462047413225973090260628004941725328341005818412362301189218973","seed":29409001678571462047413225973090260628004941725328341005818412362301189218973,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"6.rv_dm_sba_tl_access.50234395910554341310396460132242726079458345340824627308245635536247625430824","seed":50234395910554341310396460132242726079458345340824627308245635536247625430824,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"6.rv_dm_delayed_resp_sba_tl_access.94603438404640321316078001698977472081438355823374680866948347726815554824565","seed":94603438404640321316078001698977472081438355823374680866948347726815554824565,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"6.rv_dm_bad_sba_tl_access.95566838111234529212505844206990325551882800356201141540340850726341124813770","seed":95566838111234529212505844206990325551882800356201141540340850726341124813770,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"6.rv_dm_autoincr_sba_tl_access.107129123012956502396461626575713237289611339515952719059452973134319315509673","seed":107129123012956502396461626575713237289611339515952719059452973134319315509673,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"7.rv_dm_sba_tl_access.62814412256912282772152819952270182673701188005027730660787982897939605901405","seed":62814412256912282772152819952270182673701188005027730660787982897939605901405,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"7.rv_dm_delayed_resp_sba_tl_access.79929254706692559380267529993708935653033147931160497173349424624765833933212","seed":79929254706692559380267529993708935653033147931160497173349424624765833933212,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"7.rv_dm_bad_sba_tl_access.46177430719245782033815771423940758134683564798305483696980274632916250837868","seed":46177430719245782033815771423940758134683564798305483696980274632916250837868,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"7.rv_dm_autoincr_sba_tl_access.16019883533331169870838808036836006790029738744020925300543605879960034756418","seed":16019883533331169870838808036836006790029738744020925300543605879960034756418,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"8.rv_dm_sba_tl_access.53590326952266375791872718228211021524986223012649096442886575240158385744511","seed":53590326952266375791872718228211021524986223012649096442886575240158385744511,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"8.rv_dm_delayed_resp_sba_tl_access.40182794574274916851690847089484747159324993094447677391287027508875467861926","seed":40182794574274916851690847089484747159324993094447677391287027508875467861926,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"8.rv_dm_bad_sba_tl_access.114408334815917519122251262639271486261635263106340245319671108622221960606703","seed":114408334815917519122251262639271486261635263106340245319671108622221960606703,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"8.rv_dm_autoincr_sba_tl_access.79748562180365672286050960482846102603084472114233410310008749445551366058042","seed":79748562180365672286050960482846102603084472114233410310008749445551366058042,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"9.rv_dm_sba_tl_access.115575015023491256371171539233153558640065040861348137005945294529772948294817","seed":115575015023491256371171539233153558640065040861348137005945294529772948294817,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"9.rv_dm_delayed_resp_sba_tl_access.50588416907536600408731689468064811963473112823310302139434640131398487012450","seed":50588416907536600408731689468064811963473112823310302139434640131398487012450,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"9.rv_dm_bad_sba_tl_access.80745579736455697453427722117705694238197164376382190874685899220151641234253","seed":80745579736455697453427722117705694238197164376382190874685899220151641234253,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"9.rv_dm_autoincr_sba_tl_access.114174700771203403195980660807294784565395654493058198629461725138624053253761","seed":114174700771203403195980660807294784565395654493058198629461725138624053253761,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"10.rv_dm_sba_tl_access.66878064280522873137227046733616438101504298549465643030210271487965062487169","seed":66878064280522873137227046733616438101504298549465643030210271487965062487169,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/10.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"10.rv_dm_delayed_resp_sba_tl_access.58946236674967873595208395817002524331964163876689754897471798449616143569701","seed":58946236674967873595208395817002524331964163876689754897471798449616143569701,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/10.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"10.rv_dm_bad_sba_tl_access.26309148724540685116158925554079548204775972512540716701582695036879253934817","seed":26309148724540685116158925554079548204775972512540716701582695036879253934817,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/10.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"10.rv_dm_autoincr_sba_tl_access.40049927212010578230199180761204899808296397515688022404382546685770391343502","seed":40049927212010578230199180761204899808296397515688022404382546685770391343502,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"11.rv_dm_sba_tl_access.54566545784539815809466544752565810660881325793918786862354264456530905833900","seed":54566545784539815809466544752565810660881325793918786862354264456530905833900,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"11.rv_dm_delayed_resp_sba_tl_access.40038733827244186589735155655199227307373332881811771038308349096569037374114","seed":40038733827244186589735155655199227307373332881811771038308349096569037374114,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/11.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"11.rv_dm_bad_sba_tl_access.12795951190686174345830086103482063801499309175981162301990109559015188900513","seed":12795951190686174345830086103482063801499309175981162301990109559015188900513,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/11.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"11.rv_dm_autoincr_sba_tl_access.35353832995908683385532617503175055722131799559876276347441010043944398985477","seed":35353832995908683385532617503175055722131799559876276347441010043944398985477,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"12.rv_dm_sba_tl_access.54649090665445668176331974600886676204861828382528629651121519891492081831907","seed":54649090665445668176331974600886676204861828382528629651121519891492081831907,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/12.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"12.rv_dm_delayed_resp_sba_tl_access.70874394167464651084677477814906706950560690499911858021399900690822372915341","seed":70874394167464651084677477814906706950560690499911858021399900690822372915341,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/12.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"12.rv_dm_bad_sba_tl_access.41872615208932447288956927392144766561145879043930244051025334311884036310218","seed":41872615208932447288956927392144766561145879043930244051025334311884036310218,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"12.rv_dm_autoincr_sba_tl_access.89441878425775374696672809142021565746656273748786239835445095109204629722596","seed":89441878425775374696672809142021565746656273748786239835445095109204629722596,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"13.rv_dm_sba_tl_access.29420190531530054859895164049972192710421960813489001389605952821897813599199","seed":29420190531530054859895164049972192710421960813489001389605952821897813599199,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/13.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"13.rv_dm_delayed_resp_sba_tl_access.85189441238753600965650327035261799411391499067460406371470636408186088900174","seed":85189441238753600965650327035261799411391499067460406371470636408186088900174,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/13.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"13.rv_dm_bad_sba_tl_access.84253895821229107907450415381917116812459871296707474543431221001241762801961","seed":84253895821229107907450415381917116812459871296707474543431221001241762801961,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/13.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"13.rv_dm_autoincr_sba_tl_access.18186187202281468126918131887952678023964434476010626335986242321967967279343","seed":18186187202281468126918131887952678023964434476010626335986242321967967279343,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"14.rv_dm_sba_tl_access.99369173549299272682834656436728811456358149464361087377505099829391640895067","seed":99369173549299272682834656436728811456358149464361087377505099829391640895067,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/14.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"14.rv_dm_delayed_resp_sba_tl_access.40775052952982857892067558533457244106631460792089327142498941184183816071486","seed":40775052952982857892067558533457244106631460792089327142498941184183816071486,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/14.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"14.rv_dm_bad_sba_tl_access.9123449852983405244055227140418409045359588745963203556754198734256378523749","seed":9123449852983405244055227140418409045359588745963203556754198734256378523749,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/14.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"14.rv_dm_autoincr_sba_tl_access.37563712376574315647998190557692982632040108132180069013969157069647468670276","seed":37563712376574315647998190557692982632040108132180069013969157069647468670276,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"15.rv_dm_sba_tl_access.13293524296418102417973121238978062472107298061062876710958550491583592369148","seed":13293524296418102417973121238978062472107298061062876710958550491583592369148,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/15.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"15.rv_dm_delayed_resp_sba_tl_access.12440032854585151590592986621085680636504190859926803638808047924319188114860","seed":12440032854585151590592986621085680636504190859926803638808047924319188114860,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/15.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"15.rv_dm_bad_sba_tl_access.111491222227434402076902475197298170450447714455927307580381449236183406795328","seed":111491222227434402076902475197298170450447714455927307580381449236183406795328,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"15.rv_dm_autoincr_sba_tl_access.35958226357696450018874408343117458934894941314191986838030627791355761035957","seed":35958226357696450018874408343117458934894941314191986838030627791355761035957,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"16.rv_dm_sba_tl_access.107614618844151801606553253381697810341152894478441381800938896369393351103220","seed":107614618844151801606553253381697810341152894478441381800938896369393351103220,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/16.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"16.rv_dm_delayed_resp_sba_tl_access.15797191384070959463260247501462443058290266227864793721335587417141807657821","seed":15797191384070959463260247501462443058290266227864793721335587417141807657821,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/16.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"16.rv_dm_bad_sba_tl_access.71811531384661254247154915602780409018085398671204787865527215913846300211634","seed":71811531384661254247154915602780409018085398671204787865527215913846300211634,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/16.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"16.rv_dm_autoincr_sba_tl_access.70100418088300508436924593246059663734394972720426985855665324637520018975279","seed":70100418088300508436924593246059663734394972720426985855665324637520018975279,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/16.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"17.rv_dm_sba_tl_access.60039363297791017097728345015433042788990829117033739094146793193753490705614","seed":60039363297791017097728345015433042788990829117033739094146793193753490705614,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/17.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"17.rv_dm_delayed_resp_sba_tl_access.99473095834572339124435316759203936456985945587058422748137258086736686430822","seed":99473095834572339124435316759203936456985945587058422748137258086736686430822,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/17.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"17.rv_dm_bad_sba_tl_access.76089053522449164788919835185058409169182329359585841595737879339862118045672","seed":76089053522449164788919835185058409169182329359585841595737879339862118045672,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/17.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"17.rv_dm_autoincr_sba_tl_access.41405492081952963309293849446790422123595701630631719668318288503184044872194","seed":41405492081952963309293849446790422123595701630631719668318288503184044872194,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"18.rv_dm_sba_tl_access.63062481181162224535446075237886245123440605543580284678921403677938708141237","seed":63062481181162224535446075237886245123440605543580284678921403677938708141237,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/18.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"18.rv_dm_delayed_resp_sba_tl_access.43853600766255151276369061206972073709510980002534445239947289816277885452004","seed":43853600766255151276369061206972073709510980002534445239947289816277885452004,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/18.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"18.rv_dm_bad_sba_tl_access.36211889723034091087917225996319440097291143746696409254512724541687561691414","seed":36211889723034091087917225996319440097291143746696409254512724541687561691414,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/18.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"18.rv_dm_autoincr_sba_tl_access.113815454189163137557736976288791324838045985253509945716330654787619525472694","seed":113815454189163137557736976288791324838045985253509945716330654787619525472694,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_sba_tl_access","qual_name":"19.rv_dm_sba_tl_access.20108219882052613213016520273395925889977942265786712078776847093118120455975","seed":20108219882052613213016520273395925889977942265786712078776847093118120455975,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/19.rv_dm_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_delayed_resp_sba_tl_access","qual_name":"19.rv_dm_delayed_resp_sba_tl_access.114861911628414788806322752930043606313910905601138563181205783400698490847851","seed":114861911628414788806322752930043606313910905601138563181205783400698490847851,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/19.rv_dm_delayed_resp_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"19.rv_dm_bad_sba_tl_access.44770516170069730217654551366147083964265763343004691293704424790510839925933","seed":44770516170069730217654551366147083964265763343004691293704424790510839925933,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/19.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"19.rv_dm_autoincr_sba_tl_access.30426181268537982406525386601648515385176319069479550565417370644133988803470","seed":30426181268537982406525386601648515385176319069479550565417370644133988803470,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/19.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"19.rv_dm_stress_all.112416591723300719070388619828878257335424360309529154133169272938421306262248","seed":112416591723300719070388619828878257335424360309529154133169272938421306262248,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/19.rv_dm_stress_all/latest/run.log","log_context":["UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"20.rv_dm_stress_all.8651253761307384957176390650398665484096414437708013825190978176102361700334","seed":8651253761307384957176390650398665484096414437708013825190978176102361700334,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/20.rv_dm_stress_all/latest/run.log","log_context":["UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"44.rv_dm_stress_all.104021956387935283512920411051637967999522178393163344247794154120307403684403","seed":104021956387935283512920411051637967999522178393163344247794154120307403684403,"line":81,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/44.rv_dm_stress_all/latest/run.log","log_context":["UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == *'b* (* [*] vs * [*])":[{"name":"rv_dm_mem_tl_access_resuming","qual_name":"0.rv_dm_mem_tl_access_resuming.66605916211393126845625527100753236756271509128220724791243261539429885615992","seed":66605916211393126845625527100753236756271509128220724791243261539429885615992,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest/run.log","log_context":["UVM_ERROR @ 270102962 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 270102962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_mem_tl_access_resuming","qual_name":"1.rv_dm_mem_tl_access_resuming.12513658754799539537484916974532781778055449351729652228344017248069921631376","seed":12513658754799539537484916974532781778055449351729652228344017248069921631376,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest/run.log","log_context":["UVM_ERROR @  80336057 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  80336057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"1.rv_dm_stress_all.91411805435319653727370751667073544569700178629220785132928323860004505356526","seed":91411805435319653727370751667073544569700178629220785132928323860004505356526,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 220948536 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 220948536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"2.rv_dm_stress_all.114839668442769610715044001438703078614939182625363022630726387885494112016274","seed":114839668442769610715044001438703078614939182625363022630726387885494112016274,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 159282142 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 159282142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"2.rv_dm_stress_all_with_rand_reset.102935781023024852452755893272790381162509913451003904628658716063058905993577","seed":102935781023024852452755893272790381162509913451003904628658716063058905993577,"line":94,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1305981411 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1305981411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"3.rv_dm_stress_all_with_rand_reset.76920459053376242048190833810127486397943216646295628750744243140667090961714","seed":76920459053376242048190833810127486397943216646295628750744243140667090961714,"line":130,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3302169724 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 3302169724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"6.rv_dm_stress_all.96393299556397179457614432456655268599120054152863497149849633999294051352037","seed":96393299556397179457614432456655268599120054152863497149849633999294051352037,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 474603896 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 474603896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"8.rv_dm_stress_all.33190197169788664199259592970701882663832902410879858528314149242638502704317","seed":33190197169788664199259592970701882663832902410879858528314149242638502704317,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @  84279412 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  84279412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"15.rv_dm_stress_all.90527262179916139314763263432578423520774914425869441111088215849481695634857","seed":90527262179916139314763263432578423520774914425869441111088215849481695634857,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/15.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 190154336 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 190154336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"16.rv_dm_stress_all.2197428676136363450874980064871417407128532608433484703257414452879754297815","seed":2197428676136363450874980064871417407128532608433484703257414452879754297815,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/16.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 246719226 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 246719226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"23.rv_dm_stress_all.73963459780769795207730865431319847814272116358500082283666474495184534430318","seed":73963459780769795207730865431319847814272116358500082283666474495184534430318,"line":81,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/23.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 2594413321 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 2594413321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"24.rv_dm_stress_all.19744256693145594170495885390747774694555678558658282030049761331581610961535","seed":19744256693145594170495885390747774694555678558658282030049761331581610961535,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/24.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 3438897827 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 3438897827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"28.rv_dm_stress_all.83147059116658830606736164294886515045554579248479230609629510992883881267561","seed":83147059116658830606736164294886515045554579248479230609629510992883881267561,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/28.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 549845674 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 549845674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"33.rv_dm_stress_all.27957975864690336599093122882857142438282044744101945280382816772046957614324","seed":27957975864690336599093122882857142438282044744101945280382816772046957614324,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/33.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 335853834 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 335853834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"39.rv_dm_stress_all.62424278383573554448961307195983039461067615042460994933093391529548515751510","seed":62424278383573554448961307195983039461067615042460994933093391529548515751510,"line":81,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/39.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 2064813667 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 2064813667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"43.rv_dm_stress_all.5338385944952625421554650655545321097247195130784383494963448490934230184771","seed":5338385944952625421554650655545321097247195130784383494963448490934230184771,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/43.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 175873206 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 175873206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"49.rv_dm_stress_all.33358739175439830063414599710687849372398970703432439817757549002338731031072","seed":33358739175439830063414599710687849372398970703432439817757549002338731031072,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/49.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @  97241623 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  97241623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [*] vs * [*])":[{"name":"rv_dm_hart_unavail","qual_name":"0.rv_dm_hart_unavail.17014164761685601439678496068449631648148719226431826742432101252553870394598","seed":17014164761685601439678496068449631648148719226431826742432101252553870394598,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest/run.log","log_context":["UVM_ERROR @  49147164 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  49147164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"0.rv_dm_stress_all.92759769842241057610944028672162595702756099558230841651949545952563067225171","seed":92759769842241057610944028672162595702756099558230841651949545952563067225171,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1780068987 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1780068987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"0.rv_dm_stress_all_with_rand_reset.52945039203952719903375256112437629688070873411032609261251139547044362078313","seed":52945039203952719903375256112437629688070873411032609261251139547044362078313,"line":147,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3797299077 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 3797299077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_hart_unavail","qual_name":"1.rv_dm_hart_unavail.104806901494385756775857128332619028887153513281396498181680123971501261542265","seed":104806901494385756775857128332619028887153513281396498181680123971501261542265,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_hart_unavail/latest/run.log","log_context":["UVM_ERROR @ 127514794 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 127514794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_hart_unavail","qual_name":"2.rv_dm_hart_unavail.97808954502355729546211264136235550088901502963222091765241438327235751083997","seed":97808954502355729546211264136235550088901502963222091765241438327235751083997,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/2.rv_dm_hart_unavail/latest/run.log","log_context":["UVM_ERROR @  69443621 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  69443621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_hart_unavail","qual_name":"3.rv_dm_hart_unavail.94803886333432066472042612199895122918088018940705816774168483806107324127377","seed":94803886333432066472042612199895122918088018940705816774168483806107324127377,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_hart_unavail/latest/run.log","log_context":["UVM_ERROR @  38329105 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @  38329105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_hart_unavail","qual_name":"4.rv_dm_hart_unavail.73800762027348797657630425086709338221562458160325266878502972743759824297316","seed":73800762027348797657630425086709338221562458160325266878502972743759824297316,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_hart_unavail/latest/run.log","log_context":["UVM_ERROR @ 103232803 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 103232803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"5.rv_dm_stress_all_with_rand_reset.67124057478149572934833244927620227745833455813280092548681735770064176073338","seed":67124057478149572934833244927620227745833455813280092548681735770064176073338,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 376434182 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 376434182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"7.rv_dm_stress_all.61679905103807681137004683951084510630397786383249070555016603367027409594262","seed":61679905103807681137004683951084510630397786383249070555016603367027409594262,"line":83,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 3256297821 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 3256297821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"27.rv_dm_stress_all.53402433729766207627294606592354334146758734272486439302652226171198439593993","seed":53402433729766207627294606592354334146758734272486439302652226171198439593993,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/27.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 745330553 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 745330553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"30.rv_dm_stress_all.15893756277637068787238972028202886321778556780360541375702765390221795743905","seed":15893756277637068787238972028202886321778556780360541375702765390221795743905,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/30.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 267897127 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 267897127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"38.rv_dm_stress_all.102553381580903203439758613237215769146783986264958040905494380562838264049474","seed":102553381580903203439758613237215769146783986264958040905494380562838264049474,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/38.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 738432522 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 738432522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"45.rv_dm_stress_all.75645778795842545369607782816801498208883898617202528925405196875723034898496","seed":75645778795842545369607782816801498208883898617202528925405196875723034898496,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/45.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 416345340 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 416345340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*])":[{"name":"rv_dm_jtag_dmi_debug_disabled","qual_name":"0.rv_dm_jtag_dmi_debug_disabled.28108608653521537988862373452321747393063778747972300895773665243846728457681","seed":28108608653521537988862373452321747393063778747972300895773665243846728457681,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log","log_context":["UVM_ERROR @ 473048610 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1072979875 [0x3ff45fa3] vs 0 [0x0]) \n","UVM_INFO @ 473048610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_jtag_dmi_debug_disabled","qual_name":"1.rv_dm_jtag_dmi_debug_disabled.83631769563025474882106016349159852988676240336947467633110329766936458043011","seed":83631769563025474882106016349159852988676240336947467633110329766936458043011,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest/run.log","log_context":["UVM_ERROR @ 201708458 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3549110823 [0xd38b2227] vs 0 [0x0]) \n","UVM_INFO @ 201708458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"3.rv_dm_stress_all.20950393332680667954517514507841754047191236560132545644145851644906896161230","seed":20950393332680667954517514507841754047191236560132545644145851644906896161230,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/3.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 989829455 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2158035604 [0x80a10294] vs 0 [0x0]) \n","UVM_INFO @ 989829455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"4.rv_dm_stress_all.18394627116730829432139325070210572791233323109699145553951748437930003589058","seed":18394627116730829432139325070210572791233323109699145553951748437930003589058,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1542676976 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3851825011 [0xe5962f73] vs 0 [0x0]) \n","UVM_INFO @ 1542676976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"5.rv_dm_stress_all.95683146911034107467114637868401956693999108679399056495572392637449662226654","seed":95683146911034107467114637868401956693999108679399056495572392637449662226654,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/5.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 343987331 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (638967106 [0x2615dd42] vs 0 [0x0]) \n","UVM_INFO @ 343987331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"6.rv_dm_stress_all_with_rand_reset.113132274091965311646775233656111355392752468628632124880555822725765824699469","seed":113132274091965311646775233656111355392752468628632124880555822725765824699469,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 253732008 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1992292260 [0x76bff7a4] vs 0 [0x0]) \n","UVM_INFO @ 253732008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"7.rv_dm_stress_all_with_rand_reset.18144704013552732929345926888751202568008733357543471619455702494479891696719","seed":18144704013552732929345926888751202568008733357543471619455702494479891696719,"line":84,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1301954884 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2903815721 [0xad14b629] vs 0 [0x0]) \n","UVM_INFO @ 1301954884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"8.rv_dm_stress_all_with_rand_reset.79156563107393619319390658140848816306493826080321085216289695038070421469263","seed":79156563107393619319390658140848816306493826080321085216289695038070421469263,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 107335274 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (175562142 [0xa76dd9e] vs 0 [0x0]) \n","UVM_INFO @ 107335274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"13.rv_dm_stress_all.47100858697754779768619143892993197801444985868126345806815858265706988263451","seed":47100858697754779768619143892993197801444985868126345806815858265706988263451,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/13.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 189489087 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2066440766 [0x7b2b623e] vs 0 [0x0]) \n","UVM_INFO @ 189489087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"14.rv_dm_stress_all.92420704620405198995162228203065055043562432381748116172930703918616065053800","seed":92420704620405198995162228203065055043562432381748116172930703918616065053800,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/14.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 712832959 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3640140357 [0xd8f82245] vs 0 [0x0]) \n","UVM_INFO @ 712832959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"17.rv_dm_stress_all.2602062126963445124355570137427883261981288313569170745211672601895939721742","seed":2602062126963445124355570137427883261981288313569170745211672601895939721742,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/17.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @  99572161 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3264431659 [0xc293462b] vs 0 [0x0]) \n","UVM_INFO @  99572161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"21.rv_dm_stress_all.5275685580618399240404364861954910758183637059637783448927056700423174712448","seed":5275685580618399240404364861954910758183637059637783448927056700423174712448,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/21.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 216360549 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2920293487 [0xae10246f] vs 0 [0x0]) \n","UVM_INFO @ 216360549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"22.rv_dm_stress_all.29845480906771214349688064125511735896221411937658427952856791566562519284986","seed":29845480906771214349688064125511735896221411937658427952856791566562519284986,"line":83,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/22.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 2346021989 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2450640695 [0x9211cf37] vs 0 [0x0]) \n","UVM_INFO @ 2346021989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"26.rv_dm_stress_all.106130065588323019151357789863876899574227503046682123861226806451825298149363","seed":106130065588323019151357789863876899574227503046682123861226806451825298149363,"line":81,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/26.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1314055873 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1365960751 [0x516ae82f] vs 0 [0x0]) \n","UVM_INFO @ 1314055873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"29.rv_dm_stress_all.71805426574085384293705963715794646016193306109620137335328532415983566079733","seed":71805426574085384293705963715794646016193306109620137335328532415983566079733,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/29.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 666696491 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (742919426 [0x2c480d02] vs 0 [0x0]) \n","UVM_INFO @ 666696491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"31.rv_dm_stress_all.60071768419192823951321376013330124733300608287920021962355802941817388168692","seed":60071768419192823951321376013330124733300608287920021962355802941817388168692,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/31.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1176155973 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (635728905 [0x25e47409] vs 0 [0x0]) \n","UVM_INFO @ 1176155973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"32.rv_dm_stress_all.77829856248580777523994507732414253785572334086753284482193526249570494509427","seed":77829856248580777523994507732414253785572334086753284482193526249570494509427,"line":79,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/32.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 303155352 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3571082101 [0xd4da6375] vs 0 [0x0]) \n","UVM_INFO @ 303155352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"37.rv_dm_stress_all.28771285756943602233135526129010692805247151335352501426140129097119092948844","seed":28771285756943602233135526129010692805247151335352501426140129097119092948844,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/37.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 8124559073 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2054905696 [0x7a7b5f60] vs 0 [0x0]) \n","UVM_INFO @ 8124559073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"42.rv_dm_stress_all.88842490453005932478730319796006425110353084545128144562685928649025894909293","seed":88842490453005932478730319796006425110353084545128144562685928649025894909293,"line":84,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/42.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 6180708113 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (4037757513 [0xf0ab4a49] vs 0 [0x0]) \n","UVM_INFO @ 6180708113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"46.rv_dm_stress_all.17777075179389043733726651045774538276730402669726443451339744980423433706602","seed":17777075179389043733726651045774538276730402669726443451339744980423433706602,"line":81,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/46.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1457531216 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1177822662 [0x463425c6] vs 0 [0x0]) \n","UVM_INFO @ 1457531216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"48.rv_dm_stress_all.468910040277752669855962469453075259642074717202358138728062528785111292692","seed":468910040277752669855962469453075259642074717202358138728062528785111292692,"line":78,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/48.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 198153935 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2355665320 [0x8c6899a8] vs 0 [0x0]) \n","UVM_INFO @ 198153935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_debug_disabled_vseq.sv:33) [rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output)":[{"name":"rv_dm_debug_disabled","qual_name":"1.rv_dm_debug_disabled.86074832831423840102061360977906628370583247053275226053775369728082671340001","seed":86074832831423840102061360977906628370583247053275226053775369728082671340001,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_debug_disabled/latest/run.log","log_context":["UVM_ERROR @ 147870565 ps: (rv_dm_debug_disabled_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output)  \n","UVM_INFO @ 147870565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (cip_base_vseq.sv:1170) [rv_dm_common_vseq] Check failed (vseq_done)":[{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"1.rv_dm_stress_all_with_rand_reset.40969378985950991682487035823119328444032316865918646797788664761729722516727","seed":40969378985950991682487035823119328444032316865918646797788664761729722516727,"line":106,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 7838221274 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)  \n","UVM_INFO @ 7838221274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"4.rv_dm_stress_all_with_rand_reset.56158339392178447798312046049508840151831752236475721684942723029907197559107","seed":56158339392178447798312046049508840151831752236475721684942723029907197559107,"line":115,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 6824958342 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)  \n","UVM_INFO @ 6824958342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [*] vs * [*])":[{"name":"rv_dm_buffered_enable","qual_name":"6.rv_dm_buffered_enable.21980657342438965094405545682286035534649308485546587141844534322271168056056","seed":21980657342438965094405545682286035534649308485546587141844534322271168056056,"line":84,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/6.rv_dm_buffered_enable/latest/run.log","log_context":["UVM_ERROR @ 661713524 ps: (rv_dm_buffered_enable_vseq.sv:164) [uvm_test_top.env.virtual_sequencer.rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 661713524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job timed out after * minutes":[{"name":"rv_dm_stress_all","qual_name":"9.rv_dm_stress_all.80211764007520687245254483946030409422382417312657629233775597054826006759196","seed":80211764007520687245254483946030409422382417312657629233775597054826006759196,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/9.rv_dm_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"rv_dm_stress_all","qual_name":"11.rv_dm_stress_all.76634040445017635169606279217524886226056288839088048691574585295353450063239","seed":76634040445017635169606279217524886226056288839088048691574585295353450063239,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/11.rv_dm_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"rv_dm_stress_all","qual_name":"34.rv_dm_stress_all.78128745286172327551038668562348200785661363727086357955582447208807622699977","seed":78128745286172327551038668562348200785661363727086357955582447208807622699977,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/34.rv_dm_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"rv_dm_stress_all","qual_name":"35.rv_dm_stress_all.50260515196533516144343376178210242047902624501130059425448516061928070056447","seed":50260515196533516144343376178210242047902624501130059425448516061928070056447,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/35.rv_dm_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"rv_dm_stress_all","qual_name":"40.rv_dm_stress_all.99580947195542872429836425763056376767668282632898897939652183965578321104694","seed":99580947195542872429836425763056376767668282632898897939652183965578321104694,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/40.rv_dm_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"rv_dm_stress_all","qual_name":"41.rv_dm_stress_all.81350070951585203387856293008457063835153832455057496291862751336205247205764","seed":81350070951585203387856293008457063835153832455057496291862751336205247205764,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/41.rv_dm_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"rv_dm_stress_all","qual_name":"47.rv_dm_stress_all.61661220079614911717271832550916165700011315243148586861920434517491778378135","seed":61661220079614911717271832550916165700011315243148586861920434517491778378135,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/47.rv_dm_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]}]}},"passed":337,"total":483,"percent":69.77225672877847}