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5,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sram_ctrl_stress_all_with_rand_reset":{"max_time":51.0,"sim_time":4735.663855000001,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0}},"coverage":{"code":{"block":94.01,"line_statement":95.19,"branch":89.83,"condition_expression":null,"toggle":82.28,"fsm":66.67},"assertion":96.43,"functional":97.0},"cov_report_page":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cov_report/index.html","failed_jobs":{"buckets":{"UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: *":[{"name":"sram_ctrl_csr_mem_rw_with_rand_reset","qual_name":"2.sram_ctrl_csr_mem_rw_with_rand_reset.27746621605236552280759963804345527122387296294211293808253750557889850190109","seed":27746621605236552280759963804345527122387296294211293808253750557889850190109,"line":88,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  88082338 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (11 [0xb] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9 \n","UVM_INFO @  88082338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_csr_mem_rw_with_rand_reset","qual_name":"15.sram_ctrl_csr_mem_rw_with_rand_reset.17520857922634918392798988354720206805095427321318367189647705349628847171537","seed":17520857922634918392798988354720206805095427321318367189647705349628847171537,"line":94,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  31884665 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (5 [0x5] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9 \n","UVM_INFO @  31884665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: *":[{"name":"sram_ctrl_csr_mem_rw_with_rand_reset","qual_name":"8.sram_ctrl_csr_mem_rw_with_rand_reset.67921690936283749470352922325311776037121124411503259004911444961333681173711","seed":67921690936283749470352922325311776037121124411503259004911444961333681173711,"line":88,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 368915669 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0 \n","UVM_INFO @ 368915669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!":[{"name":"sram_ctrl_max_throughput","qual_name":"0.sram_ctrl_max_throughput.66505274496502352867489244193614604657015091125746699703259900533588142684214","seed":66505274496502352867489244193614604657015091125746699703259900533588142684214,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_FATAL @  22476887 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2;         mask dist {'1 :/ 100 - partial_access_pct,                    [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! \n","UVM_INFO @  22476887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"0.sram_ctrl_throughput_w_readback.19930239682402698564595182458615920658777526890278963349981699795156422469300","seed":19930239682402698564595182458615920658777526890278963349981699795156422469300,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_FATAL @ 103937944 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2;         mask dist {'1 :/ 100 - partial_access_pct,                    [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! \n","UVM_INFO @ 103937944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_max_throughput","qual_name":"1.sram_ctrl_max_throughput.89018585458675937953633866057683608000817584495215814247730901525500313612762","seed":89018585458675937953633866057683608000817584495215814247730901525500313612762,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_FATAL @  87928504 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2;         mask dist {'1 :/ 100 - partial_access_pct,                    [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! \n","UVM_INFO @  87928504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"1.sram_ctrl_throughput_w_readback.9313734999690652309710893607515222516681454769819084643370869670800530789552","seed":9313734999690652309710893607515222516681454769819084643370869670800530789552,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_FATAL @ 166682660 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2;         mask dist {'1 :/ 100 - partial_access_pct,                    [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! \n","UVM_INFO @ 166682660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_max_throughput","qual_name":"2.sram_ctrl_max_throughput.111038766405268547818337635578072186320813037593944108603402697258331349177332","seed":111038766405268547818337635578072186320813037593944108603402697258331349177332,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_FATAL @ 121959456 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2;         mask dist {'1 :/ 100 - partial_access_pct,                    [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! \n","UVM_INFO @ 121959456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"2.sram_ctrl_throughput_w_readback.4969762468626698522252800757959671784982815136980786255586070247777629935920","seed":4969762468626698522252800757959671784982815136980786255586070247777629935920,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_FATAL @  90524474 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2;         mask dist {'1 :/ 100 - partial_access_pct,                    [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! \n","UVM_INFO @  90524474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_max_throughput","qual_name":"3.sram_ctrl_max_throughput.50543126864602173540691315037218967978922993095638999218394421275553210205299","seed":50543126864602173540691315037218967978922993095638999218394421275553210205299,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_FATAL @  89306957 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2;         mask dist {'1 :/ 100 - partial_access_pct,                    [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! \n","UVM_INFO @  89306957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"3.sram_ctrl_throughput_w_readback.9671520158856319296037166779669229386326709555488191541164134875242718970766","seed":9671520158856319296037166779669229386326709555488191541164134875242718970766,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_FATAL @  33047765 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2;         mask dist {'1 :/ 100 - partial_access_pct,                    [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! \n","UVM_INFO @  33047765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_max_throughput","qual_name":"4.sram_ctrl_max_throughput.114507241642001454619033567992456392718362573762862908955537924029555027930410","seed":114507241642001454619033567992456392718362573762862908955537924029555027930410,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_FATAL @  37887150 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2;         mask dist {'1 :/ 100 - partial_access_pct,                    [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! \n","UVM_INFO @  37887150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"4.sram_ctrl_throughput_w_readback.48929284685148690671289307151414933366552884287349579573516769043395859208769","seed":48929284685148690671289307151414933366552884287349579573516769043395859208769,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_FATAL @ 115822213 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2;         mask dist {'1 :/ 100 - partial_access_pct,                    [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! \n","UVM_INFO @ 115822213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"xmsim: *E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_*/rtl/tlul_assert.sv,319): Assertion noOutstandingReqsAtEndOfSim_A has failed":[{"name":"sram_ctrl_alert_test","qual_name":"5.sram_ctrl_alert_test.7179508422782669267936464984843233175796828871384101636481180473909441003861","seed":7179508422782669267936464984843233175796828871384101636481180473909441003861,"line":122,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_alert_test/latest/run.log","log_context":["xmsim: *E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv,319): (time 33579117 PS) Assertion tb.dut.tlul_assert_device_regs.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A has failed \n","xmsim: *W,SLFINV: Call to process::self() from invalid process; returning null.\n","xmsim: *W,SLFINV: Call to process::self() from invalid process; returning null.\n","xmsim: *W,SLFINV: Call to process::self() from invalid process; returning null.\n","xmsim: *W,SLFINV: Call to process::self() from invalid process; returning null.\n"]}]}},"passed":276,"total":290,"percent":95.17241379310344}