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---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"5.alert_handler_ping_timeout.54301108187775409377950910363305168033670803596577848315233448172488169867916","seed":54301108187775409377950910363305168033670803596577848315233448172488169867916,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 12375121388 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 12375121388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"8.alert_handler_ping_timeout.55070658714341536180242409245409816241204789245992488396029886339213643758278","seed":55070658714341536180242409245409816241204789245992488396029886339213643758278,"line":156,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 51669363894 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 51669363894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"10.alert_handler_ping_timeout.109992222028003879642124736056267000904314931755377175763410296216329724461485","seed":109992222028003879642124736056267000904314931755377175763410296216329724461485,"line":153,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 18589077178 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 18589077178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"11.alert_handler_ping_timeout.22402295268965725187183529954567870641855928108918146774884890861511036921266","seed":22402295268965725187183529954567870641855928108918146774884890861511036921266,"line":123,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 7010687766 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 7010687766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"12.alert_handler_ping_timeout.21597399169120875066065947206902839588032898597099368396404818250739430976981","seed":21597399169120875066065947206902839588032898597099368396404818250739430976981,"line":117,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 13505771634 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 13505771634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"16.alert_handler_ping_timeout.88042399902281017801034482363927696496278198803273728301708313773206327923041","seed":88042399902281017801034482363927696496278198803273728301708313773206327923041,"line":126,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 7781630439 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 7781630439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"21.alert_handler_ping_timeout.20840404182384806976164140580011548618233716790350708600087534044616154931086","seed":20840404182384806976164140580011548618233716790350708600087534044616154931086,"line":120,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 8128140946 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 8128140946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"22.alert_handler_ping_timeout.63912006268579039826857586267853536135102708417161584845528534397330806844279","seed":63912006268579039826857586267853536135102708417161584845528534397330806844279,"line":105,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 10735508208 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 10735508208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"23.alert_handler_ping_timeout.59699360142521885845332582388632724553274936550818501641611539537678513196274","seed":59699360142521885845332582388632724553274936550818501641611539537678513196274,"line":90,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 28260098745 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 28260098745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"24.alert_handler_ping_timeout.107212832430441946514630865679375891870782028956590990255345105873713507539586","seed":107212832430441946514630865679375891870782028956590990255345105873713507539586,"line":87,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 3939873082 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 3939873082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"28.alert_handler_ping_timeout.27939020891266007695234295187538027076553995495503161373390516770037162165506","seed":27939020891266007695234295187538027076553995495503161373390516770037162165506,"line":90,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 3055744879 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 3055744879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"34.alert_handler_ping_timeout.61113911709092192677552795077906719456826284359016210419021976478616610593149","seed":61113911709092192677552795077906719456826284359016210419021976478616610593149,"line":117,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 5078177645 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 5078177645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"35.alert_handler_ping_timeout.99967766409463470716798028051195081523622596231605369208221408393111599231236","seed":99967766409463470716798028051195081523622596231605369208221408393111599231236,"line":87,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 2963357344 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 2963357344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"38.alert_handler_ping_timeout.26528810913563261608792783812433710772442403627233012122578749808335489524716","seed":26528810913563261608792783812433710772442403627233012122578749808335489524716,"line":87,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 2962776800 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 2962776800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"41.alert_handler_ping_timeout.76822451985651988083253058026256471162742623541514504784379571228648580200988","seed":76822451985651988083253058026256471162742623541514504784379571228648580200988,"line":93,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 8350211767 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 8350211767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"42.alert_handler_ping_timeout.10063859943538311248845307801018191748890382315434657762393095293477643698896","seed":10063859943538311248845307801018191748890382315434657762393095293477643698896,"line":108,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/42.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 6990262983 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 6990262983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"46.alert_handler_ping_timeout.74814661885066682475306255650445729517374011993339836308352235635834553623421","seed":74814661885066682475306255650445729517374011993339836308352235635834553623421,"line":91,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 6226301924 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 6226301924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"49.alert_handler_ping_timeout.81953525248415032689736634740528046695230926167073152702678464755727167476705","seed":81953525248415032689736634740528046695230926167073152702678464755727167476705,"line":93,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 3140233455 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 3140233455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_state":[{"name":"alert_handler_sig_int_fail","qual_name":"2.alert_handler_sig_int_fail.42661366988562020000005151432820684240539791919441968249901494763414452790488","seed":42661366988562020000005151432820684240539791919441968249901494763414452790488,"line":83,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest/run.log","log_context":["UVM_ERROR @ 669176859 ps: (alert_handler_scoreboard.sv:490) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 6 [0x6]) reg name: alert_handler_reg_block.classa_state\n","UVM_INFO @ 669176859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model.":[{"name":"alert_handler_ping_timeout","qual_name":"2.alert_handler_ping_timeout.41277610727596617680983044495512103513866287560628934459222377266614682215966","seed":41277610727596617680983044495512103513866287560628934459222377266614682215966,"line":81,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 692057451 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 692057451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"20.alert_handler_ping_timeout.4402320425414356745013211198263252121671635022797649065906329648165622521392","seed":4402320425414356745013211198263252121671635022797649065906329648165622521392,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 2992562420 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 2992562420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"33.alert_handler_ping_timeout.84146305391574305434667777659122952482321818733224270154887569877523099595278","seed":84146305391574305434667777659122952482321818733224270154887569877523099595278,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 395518125 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 395518125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"39.alert_handler_ping_timeout.66506821651548183466178466389585435403293119943384044405628892994350237726490","seed":66506821651548183466178466389585435403293119943384044405628892994350237726490,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/39.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 364799936 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 364799936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"3.alert_handler_stress_all_with_rand_reset.109032840623945761824501414937187709622695406112956688033328305364046356893657","seed":109032840623945761824501414937187709622695406112956688033328305364046356893657,"line":93,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 669223678 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 669223678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"4.alert_handler_stress_all_with_rand_reset.103871841911193963879259103355127385992701903906077953996909856074520803430422","seed":103871841911193963879259103355127385992701903906077953996909856074520803430422,"line":138,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1787614909 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1787614909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"6.alert_handler_stress_all_with_rand_reset.22055496770209494740337226404613979725774322805897954011193717887957337793503","seed":22055496770209494740337226404613979725774322805897954011193717887957337793503,"line":154,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4999811284 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4999811284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"9.alert_handler_stress_all_with_rand_reset.112765474937221200809637376031385262373649504464108270318831517264872691481331","seed":112765474937221200809637376031385262373649504464108270318831517264872691481331,"line":134,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5456448882 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5456448882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"10.alert_handler_stress_all_with_rand_reset.82484266701173100182895834682244624668251860901086708415899361546267488258449","seed":82484266701173100182895834682244624668251860901086708415899361546267488258449,"line":83,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 500024967 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 500024967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"17.alert_handler_stress_all_with_rand_reset.18476886437517555798042286896811799924437964249363266083446905238618330749456","seed":18476886437517555798042286896811799924437964249363266083446905238618330749456,"line":95,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1021584936 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1021584936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"18.alert_handler_stress_all_with_rand_reset.113614402260836331171765597281670561346502787886970875634260364097271306894319","seed":113614402260836331171765597281670561346502787886970875634260364097271306894319,"line":114,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6273121882 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 6273121882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"19.alert_handler_stress_all_with_rand_reset.99558339354781602370545941091541456145025219312625947632648486453403569904913","seed":99558339354781602370545941091541456145025219312625947632648486453403569904913,"line":116,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1938299391 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1938299391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"24.alert_handler_stress_all_with_rand_reset.14057395891928779423338310915099335877706300519114475232930640847687567830044","seed":14057395891928779423338310915099335877706300519114475232930640847687567830044,"line":102,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 919514440 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 919514440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"27.alert_handler_stress_all_with_rand_reset.70923235583608739867859265114078508549651414825670951905153951570144541401439","seed":70923235583608739867859265114078508549651414825670951905153951570144541401439,"line":112,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7489642207 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 7489642207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"29.alert_handler_stress_all_with_rand_reset.94562701928253622286010427400716462033323453562951578803616412491275791660466","seed":94562701928253622286010427400716462033323453562951578803616412491275791660466,"line":133,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/29.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1537051706 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1537051706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"31.alert_handler_stress_all_with_rand_reset.37168817385680751267996040892097479137726945896321278140528235989493267193271","seed":37168817385680751267996040892097479137726945896321278140528235989493267193271,"line":127,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2157266556 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2157266556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"32.alert_handler_stress_all_with_rand_reset.62440417373537752298273820752322789371054359082604755343978587822215728564577","seed":62440417373537752298273820752322789371054359082604755343978587822215728564577,"line":83,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/32.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2064877469 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2064877469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"34.alert_handler_stress_all_with_rand_reset.19119095159955706729455200576809178251205526188021756404927220074752984143372","seed":19119095159955706729455200576809178251205526188021756404927220074752984143372,"line":116,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/34.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 20294227505 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 20294227505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"40.alert_handler_stress_all_with_rand_reset.29141928480475311929851775680339825174661414927997840490453480094295401972413","seed":29141928480475311929851775680339825174661414927997840490453480094295401972413,"line":173,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7831056480 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 7831056480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"43.alert_handler_stress_all_with_rand_reset.20418332064513969919520477151929706904074901752966068365239798799069908182842","seed":20418332064513969919520477151929706904074901752966068365239798799069908182842,"line":106,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/43.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 11509077935 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 11509077935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"44.alert_handler_stress_all_with_rand_reset.106779967993556820642243802809653337610394503554227357066585047541612270915668","seed":106779967993556820642243802809653337610394503554227357066585047541612270915668,"line":149,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/44.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 22809309158 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 22809309158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"45.alert_handler_stress_all_with_rand_reset.40740266440534605102014900835924938212999054334869334043749214894377390994763","seed":40740266440534605102014900835924938212999054334869334043749214894377390994763,"line":165,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/45.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6865434717 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 6865434717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"47.alert_handler_stress_all_with_rand_reset.45755494751285253354581927099728727721345954425679606685314937856407544172826","seed":45755494751285253354581927099728727721345954425679606685314937856407544172826,"line":143,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/47.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1671017775 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1671017775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"48.alert_handler_stress_all_with_rand_reset.26625663222090566162694888359165633442435325494447129982032370429020636279140","seed":26625663222090566162694888359165633442435325494447129982032370429020636279140,"line":217,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/48.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 10208529905 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 10208529905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"49.alert_handler_stress_all_with_rand_reset.4235210324033469046358792855667684673503144930537892563081172735584082293575","seed":4235210324033469046358792855667684673503144930537892563081172735584082293575,"line":83,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/49.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 106603514 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 106603514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.loc_alert_cause_*":[{"name":"alert_handler_lpg","qual_name":"5.alert_handler_lpg.57380402392635889715980858576332577451981022791461693231448362748093556433968","seed":57380402392635889715980858576332577451981022791461693231448362748093556433968,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_lpg/latest/run.log","log_context":["UVM_ERROR @ 8945061276 ps: (alert_handler_scoreboard.sv:490) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: alert_handler_reg_block.loc_alert_cause_0\n","UVM_INFO @ 8945061276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_lpg_stub_clk","qual_name":"45.alert_handler_lpg_stub_clk.21224122446785414659975750244135073556729219139708698858202617388543609153538","seed":21224122446785414659975750244135073556729219139708698858202617388543609153538,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/45.alert_handler_lpg_stub_clk/latest/run.log","log_context":["UVM_ERROR @ 111586137775 ps: (alert_handler_scoreboard.sv:490) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: alert_handler_reg_block.loc_alert_cause_0\n","UVM_INFO @ 111586137775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"alert_handler_lpg_stub_clk","qual_name":"27.alert_handler_lpg_stub_clk.44194124664178592216599730332102044493607842708217064781507323692756527123680","seed":44194124664178592216599730332102044493607842708217064781507323692756527123680,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_lpg_stub_clk/latest/run.log","log_context":["UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":802,"total":850,"percent":94.3529411764706}