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[`5b8f674`](https://github.com/lowrisc/opentitan/tree/5b8f6746131e231116e685585432b70359d2c727)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-20T00:07:04Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"clkmgr_smoke":{"max_time":2.05,"sim_time":204.832732,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.77,"sim_time":101.87416800000001,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"clkmgr_csr_rw":{"max_time":1.25,"sim_time":38.327107000000005,"passed":6,"total":20,"percent":30.0}},"passed":6,"total":20,"percent":30.0},"csr_bit_bash":{"tests":{"clkmgr_csr_bit_bash":{"max_time":12.22,"sim_time":1443.746766,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"csr_aliasing":{"tests":{"clkmgr_csr_aliasing":{"max_time":1.69,"sim_time":74.20413099999999,"passed":1,"total":5,"percent":20.0}},"passed":1,"total":5,"percent":20.0},"csr_mem_rw_with_rand_reset":{"tests":{"clkmgr_csr_mem_rw_with_rand_reset":{"max_time":3.73,"sim_time":211.21400500000001,"passed":13,"total":20,"percent":65.0}},"passed":13,"total":20,"percent":65.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"clkmgr_csr_rw":{"max_time":1.25,"sim_time":38.327107000000005,"passed":6,"total":20,"percent":30.0},"clkmgr_csr_aliasing":{"max_time":1.69,"sim_time":74.20413099999999,"passed":1,"total":5,"percent":20.0}},"passed":7,"total":25,"percent":28.0}},"passed":75,"total":105,"percent":71.42857142857143},"V2":{"testpoints":{"peri_enables":{"tests":{"clkmgr_peri":{"max_time":1.41,"sim_time":109.029854,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"trans_enables":{"tests":{"clkmgr_trans":{"max_time":2.6,"sim_time":261.369983,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"clk_status":{"tests":{"clkmgr_clk_status":{"max_time":1.78,"sim_time":194.888227,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"jitter":{"tests":{"clkmgr_smoke":{"max_time":2.05,"sim_time":204.832732,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"frequency":{"tests":{"clkmgr_frequency":{"max_time":1.15,"sim_time":74.541092,"passed":1,"total":50,"percent":2.0}},"passed":1,"total":50,"percent":2.0},"frequency_timeout":{"tests":{"clkmgr_frequency_timeout":{"max_time":0.82,"sim_time":22.767249,"passed":1,"total":50,"percent":2.0}},"passed":1,"total":50,"percent":2.0},"frequency_overflow":{"tests":{"clkmgr_frequency":{"max_time":1.15,"sim_time":74.541092,"passed":1,"total":50,"percent":2.0}},"passed":1,"total":50,"percent":2.0},"stress_all":{"tests":{"clkmgr_stress_all":{"max_time":5.34,"sim_time":577.851877,"passed":5,"total":50,"percent":10.0}},"passed":5,"total":50,"percent":10.0},"alert_test":{"tests":{"clkmgr_alert_test":{"max_time":1.29,"sim_time":83.727036,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"clkmgr_tl_errors":{"max_time":11.94,"sim_time":1240.7901029999998,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"clkmgr_tl_errors":{"max_time":11.94,"sim_time":1240.7901029999998,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.77,"sim_time":101.87416800000001,"passed":5,"total":5,"percent":100.0},"clkmgr_csr_rw":{"max_time":1.25,"sim_time":38.327107000000005,"passed":6,"total":20,"percent":30.0},"clkmgr_csr_aliasing":{"max_time":1.69,"sim_time":74.20413099999999,"passed":1,"total":5,"percent":20.0},"clkmgr_same_csr_outstanding":{"max_time":2.37,"sim_time":217.731241,"passed":3,"total":20,"percent":15.0}},"passed":15,"total":50,"percent":30.0},"tl_d_partial_access":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.77,"sim_time":101.87416800000001,"passed":5,"total":5,"percent":100.0},"clkmgr_csr_rw":{"max_time":1.25,"sim_time":38.327107000000005,"passed":6,"total":20,"percent":30.0},"clkmgr_csr_aliasing":{"max_time":1.69,"sim_time":74.20413099999999,"passed":1,"total":5,"percent":20.0},"clkmgr_same_csr_outstanding":{"max_time":2.37,"sim_time":217.731241,"passed":3,"total":20,"percent":15.0}},"passed":15,"total":50,"percent":30.0}},"passed":292,"total":470,"percent":62.12765957446808},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"clkmgr_tl_intg_err":{"max_time":1.51,"sim_time":99.861688,"passed":0,"total":20,"percent":0.0},"clkmgr_sec_cm":{"max_time":11.44,"sim_time":1420.7822409999999,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":25,"percent":20.0},"shadow_reg_update_error":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":3.46,"sim_time":342.96806699999996,"passed":20,"total":20,"percent":100.0}},"pas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(csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *":[{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"0.clkmgr_shadow_reg_errors_with_csr_rw.46126130197105721403572866663370427294323964051741523323406329642897609965554","seed":46126130197105721403572866663370427294323964051741523323406329642897609965554,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   8447647 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   8447647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_aliasing","qual_name":"1.clkmgr_csr_aliasing.94287846020423868676359119293502405978885768234999257664539311284298138547219","seed":94287846020423868676359119293502405978885768234999257664539311284298138547219,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_csr_aliasing/latest/run.log","log_context":["UVM_ERROR @  30207296 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  30207296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"2.clkmgr_shadow_reg_errors_with_csr_rw.90271462233230291460142612197799723057480918766384916808777122757695862715834","seed":90271462233230291460142612197799723057480918766384916808777122757695862715834,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3040971 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   3040971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"2.clkmgr_tl_intg_err.53787557947843545963948804446859324219008328910723315278306169564457494334386","seed":53787557947843545963948804446859324219008328910723315278306169564457494334386,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   4150483 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   4150483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"2.clkmgr_csr_rw.10447721412994373244154293676337028113425076794115104426104483897521438982389","seed":10447721412994373244154293676337028113425076794115104426104483897521438982389,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   9765343 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   9765343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_aliasing","qual_name":"2.clkmgr_csr_aliasing.45136017990222535266290072024825091419967118256632199269187672955530677765138","seed":45136017990222535266290072024825091419967118256632199269187672955530677765138,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_csr_aliasing/latest/run.log","log_context":["UVM_ERROR @   7212517 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   7212517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"2.clkmgr_csr_mem_rw_with_rand_reset.70980941235930937480715767203782431170117582857109705059939035005217177240582","seed":70980941235930937480715767203782431170117582857109705059939035005217177240582,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  11284875 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  11284875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_aliasing","qual_name":"3.clkmgr_csr_aliasing.59483176982067030010590432653563280385629656574349538517132805017752835199911","seed":59483176982067030010590432653563280385629656574349538517132805017752835199911,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_csr_aliasing/latest/run.log","log_context":["UVM_ERROR @   4160006 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   4160006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"3.clkmgr_csr_mem_rw_with_rand_reset.88146908531311300690500390519074138682478084039733079595395388047368718594684","seed":88146908531311300690500390519074138682478084039733079595395388047368718594684,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  46274795 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  46274795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"4.clkmgr_shadow_reg_errors_with_csr_rw.16609603778039195093519860715729046960944192768214388514010605954753610802027","seed":16609603778039195093519860715729046960944192768214388514010605954753610802027,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  23345633 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  23345633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"4.clkmgr_tl_intg_err.40462054782299813190994608533655541006861031167178186787541668637636964063645","seed":40462054782299813190994608533655541006861031167178186787541668637636964063645,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   9739445 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   9739445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"4.clkmgr_csr_rw.73807334079273902585669983233792898720545455980569428221308828418682301582973","seed":73807334079273902585669983233792898720545455980569428221308828418682301582973,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @  10715816 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  10715816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_aliasing","qual_name":"4.clkmgr_csr_aliasing.53991200608127162753145021110905241411799848719482467750047222108482603131418","seed":53991200608127162753145021110905241411799848719482467750047222108482603131418,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_csr_aliasing/latest/run.log","log_context":["UVM_ERROR @ 101192467 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @ 101192467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"4.clkmgr_csr_mem_rw_with_rand_reset.8876077414309990260220253898146324853189777433939383359400739308919325579618","seed":8876077414309990260220253898146324853189777433939383359400739308919325579618,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  25433895 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  25433895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"5.clkmgr_shadow_reg_errors_with_csr_rw.48171695092462000691571214472273586655243517782528054489687329265038717724655","seed":48171695092462000691571214472273586655243517782528054489687329265038717724655,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  10678475 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  10678475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"6.clkmgr_tl_intg_err.37168746355970072931547726048200201659600471077936750365270934433459336042913","seed":37168746355970072931547726048200201659600471077936750365270934433459336042913,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   9533759 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   9533759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"6.clkmgr_csr_rw.94852509333418649564489985347675371623292514567911022382534559358555332757262","seed":94852509333418649564489985347675371623292514567911022382534559358555332757262,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   5409293 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   5409293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"7.clkmgr_tl_intg_err.38194355498501818328418778944521588123656391021015259234934109037673236558415","seed":38194355498501818328418778944521588123656391021015259234934109037673236558415,"line":117,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  99861688 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  99861688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"8.clkmgr_tl_intg_err.19074106971693901167324774000225120277066143690698388292181978753397991795295","seed":19074106971693901167324774000225120277066143690698388292181978753397991795295,"line":90,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  32645772 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  32645772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"9.clkmgr_shadow_reg_errors_with_csr_rw.46307273545738757948798502609969963371190720508373824265026829502313605434351","seed":46307273545738757948798502609969963371190720508373824265026829502313605434351,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   5630839 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   5630839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"9.clkmgr_tl_intg_err.11345971724520384934636694428408301630937531045149002373678122070202111446782","seed":11345971724520384934636694428408301630937531045149002373678122070202111446782,"line":94,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  10655941 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  10655941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"9.clkmgr_csr_rw.72715320352567034686449545779106966929396036649097207690539026687155558433904","seed":72715320352567034686449545779106966929396036649097207690539026687155558433904,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2689506 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   2689506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"10.clkmgr_csr_rw.47679324765469134973391358780162785980175628772810932808254648587698205792036","seed":47679324765469134973391358780162785980175628772810932808254648587698205792036,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   5652109 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   5652109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"11.clkmgr_shadow_reg_errors_with_csr_rw.55161779579518685019424721472437105190077600824902252108541234768523724652806","seed":55161779579518685019424721472437105190077600824902252108541234768523724652806,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   6098899 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   6098899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"11.clkmgr_tl_intg_err.113022061945128567881809833344686530649587212501484345903045222060650888725743","seed":113022061945128567881809833344686530649587212501484345903045222060650888725743,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   2941864 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   2941864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"12.clkmgr_shadow_reg_errors_with_csr_rw.41774092060778447587911178694762311734865903704793736129996676771498981133160","seed":41774092060778447587911178694762311734865903704793736129996676771498981133160,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  10238859 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  10238859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"12.clkmgr_tl_intg_err.13524828288224605729573951073676443675898625731456370146600197929458016475719","seed":13524828288224605729573951073676443675898625731456370146600197929458016475719,"line":90,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  18982403 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  18982403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"12.clkmgr_csr_rw.21998433265016678010689482706604262371630695459911851505059057381238947751191","seed":21998433265016678010689482706604262371630695459911851505059057381238947751191,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3006837 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   3006837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"13.clkmgr_csr_rw.1168651463870820454542333378289754509153124488329701831375922104964945698747","seed":1168651463870820454542333378289754509153124488329701831375922104964945698747,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   7355623 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   7355623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"14.clkmgr_csr_rw.48738314412908840984278814852977712853284027231010099349862712007801281274981","seed":48738314412908840984278814852977712853284027231010099349862712007801281274981,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @  12060776 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  12060776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"15.clkmgr_shadow_reg_errors_with_csr_rw.101251327979431250857238138107104643691604816263779525816406185645467196086912","seed":101251327979431250857238138107104643691604816263779525816406185645467196086912,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  24038494 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  24038494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"15.clkmgr_tl_intg_err.792435056671738503228958836381081170023271335572195727023122671513716991529","seed":792435056671738503228958836381081170023271335572195727023122671513716991529,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  11047285 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  11047285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"16.clkmgr_shadow_reg_errors_with_csr_rw.82852106340839313430766629777561841577748934082610287401382158761096894483772","seed":82852106340839313430766629777561841577748934082610287401382158761096894483772,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  44616648 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  44616648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"17.clkmgr_shadow_reg_errors_with_csr_rw.205525413903305851277360839127143205319493026410705327338485954238747169408","seed":205525413903305851277360839127143205319493026410705327338485954238747169408,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  16687428 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  16687428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"18.clkmgr_shadow_reg_errors_with_csr_rw.114720237150441217462902316543235462551880059946246977243367367052848501682300","seed":114720237150441217462902316543235462551880059946246977243367367052848501682300,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   1466909 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   1466909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"19.clkmgr_shadow_reg_errors_with_csr_rw.109493055433118103432596292645626720090335730307175325619622186238662688502805","seed":109493055433118103432596292645626720090335730307175325619622186238662688502805,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  14975427 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  14975427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"19.clkmgr_csr_mem_rw_with_rand_reset.84191599887487882956018497503686968041048258098268624896463943647408477387996","seed":84191599887487882956018497503686968041048258098268624896463943647408477387996,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  21462342 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  21462342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: *":[{"name":"clkmgr_tl_intg_err","qual_name":"0.clkmgr_tl_intg_err.71448551782645725307717165433087722662834401639489130766554334715717023743548","seed":71448551782645725307717165433087722662834401639489130766554334715717023743548,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   3318110 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   3318110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"0.clkmgr_csr_rw.65784611723456678915045086923569588268402696653189822061570796554032997160368","seed":65784611723456678915045086923569588268402696653189822061570796554032997160368,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3473529 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   3473529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"1.clkmgr_shadow_reg_errors_with_csr_rw.22425360193103885330916960574332244895094146026000310070570910072386027601385","seed":22425360193103885330916960574332244895094146026000310070570910072386027601385,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   9204296 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   9204296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"1.clkmgr_tl_intg_err.77235772527838942004170370204130722950734115059875323073284005710098888149127","seed":77235772527838942004170370204130722950734115059875323073284005710098888149127,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   5349193 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   5349193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"3.clkmgr_shadow_reg_errors_with_csr_rw.62954882105796590618887949586797141445789395038684892233920711570437341884061","seed":62954882105796590618887949586797141445789395038684892233920711570437341884061,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2983150 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2983150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"3.clkmgr_tl_intg_err.62888115743736117512817837310267497666138416518000570145849869077880437645386","seed":62888115743736117512817837310267497666138416518000570145849869077880437645386,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   2774773 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2774773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"3.clkmgr_csr_rw.99481794730315962329486747788119297752321303671486261636608575511661612285314","seed":99481794730315962329486747788119297752321303671486261636608575511661612285314,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2415092 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2415092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"5.clkmgr_tl_intg_err.33060124887819810149944929777503219797946378004825266579346557094049559964616","seed":33060124887819810149944929777503219797946378004825266579346557094049559964616,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   2598930 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2598930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"6.clkmgr_shadow_reg_errors_with_csr_rw.68689610482626553363128461744606509450621386236491485108905856214556517050958","seed":68689610482626553363128461744606509450621386236491485108905856214556517050958,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  12260040 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  12260040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"7.clkmgr_shadow_reg_errors_with_csr_rw.89496340668565531746404179018278895033110072737803407815898766043983872078203","seed":89496340668565531746404179018278895033110072737803407815898766043983872078203,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  10808350 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  10808350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"8.clkmgr_shadow_reg_errors_with_csr_rw.61599607021499004565729016935604335232211970334521943005114653519325412076880","seed":61599607021499004565729016935604335232211970334521943005114653519325412076880,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   6233947 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   6233947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"8.clkmgr_csr_rw.12981444801737580110787954167216292330583643581814571167202371920709238808055","seed":12981444801737580110787954167216292330583643581814571167202371920709238808055,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3159941 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   3159941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"10.clkmgr_shadow_reg_errors_with_csr_rw.34356153255655818895081495086666377064530004320257573427011484164618951479052","seed":34356153255655818895081495086666377064530004320257573427011484164618951479052,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   5220234 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   5220234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"10.clkmgr_tl_intg_err.42198413010996570967582716209419755838214882466146078116990821779905513804262","seed":42198413010996570967582716209419755838214882466146078116990821779905513804262,"line":89,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   8296766 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   8296766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"11.clkmgr_csr_rw.56778680548012077938639130496287125775388682526367409102422743994457412657177","seed":56778680548012077938639130496287125775388682526367409102422743994457412657177,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @  35732081 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  35732081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"13.clkmgr_shadow_reg_errors_with_csr_rw.38900154565518737637938957300517362785666146402284069766090816257298890639902","seed":38900154565518737637938957300517362785666146402284069766090816257298890639902,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2313337 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2313337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"13.clkmgr_tl_intg_err.101349899855010889477899614458415468955336665476660560818149000096431996881437","seed":101349899855010889477899614458415468955336665476660560818149000096431996881437,"line":104,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  13396241 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  13396241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"13.clkmgr_csr_mem_rw_with_rand_reset.33403291891870945849177707942591563408474267237272603999497700568486386044669","seed":33403291891870945849177707942591563408474267237272603999497700568486386044669,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  87043628 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  87043628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"14.clkmgr_shadow_reg_errors_with_csr_rw.83864913234574281990159735899760852089693520729121810749242660403432094682571","seed":83864913234574281990159735899760852089693520729121810749242660403432094682571,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  33949588 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  33949588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"14.clkmgr_tl_intg_err.87735100546532340235716232061854672903006995063690633295528483289822230884413","seed":87735100546532340235716232061854672903006995063690633295528483289822230884413,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  24461278 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  24461278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"15.clkmgr_csr_mem_rw_with_rand_reset.60057618638433198409442703218686961975050977471359241383612848170705971373515","seed":60057618638433198409442703218686961975050977471359241383612848170705971373515,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  18897825 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  18897825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"16.clkmgr_tl_intg_err.24113009907187150149098133371179127009658586676102508684729438282453130141338","seed":24113009907187150149098133371179127009658586676102508684729438282453130141338,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   3100666 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   3100666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"16.clkmgr_csr_mem_rw_with_rand_reset.4816746166152901776806277827086622752566193543779581718169182254881869943526","seed":4816746166152901776806277827086622752566193543779581718169182254881869943526,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   2761076 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2761076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"17.clkmgr_tl_intg_err.40819069469530480009738669321068025912140736850041505082301400132174295507066","seed":40819069469530480009738669321068025912140736850041505082301400132174295507066,"line":97,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  16791517 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  16791517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"18.clkmgr_tl_intg_err.45242558248288580838932835265333674922282194209612307939206588263037131739216","seed":45242558248288580838932835265333674922282194209612307939206588263037131739216,"line":93,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   7841023 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   7841023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"18.clkmgr_csr_rw.109208541665899970597699278426076237637235179345438806418256320927397529573908","seed":109208541665899970597699278426076237637235179345438806418256320927397529573908,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   4533960 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   4533960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"19.clkmgr_tl_intg_err.69269012077034965866095170265047883017192068430016355933824487139951158264999","seed":69269012077034965866095170265047883017192068430016355933824487139951158264999,"line":85,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   3165732 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   3165732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"19.clkmgr_csr_rw.66355002076685179534817159895724743176764294147617623339861195621840634986817","seed":66355002076685179534817159895724743176764294147617623339861195621840634986817,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @  10704281 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  10704281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *":[{"name":"clkmgr_csr_bit_bash","qual_name":"0.clkmgr_csr_bit_bash.76878150226507064765233136032953348133516655403025774837916887834101870097345","seed":76878150226507064765233136032953348133516655403025774837916887834101870097345,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @ 180869335 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @ 180869335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_bit_bash","qual_name":"1.clkmgr_csr_bit_bash.99615232472825571301316662432712743119286409031345654616680422883723051442316","seed":99615232472825571301316662432712743119286409031345654616680422883723051442316,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @  36644916 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @  36644916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_bit_bash","qual_name":"2.clkmgr_csr_bit_bash.99384542817095424322161440714037403321546459820705136279251047382479433536488","seed":99384542817095424322161440714037403321546459820705136279251047382479433536488,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @ 1443746766 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @ 1443746766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_bit_bash","qual_name":"3.clkmgr_csr_bit_bash.24659598986112935107106489034932795835697985263178773479384679994656847670448","seed":24659598986112935107106489034932795835697985263178773479384679994656847670448,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @ 146675132 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @ 146675132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_bit_bash","qual_name":"4.clkmgr_csr_bit_bash.33858285263445646397593845333095870683135899008216073582149510474623049599196","seed":33858285263445646397593845333095870683135899008216073582149510474623049599196,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @  64448534 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @  64448534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch":[{"name":"clkmgr_same_csr_outstanding","qual_name":"0.clkmgr_same_csr_outstanding.108815995534526337816313430925939366212831284877189225356450274547844189710348","seed":108815995534526337816313430925939366212831284877189225356450274547844189710348,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   6741419 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x65c832a4 read out mismatch\n","UVM_INFO @   6741419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"1.clkmgr_same_csr_outstanding.53556462808690579522163561812893116172141347495512678338351711427479994536612","seed":53556462808690579522163561812893116172141347495512678338351711427479994536612,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   9346659 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x4c1e4a4 read out mismatch\n","UVM_INFO @   9346659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"3.clkmgr_same_csr_outstanding.50951492054737950196591935077613476429269610247611944786021514995011505271147","seed":50951492054737950196591935077613476429269610247611944786021514995011505271147,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   5285903 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xc6eb2f64 read out mismatch\n","UVM_INFO @   5285903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"4.clkmgr_same_csr_outstanding.102574934693661115229284074412131073854148657779445552059031321469054021887916","seed":102574934693661115229284074412131073854148657779445552059031321469054021887916,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   3538792 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xaa9e8624 read out mismatch\n","UVM_INFO @   3538792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"5.clkmgr_same_csr_outstanding.49766669316530115210991912555786424453898092962875005912391472189834821498451","seed":49766669316530115210991912555786424453898092962875005912391472189834821498451,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  80725342 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xe3b50724 read out mismatch\n","UVM_INFO @  80725342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"7.clkmgr_same_csr_outstanding.25579214340266423932060583346288654265881344797597991698951877576567652106740","seed":25579214340266423932060583346288654265881344797597991698951877576567652106740,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   9476924 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x8caea624 read out mismatch\n","UVM_INFO @   9476924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"8.clkmgr_same_csr_outstanding.16541612363061256561672340444242429405750281283191320255451138886532564072024","seed":16541612363061256561672340444242429405750281283191320255451138886532564072024,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   4924150 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xa058ec24 read out mismatch\n","UVM_INFO @   4924150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"9.clkmgr_same_csr_outstanding.82802519806195120436267021501787083465332767422973143779935387600406241922002","seed":82802519806195120436267021501787083465332767422973143779935387600406241922002,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  21660175 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x8aaff964 read out mismatch\n","UVM_INFO @  21660175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"11.clkmgr_same_csr_outstanding.30370368163159528613570150341157174286212381012808954787383865467863407209122","seed":30370368163159528613570150341157174286212381012808954787383865467863407209122,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   7025908 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x9edc3d64 read out mismatch\n","UVM_INFO @   7025908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"12.clkmgr_same_csr_outstanding.26277609401771756018700516709703548546611086540786399141937396073822895830470","seed":26277609401771756018700516709703548546611086540786399141937396073822895830470,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   2129455 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x6d9424 read out mismatch\n","UVM_INFO @   2129455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"13.clkmgr_same_csr_outstanding.48501051327682360910824506897450500616579476210225513677925231362568485819694","seed":48501051327682360910824506897450500616579476210225513677925231362568485819694,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   4513527 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x3300cae4 read out mismatch\n","UVM_INFO @   4513527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"14.clkmgr_same_csr_outstanding.54991019674336705559226643982711260472297556540465391850095085228070219966612","seed":54991019674336705559226643982711260472297556540465391850095085228070219966612,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   2248255 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xab805ce4 read out mismatch\n","UVM_INFO @   2248255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"15.clkmgr_same_csr_outstanding.97193796166469552646731405998735605277794715535644757916027046273157993423896","seed":97193796166469552646731405998735605277794715535644757916027046273157993423896,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   6492932 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xdee5c0e4 read out mismatch\n","UVM_INFO @   6492932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"16.clkmgr_same_csr_outstanding.33343463200959167209478314982279086939945592160299030861267005283057896053219","seed":33343463200959167209478314982279086939945592160299030861267005283057896053219,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   1959293 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x1d51024 read out mismatch\n","UVM_INFO @   1959293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"17.clkmgr_same_csr_outstanding.34010286957638552156669410386923204133501423563988861588626161803346883951926","seed":34010286957638552156669410386923204133501423563988861588626161803346883951926,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   5553074 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xd0c95ca4 read out mismatch\n","UVM_INFO @   5553074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"18.clkmgr_same_csr_outstanding.60351768941267548671789502814837428649094787893649621949959910865135374294158","seed":60351768941267548671789502814837428649094787893649621949959910865135374294158,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   2918090 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x1f15ffa4 read out mismatch\n","UVM_INFO @   2918090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"19.clkmgr_same_csr_outstanding.92533960401912520103356254256093182519812114701442403536935120824160029325298","seed":92533960401912520103356254256093182519812114701442403536935120824160029325298,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   8336175 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x3752bc64 read out mismatch\n","UVM_INFO @   8336175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*":[{"name":"clkmgr_frequency","qual_name":"0.clkmgr_frequency.37245970125854781167372535321015571271599416623814352417639069087828803251118","seed":37245970125854781167372535321015571271599416623814352417639069087828803251118,"line":80,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  61006794 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  61006794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"1.clkmgr_frequency.108075609897564474856588079357630763354313968381025508386013515094113078361030","seed":108075609897564474856588079357630763354313968381025508386013515094113078361030,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   8572473 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8572473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"1.clkmgr_stress_all.71235159760838009006147267793541770430554616359621141603609555228491062680150","seed":71235159760838009006147267793541770430554616359621141603609555228491062680150,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 187092721 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 187092721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"2.clkmgr_frequency.33518460488982416786477329627213182298429818980999013768427847690809176048173","seed":33518460488982416786477329627213182298429818980999013768427847690809176048173,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5078083 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5078083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"3.clkmgr_frequency.71230865541546104805479468114529415154872787973227187781399723571149293987015","seed":71230865541546104805479468114529415154872787973227187781399723571149293987015,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5484876 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5484876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"3.clkmgr_stress_all.18449094067719099273429415328178060702630600130926782884730850347812979769850","seed":18449094067719099273429415328178060702630600130926782884730850347812979769850,"line":100,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  22236892 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  22236892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"4.clkmgr_frequency.50949763482314130932375362158388054567815389992514877044612064427588762883767","seed":50949763482314130932375362158388054567815389992514877044612064427588762883767,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5349727 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5349727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"5.clkmgr_frequency.9835552331885184636299804180422451597392600071990108183378768291852202621640","seed":9835552331885184636299804180422451597392600071990108183378768291852202621640,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6160810 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6160810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"5.clkmgr_stress_all_with_rand_reset.113041880117668552015673827175611257025891054656835579002577617273135602319106","seed":113041880117668552015673827175611257025891054656835579002577617273135602319106,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  44995685 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  44995685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"5.clkmgr_stress_all.5186158534632626419660244035067159706333286432856454829889256935856350495789","seed":5186158534632626419660244035067159706333286432856454829889256935856350495789,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  50531251 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  50531251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"6.clkmgr_frequency.3492508498392784798563826024371936010042108328619379526704132433863477875930","seed":3492508498392784798563826024371936010042108328619379526704132433863477875930,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5198165 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5198165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"6.clkmgr_stress_all_with_rand_reset.76840224335568295637504344641298054900367117097101774830351551408862859509433","seed":76840224335568295637504344641298054900367117097101774830351551408862859509433,"line":110,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  57170749 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  57170749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"6.clkmgr_stress_all.29578711787983813642571987201527590585027080633851212575477051351486086298786","seed":29578711787983813642571987201527590585027080633851212575477051351486086298786,"line":150,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  51580656 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  51580656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"7.clkmgr_frequency.34157195890647065222670512237510517879047659386073614624941628044474926237794","seed":34157195890647065222670512237510517879047659386073614624941628044474926237794,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  10493815 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  10493815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"7.clkmgr_stress_all_with_rand_reset.80878357432093399308191218477386230951726192153254628247488339547634547547633","seed":80878357432093399308191218477386230951726192153254628247488339547634547547633,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  32803758 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  32803758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"8.clkmgr_frequency.72545844863286532081831874207740943398776314411737557507913627889460895811585","seed":72545844863286532081831874207740943398776314411737557507913627889460895811585,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7102610 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7102610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"8.clkmgr_stress_all_with_rand_reset.93881851380619036024478734419752088841329346045503458688730575001282751560808","seed":93881851380619036024478734419752088841329346045503458688730575001282751560808,"line":122,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 119991064 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 119991064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"9.clkmgr_frequency.104993799855774037836274859514946643680482584668487808501545811074738049115934","seed":104993799855774037836274859514946643680482584668487808501545811074738049115934,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   8040034 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8040034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"9.clkmgr_stress_all.21376629403804214729719609756572271039006454581276061902939947168665524974517","seed":21376629403804214729719609756572271039006454581276061902939947168665524974517,"line":240,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 134561090 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 134561090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"10.clkmgr_frequency.57175458527150131180014190817959546412019434861184973834609545660008434529829","seed":57175458527150131180014190817959546412019434861184973834609545660008434529829,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4368669 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4368669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"10.clkmgr_stress_all_with_rand_reset.32502226646649664184531625261739480017191274942428497445889555617519375616676","seed":32502226646649664184531625261739480017191274942428497445889555617519375616676,"line":91,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  35376905 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  35376905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"11.clkmgr_frequency.51737404933532140888460210086724703030563586345690167893513890622901502006656","seed":51737404933532140888460210086724703030563586345690167893513890622901502006656,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  10730333 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  10730333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"11.clkmgr_stress_all_with_rand_reset.103542076463441052954911485348700098384017538036053659979743057043004509066117","seed":103542076463441052954911485348700098384017538036053659979743057043004509066117,"line":89,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 129186135 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 129186135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"12.clkmgr_frequency.50686041616609096935234651335383736976637644943497848143570463372515059850575","seed":50686041616609096935234651335383736976637644943497848143570463372515059850575,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7820557 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7820557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"13.clkmgr_frequency.4415227427077940520944784124814244605762054806462660082227455238828982626343","seed":4415227427077940520944784124814244605762054806462660082227455238828982626343,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7447854 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7447854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"13.clkmgr_stress_all_with_rand_reset.33551428863788031874369362478629188574570935016952793584203096294565887031864","seed":33551428863788031874369362478629188574570935016952793584203096294565887031864,"line":97,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  93550169 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  93550169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"14.clkmgr_frequency.7719762782956078373002397587383135997475948260867931986201757400835903936417","seed":7719762782956078373002397587383135997475948260867931986201757400835903936417,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  11259946 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  11259946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"14.clkmgr_stress_all_with_rand_reset.18250243400174038132801307094288103380660901218073030373995678618509575050971","seed":18250243400174038132801307094288103380660901218073030373995678618509575050971,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  51386182 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  51386182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"15.clkmgr_frequency.52101522074270130822646456398794496113744847053038207397443865484295077815957","seed":52101522074270130822646456398794496113744847053038207397443865484295077815957,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7205326 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7205326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"16.clkmgr_frequency.56049605674020850263791654157221400473024619199113963930730690199633537082180","seed":56049605674020850263791654157221400473024619199113963930730690199633537082180,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5752051 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5752051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"16.clkmgr_stress_all_with_rand_reset.100403554443594192316491745538496677213722126413174659034612070858109171261164","seed":100403554443594192316491745538496677213722126413174659034612070858109171261164,"line":158,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  31213172 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  31213172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"16.clkmgr_stress_all.41694922782135038515750974029498451234301836253689873829252076765383732375992","seed":41694922782135038515750974029498451234301836253689873829252076765383732375992,"line":164,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  65067203 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  65067203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"17.clkmgr_frequency.63034789155999222945149563009778506072223269824128127984259975070320133615394","seed":63034789155999222945149563009778506072223269824128127984259975070320133615394,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7492111 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7492111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"17.clkmgr_stress_all.76242064958538925849433517670802188253877152984520044216793497157083150723311","seed":76242064958538925849433517670802188253877152984520044216793497157083150723311,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  11116450 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  11116450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"18.clkmgr_frequency.112010720607193050341603089472789616966117838997782379072550317911380983356634","seed":112010720607193050341603089472789616966117838997782379072550317911380983356634,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7375576 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7375576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"18.clkmgr_stress_all_with_rand_reset.89485415868444641395577931817353393217050211611457322452658976042608305047297","seed":89485415868444641395577931817353393217050211611457322452658976042608305047297,"line":80,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   8809824 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   8809824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"19.clkmgr_frequency.46824961298444029520917828836415000588699533008623470533984506274659092150417","seed":46824961298444029520917828836415000588699533008623470533984506274659092150417,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4171775 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4171775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"19.clkmgr_stress_all.110219323917750581431131057509111696336641780675878931048864032475383631851375","seed":110219323917750581431131057509111696336641780675878931048864032475383631851375,"line":136,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 183493650 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 183493650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"20.clkmgr_frequency.23669709866271658189872029425491819121135202685219254307926019157733348907456","seed":23669709866271658189872029425491819121135202685219254307926019157733348907456,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  12462303 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  12462303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"21.clkmgr_frequency.57358399550108465657801268242730377750575023188803707771615253092253553477099","seed":57358399550108465657801268242730377750575023188803707771615253092253553477099,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7019416 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7019416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"21.clkmgr_stress_all.29643065872955990469656856572403744674413306542849465981032862669650921228071","seed":29643065872955990469656856572403744674413306542849465981032862669650921228071,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  12591346 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  12591346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"22.clkmgr_frequency.20978130821783073441764649002261806074622222513698722562840603522645916150339","seed":20978130821783073441764649002261806074622222513698722562840603522645916150339,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6817771 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6817771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"22.clkmgr_stress_all_with_rand_reset.111809820072439178714894948545957044828491496882300130263236932882171517338420","seed":111809820072439178714894948545957044828491496882300130263236932882171517338420,"line":101,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  83273178 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  83273178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"22.clkmgr_stress_all.99294080243364625211001588202398773673257579175891655832892182088897787062852","seed":99294080243364625211001588202398773673257579175891655832892182088897787062852,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  79436430 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  79436430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"23.clkmgr_frequency.59239945855822086689524755310195561334947354356763521265836635048999394260525","seed":59239945855822086689524755310195561334947354356763521265836635048999394260525,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   9084381 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   9084381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"24.clkmgr_frequency.46804886092050603778819285802414661808838234911036670389023828606557422299986","seed":46804886092050603778819285802414661808838234911036670389023828606557422299986,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   8298377 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   8298377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"24.clkmgr_stress_all_with_rand_reset.9348465589575621081303005085330535598621923898296054800828819748359439622396","seed":9348465589575621081303005085330535598621923898296054800828819748359439622396,"line":184,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 118409743 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 118409743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"24.clkmgr_stress_all.63024605920094721899018884543930267461747332643690205993191092618728433632383","seed":63024605920094721899018884543930267461747332643690205993191092618728433632383,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  62696991 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  62696991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"25.clkmgr_frequency.6361914185486516957923332932000438684714037480390767891659904737458180552960","seed":6361914185486516957923332932000438684714037480390767891659904737458180552960,"line":80,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  36202384 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  36202384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"25.clkmgr_stress_all.6843156347144340495631017646865679015578832360141543244128491999406714300389","seed":6843156347144340495631017646865679015578832360141543244128491999406714300389,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  32272705 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  32272705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"26.clkmgr_frequency.38456786103680890586890807741542269632258023332992699788368446185851570587562","seed":38456786103680890586890807741542269632258023332992699788368446185851570587562,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  21297434 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  21297434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"26.clkmgr_stress_all_with_rand_reset.22975035182283589008896659080508248728338374384764335265591749034827369274265","seed":22975035182283589008896659080508248728338374384764335265591749034827369274265,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  13367831 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  13367831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"27.clkmgr_frequency.25705104012850717857992406712696213724932015115306876866561793634555992151481","seed":25705104012850717857992406712696213724932015115306876866561793634555992151481,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6941861 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6941861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"27.clkmgr_stress_all_with_rand_reset.27896800202936610303242438213383415619728315286378783533571983640224745690351","seed":27896800202936610303242438213383415619728315286378783533571983640224745690351,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  57049977 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  57049977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"27.clkmgr_stress_all.53953526308283167938867772319428372706536763747245271434909173464021002054971","seed":53953526308283167938867772319428372706536763747245271434909173464021002054971,"line":240,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 268028091 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 268028091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"28.clkmgr_frequency.102575133557822495980388481998654382354911396263416265606526823894437831689404","seed":102575133557822495980388481998654382354911396263416265606526823894437831689404,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/28.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  20286367 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  20286367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"29.clkmgr_frequency.106731102124248197448616569771178310690134418672501810697560327543378116339337","seed":106731102124248197448616569771178310690134418672501810697560327543378116339337,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5988288 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5988288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"29.clkmgr_stress_all_with_rand_reset.97281083013581030727326429726321218762529927415059142414079841687500033390668","seed":97281083013581030727326429726321218762529927415059142414079841687500033390668,"line":117,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  90932974 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  90932974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"29.clkmgr_stress_all.77866544967678673732098578215899143078933779981728615320690454014930772735194","seed":77866544967678673732098578215899143078933779981728615320690454014930772735194,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  14283548 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  14283548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"30.clkmgr_frequency.88648557907799462132853597072238800040390750437909748398507847319884525829112","seed":88648557907799462132853597072238800040390750437909748398507847319884525829112,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   3971292 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3971292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"31.clkmgr_frequency.92836080798957199225577776290901447509168769100120115804979550295815494010305","seed":92836080798957199225577776290901447509168769100120115804979550295815494010305,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5640756 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5640756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"32.clkmgr_frequency.101072371848710270676012433674778935825311585561965551727251074281168135307926","seed":101072371848710270676012433674778935825311585561965551727251074281168135307926,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  16649752 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  16649752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"32.clkmgr_stress_all_with_rand_reset.69867735176777618983861232835404574400834155574216778189967564569592513731682","seed":69867735176777618983861232835404574400834155574216778189967564569592513731682,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   5467080 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5467080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"32.clkmgr_stress_all.44822484607086849133597459609827123617696117152619510499169054963518605230459","seed":44822484607086849133597459609827123617696117152619510499169054963518605230459,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   6711070 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6711070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"33.clkmgr_frequency.12865961209928582145848028974511479496782529972594927459219719940030420346990","seed":12865961209928582145848028974511479496782529972594927459219719940030420346990,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6356261 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6356261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"33.clkmgr_stress_all_with_rand_reset.94540630160811592878789955155530969447098007047502317068614494913137165425825","seed":94540630160811592878789955155530969447098007047502317068614494913137165425825,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  14677574 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  14677574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"34.clkmgr_stress_all_with_rand_reset.46072710824360628335423470854067907153871195072251022700252431573192267621668","seed":46072710824360628335423470854067907153871195072251022700252431573192267621668,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  52961952 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  52961952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"35.clkmgr_frequency.56527409038869375386364551764201185045945501719475537333386400751358988935680","seed":56527409038869375386364551764201185045945501719475537333386400751358988935680,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4352211 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4352211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"35.clkmgr_stress_all_with_rand_reset.84314241250929761711583567380370445296932791311760907848773708482149694760528","seed":84314241250929761711583567380370445296932791311760907848773708482149694760528,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  15929630 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  15929630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"36.clkmgr_frequency.47951375758190860122084598161559032599290768335392614925395406652504487152757","seed":47951375758190860122084598161559032599290768335392614925395406652504487152757,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4847449 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4847449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"36.clkmgr_stress_all_with_rand_reset.282456590299978718936169660211620976374324944887576830236488748506824888389","seed":282456590299978718936169660211620976374324944887576830236488748506824888389,"line":113,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 127296185 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 127296185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"36.clkmgr_stress_all.57548413669148875410191445375963564290921992474468769354142771552410783174783","seed":57548413669148875410191445375963564290921992474468769354142771552410783174783,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  24347865 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  24347865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"37.clkmgr_frequency.28523547261704921295391102845058189315911520940266181834161941678262131177085","seed":28523547261704921295391102845058189315911520940266181834161941678262131177085,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4898518 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4898518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"37.clkmgr_stress_all.15345132099127238727295553698222847964135506323435217571823582263392777640392","seed":15345132099127238727295553698222847964135506323435217571823582263392777640392,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  46291731 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  46291731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"38.clkmgr_frequency.110987708696634306631311906816736645500618188558712800896770076364465665172781","seed":110987708696634306631311906816736645500618188558712800896770076364465665172781,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5455105 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5455105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"38.clkmgr_stress_all_with_rand_reset.20067210589161650549103757562813698201146040600721823252541603927995379583732","seed":20067210589161650549103757562813698201146040600721823252541603927995379583732,"line":157,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  30823851 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  30823851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"39.clkmgr_frequency.94435397931627665478488451689404789568871026556823506532301036285598656762990","seed":94435397931627665478488451689404789568871026556823506532301036285598656762990,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  45099894 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  45099894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"40.clkmgr_frequency.17883865085881520534325759797248633003554380384268867570794114173434716590946","seed":17883865085881520534325759797248633003554380384268867570794114173434716590946,"line":80,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  26277840 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  26277840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"40.clkmgr_stress_all_with_rand_reset.10219724179148618183396490581187846703742627750055427942028168950888235266922","seed":10219724179148618183396490581187846703742627750055427942028168950888235266922,"line":110,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  64861352 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  64861352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"40.clkmgr_stress_all.101725920794077222428758581159394214986506854705491134018178518276257301369596","seed":101725920794077222428758581159394214986506854705491134018178518276257301369596,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   5556624 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5556624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"41.clkmgr_frequency.29138004152601198594842588081012472855026362464260981585103847841247661374736","seed":29138004152601198594842588081012472855026362464260981585103847841247661374736,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   9181118 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   9181118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"41.clkmgr_stress_all_with_rand_reset.36617770022086931085021017158848288435580088708643235938676579199587299786899","seed":36617770022086931085021017158848288435580088708643235938676579199587299786899,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  15836644 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  15836644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"42.clkmgr_frequency.12516044530243672625961014596447900949012307285054520314260844559279131409497","seed":12516044530243672625961014596447900949012307285054520314260844559279131409497,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  16920459 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  16920459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"43.clkmgr_frequency.104862652852320458074984959869487822766207444407223500204065251118631177652088","seed":104862652852320458074984959869487822766207444407223500204065251118631177652088,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   9341350 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   9341350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"44.clkmgr_frequency.47481642059539844559733166301609747538413492075578301744955677216913177960484","seed":47481642059539844559733166301609747538413492075578301744955677216913177960484,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   9553604 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   9553604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"44.clkmgr_stress_all.46186723555108855715747140247422318809601834514365888351520045790572099582784","seed":46186723555108855715747140247422318809601834514365888351520045790572099582784,"line":184,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 201074975 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 201074975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"45.clkmgr_frequency.64187616766824716701351527715912480610151752102693295267265038017963114490545","seed":64187616766824716701351527715912480610151752102693295267265038017963114490545,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4956525 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4956525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"45.clkmgr_stress_all_with_rand_reset.97769344012588981238649994707993351115595027183095836190586231310031005361311","seed":97769344012588981238649994707993351115595027183095836190586231310031005361311,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  30699126 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  30699126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"45.clkmgr_stress_all.74521288640069576870386627861796500432271282404868395076471105410777138728332","seed":74521288640069576870386627861796500432271282404868395076471105410777138728332,"line":100,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  21620146 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  21620146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"46.clkmgr_frequency.97088692979454468587796479336230035256160854189574085028976661963516269285052","seed":97088692979454468587796479336230035256160854189574085028976661963516269285052,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  17794542 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  17794542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"47.clkmgr_frequency.49489609575626960394747376835279656690734041532849272406331482477342725382022","seed":49489609575626960394747376835279656690734041532849272406331482477342725382022,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  12567750 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  12567750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"48.clkmgr_frequency.82294292192727581257664278803362271403554840709629866557364341082976530372306","seed":82294292192727581257664278803362271403554840709629866557364341082976530372306,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  12274141 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  12274141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"48.clkmgr_stress_all.114209907745626702022553660173064727445843625657176972498026313802517832082109","seed":114209907745626702022553660173064727445843625657176972498026313802517832082109,"line":147,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 127460310 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 127460310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"49.clkmgr_frequency.41064964705767520100509016843469036888574831206451851727370162681858153413001","seed":41064964705767520100509016843469036888574831206451851727370162681858153413001,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5706958 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5706958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*":[{"name":"clkmgr_frequency_timeout","qual_name":"0.clkmgr_frequency_timeout.30975201651423421051363208638847051802311569792572131425913699929141635906656","seed":30975201651423421051363208638847051802311569792572131425913699929141635906656,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   1756931 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   1756931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"0.clkmgr_stress_all_with_rand_reset.57734714871140740901927377259991692049898471478784625847336203045608619743499","seed":57734714871140740901927377259991692049898471478784625847336203045608619743499,"line":119,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  22452471 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  22452471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"1.clkmgr_frequency_timeout.110197482303796969619275142635969367848620016050450730584064381543437788490949","seed":110197482303796969619275142635969367848620016050450730584064381543437788490949,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5317083 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5317083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"1.clkmgr_stress_all_with_rand_reset.17117931995868255766970551287193212434896111445905212927416380529017454025164","seed":17117931995868255766970551287193212434896111445905212927416380529017454025164,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  12875720 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  12875720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"2.clkmgr_frequency_timeout.11732309990203532287612787143935742902362678267438264221666783221435058363507","seed":11732309990203532287612787143935742902362678267438264221666783221435058363507,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4422904 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4422904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"2.clkmgr_stress_all_with_rand_reset.70259145991935991318853508263584877050301711291521168607885433175347365942741","seed":70259145991935991318853508263584877050301711291521168607885433175347365942741,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  10187231 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  10187231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"2.clkmgr_stress_all.3084736940073720216724428730504341687093190816455407181190504076976985987290","seed":3084736940073720216724428730504341687093190816455407181190504076976985987290,"line":118,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  20943331 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  20943331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"3.clkmgr_frequency_timeout.24837560688810798096652196592597636657818120075605957116896112981360209575879","seed":24837560688810798096652196592597636657818120075605957116896112981360209575879,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2516282 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2516282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"3.clkmgr_stress_all_with_rand_reset.53053562345693594095830154627203083198311748954748569203098473866701001181482","seed":53053562345693594095830154627203083198311748954748569203098473866701001181482,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   5447410 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5447410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"4.clkmgr_frequency_timeout.93073365864511772829581782823776597579304037752683884817325510024010841543632","seed":93073365864511772829581782823776597579304037752683884817325510024010841543632,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   8281057 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8281057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"4.clkmgr_stress_all_with_rand_reset.107394741867688316951930415905224487081982949571528463093870386883226731004129","seed":107394741867688316951930415905224487081982949571528463093870386883226731004129,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   4816615 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4816615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"4.clkmgr_stress_all.102556664620100064821083886839733091408624486399079872050839160825725775878537","seed":102556664620100064821083886839733091408624486399079872050839160825725775878537,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   6387423 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6387423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"5.clkmgr_frequency_timeout.58743058000439463274505013377321458506945206359665842347283433880336598417463","seed":58743058000439463274505013377321458506945206359665842347283433880336598417463,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3805714 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3805714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"6.clkmgr_frequency_timeout.64168300831955734329188851058752011318976766310544147222430772546963713366660","seed":64168300831955734329188851058752011318976766310544147222430772546963713366660,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3494114 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3494114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"7.clkmgr_frequency_timeout.79721646047998295446719112180809659807989118235494353483932028670831262010744","seed":79721646047998295446719112180809659807989118235494353483932028670831262010744,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4679928 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4679928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"7.clkmgr_stress_all.16401775819528922379717061917337239861318014086322320199254428712402216745341","seed":16401775819528922379717061917337239861318014086322320199254428712402216745341,"line":230,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 577851877 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 577851877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"8.clkmgr_frequency_timeout.98466212499182217919229701873414034151374609920709154735368882318294964343162","seed":98466212499182217919229701873414034151374609920709154735368882318294964343162,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3290430 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3290430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"8.clkmgr_stress_all.101027408400102303248160853032113752994091012450329443855184616561090329382225","seed":101027408400102303248160853032113752994091012450329443855184616561090329382225,"line":129,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  95599110 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  95599110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"9.clkmgr_frequency_timeout.85190020985360388199596811212803492495016376104103807541043159333276698563614","seed":85190020985360388199596811212803492495016376104103807541043159333276698563614,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3267285 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3267285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"9.clkmgr_stress_all_with_rand_reset.38856508546226418350093506502346824771855583671835641046636415496231213853521","seed":38856508546226418350093506502346824771855583671835641046636415496231213853521,"line":143,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 441371571 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 441371571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"10.clkmgr_frequency_timeout.41289962647075032721581128604543276125211373553962372455145217551192100988515","seed":41289962647075032721581128604543276125211373553962372455145217551192100988515,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5415350 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5415350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"10.clkmgr_stress_all.15635489392550208608948362811820837991759892917242728584039261685715747317814","seed":15635489392550208608948362811820837991759892917242728584039261685715747317814,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  69315056 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  69315056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"11.clkmgr_stress_all.110978507786728398069325116908143714546361202912587665574960610725599589549748","seed":110978507786728398069325116908143714546361202912587665574960610725599589549748,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 114845000 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 114845000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"12.clkmgr_frequency_timeout.87416094489595395530329007326964134681704895379588246956839758694336740887568","seed":87416094489595395530329007326964134681704895379588246956839758694336740887568,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   1868139 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   1868139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"12.clkmgr_stress_all_with_rand_reset.99085284369415026240962973470973674610713444861504228164706870473977603239080","seed":99085284369415026240962973470973674610713444861504228164706870473977603239080,"line":103,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 234746241 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 234746241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"12.clkmgr_stress_all.115462526835576421560222577192568102742257021254688396729871012492953476399347","seed":115462526835576421560222577192568102742257021254688396729871012492953476399347,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   5347878 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5347878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"13.clkmgr_frequency_timeout.7385182732033187276628287722287519784796880599957626610731614604631866561646","seed":7385182732033187276628287722287519784796880599957626610731614604631866561646,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3005704 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3005704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"13.clkmgr_stress_all.114152929027054822202742874908623129971873728126741626848682876885627787600551","seed":114152929027054822202742874908623129971873728126741626848682876885627787600551,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   1430614 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   1430614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"14.clkmgr_frequency_timeout.5630551927020426781630729084451460387839878362810742104204441659715307334012","seed":5630551927020426781630729084451460387839878362810742104204441659715307334012,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3662882 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3662882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"14.clkmgr_stress_all.75726604917355693286679022062304721009598614866104015880063780661749141668280","seed":75726604917355693286679022062304721009598614866104015880063780661749141668280,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  20969986 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  20969986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"15.clkmgr_frequency_timeout.50597420714193346390288822035267175898769388422230319645214153153017137815218","seed":50597420714193346390288822035267175898769388422230319645214153153017137815218,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5694525 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5694525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"15.clkmgr_stress_all_with_rand_reset.52112410415384703549664879877268978300374463649053909644155490810448363016516","seed":52112410415384703549664879877268978300374463649053909644155490810448363016516,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   9099634 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   9099634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"15.clkmgr_stress_all.103806609736326216064793218892196075338312954150675133994180117407378847202537","seed":103806609736326216064793218892196075338312954150675133994180117407378847202537,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   6039889 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6039889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"16.clkmgr_frequency_timeout.9548654362958860000557579276902056149184450655360767216562783854089274255918","seed":9548654362958860000557579276902056149184450655360767216562783854089274255918,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @  16138412 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  16138412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"17.clkmgr_frequency_timeout.74737352381382848747213731544356750530869115759175522228344508769677956316181","seed":74737352381382848747213731544356750530869115759175522228344508769677956316181,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3718874 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3718874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"17.clkmgr_stress_all_with_rand_reset.6891333807912863565139899949616755340300442026972622869658492505595605018371","seed":6891333807912863565139899949616755340300442026972622869658492505595605018371,"line":159,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 110640070 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 110640070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"18.clkmgr_frequency_timeout.3152809372736184476882846818644542029777290427015517652877831619911960816778","seed":3152809372736184476882846818644542029777290427015517652877831619911960816778,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   8217405 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8217405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"18.clkmgr_stress_all.5823687485769040781245241034015299059632776731131055850054926730045334914398","seed":5823687485769040781245241034015299059632776731131055850054926730045334914398,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  20690763 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  20690763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"19.clkmgr_frequency_timeout.27186581634600508203034098920826726089778949293429655688548266957932738409356","seed":27186581634600508203034098920826726089778949293429655688548266957932738409356,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3378904 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3378904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"19.clkmgr_stress_all_with_rand_reset.37176196697828221424358142072869021712392972930804560566198417911263450093319","seed":37176196697828221424358142072869021712392972930804560566198417911263450093319,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   6268399 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6268399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"20.clkmgr_frequency_timeout.12473541189852748185009430585068758177700305307783726492683628136492257198961","seed":12473541189852748185009430585068758177700305307783726492683628136492257198961,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   8420600 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   8420600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"20.clkmgr_stress_all_with_rand_reset.80079575213027581602204144986056244440426022739438417020346235825427429522611","seed":80079575213027581602204144986056244440426022739438417020346235825427429522611,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   9865654 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   9865654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"20.clkmgr_stress_all.25672743283969255923212098188542875417990984329562860408031088768344646594804","seed":25672743283969255923212098188542875417990984329562860408031088768344646594804,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   2763670 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2763670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"21.clkmgr_frequency_timeout.30770473224235740399402166157626799251150049268147581621094520662445996666211","seed":30770473224235740399402166157626799251150049268147581621094520662445996666211,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2400289 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2400289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"21.clkmgr_stress_all_with_rand_reset.59526581303280468838923989963692855082078130346660393493254540870413541637091","seed":59526581303280468838923989963692855082078130346660393493254540870413541637091,"line":93,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  36541672 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  36541672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"22.clkmgr_frequency_timeout.89251267682354320426236102354689912205524773969616569213943715531756246676753","seed":89251267682354320426236102354689912205524773969616569213943715531756246676753,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3986343 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3986343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"23.clkmgr_frequency_timeout.92111959763895556814760601551523249998493841837927066192571202614035703793129","seed":92111959763895556814760601551523249998493841837927066192571202614035703793129,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5038928 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5038928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"23.clkmgr_stress_all_with_rand_reset.103561895817958616934104791399229703288842204297503209606572165082909865281678","seed":103561895817958616934104791399229703288842204297503209606572165082909865281678,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  15739224 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  15739224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"23.clkmgr_stress_all.22674910068600977259795907994477405083546109404312874192151531767653036233488","seed":22674910068600977259795907994477405083546109404312874192151531767653036233488,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   3626652 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3626652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"24.clkmgr_frequency_timeout.109100085075888728319546722123983328578990162106981333989405835898172481429115","seed":109100085075888728319546722123983328578990162106981333989405835898172481429115,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2481890 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2481890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"25.clkmgr_frequency_timeout.2148530993798813199305271993084196488450338256948430114526810193776345787007","seed":2148530993798813199305271993084196488450338256948430114526810193776345787007,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3022966 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3022966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"25.clkmgr_stress_all_with_rand_reset.88062892314264864563398980146980507985468573368028953364209971761242823851624","seed":88062892314264864563398980146980507985468573368028953364209971761242823851624,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   4012649 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4012649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"26.clkmgr_frequency_timeout.33407229940924494918573928472140597121646839351688457383209065473652599653351","seed":33407229940924494918573928472140597121646839351688457383209065473652599653351,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5216735 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5216735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"26.clkmgr_stress_all.56161051460558090061447867514202038488420551675818052417478913904426041541201","seed":56161051460558090061447867514202038488420551675818052417478913904426041541201,"line":130,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  80356867 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  80356867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"27.clkmgr_frequency_timeout.21388636883312996645032492436084114062598684787467364998195746231848079198314","seed":21388636883312996645032492436084114062598684787467364998195746231848079198314,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @  14337876 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  14337876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"28.clkmgr_frequency_timeout.19696992650317135725094175832856762876890489791005610794508261001949186434517","seed":19696992650317135725094175832856762876890489791005610794508261001949186434517,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/28.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4377072 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4377072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"28.clkmgr_stress_all_with_rand_reset.94721087118622820619300393581959108202366121782483437173832735215417220012966","seed":94721087118622820619300393581959108202366121782483437173832735215417220012966,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/28.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 101157176 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 101157176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"28.clkmgr_stress_all.110451358988852015615005266081674545156337005156162036166220736446643707654580","seed":110451358988852015615005266081674545156337005156162036166220736446643707654580,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/28.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   4502944 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4502944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"29.clkmgr_frequency_timeout.88643533396830411686418266161096949241709482299975011392664443403484610931222","seed":88643533396830411686418266161096949241709482299975011392664443403484610931222,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5115293 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5115293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"30.clkmgr_frequency_timeout.50781327612755328034365088228103231623489055761924888752306943344598111633955","seed":50781327612755328034365088228103231623489055761924888752306943344598111633955,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5856101 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5856101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"30.clkmgr_stress_all_with_rand_reset.11051110902645111172088354351225632458252198678904804161960733247474244614468","seed":11051110902645111172088354351225632458252198678904804161960733247474244614468,"line":113,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 326826791 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 326826791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"31.clkmgr_frequency_timeout.113280243658514806039403500149125010553237528048983269589289206105719780731155","seed":113280243658514806039403500149125010553237528048983269589289206105719780731155,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3400590 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3400590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"31.clkmgr_stress_all_with_rand_reset.87195814616339765294653396749799844487598777532456185894845316772437156704166","seed":87195814616339765294653396749799844487598777532456185894845316772437156704166,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  16056808 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  16056808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"32.clkmgr_frequency_timeout.26770949320641494176930271907129475450558864242656570251341303180511321879772","seed":26770949320641494176930271907129475450558864242656570251341303180511321879772,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2627935 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2627935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"33.clkmgr_frequency_timeout.55623788209165119763925022307505821108679441255062541229806519772842224878557","seed":55623788209165119763925022307505821108679441255062541229806519772842224878557,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3643471 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3643471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"33.clkmgr_stress_all.115105147765339934059257840274928812566438691729058875381366299080053928056182","seed":115105147765339934059257840274928812566438691729058875381366299080053928056182,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   5207476 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5207476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"34.clkmgr_frequency_timeout.45909689121010942717328897782054908567032454826221953560354734360051116587707","seed":45909689121010942717328897782054908567032454826221953560354734360051116587707,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @  34650036 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  34650036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"34.clkmgr_stress_all.56734925688907276448668197490473966893716703217618491461649516911097745792133","seed":56734925688907276448668197490473966893716703217618491461649516911097745792133,"line":122,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  82200468 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  82200468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"35.clkmgr_frequency_timeout.9258379268044915160220389177939839399279221397713215654090557990829041874699","seed":9258379268044915160220389177939839399279221397713215654090557990829041874699,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3998682 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3998682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"35.clkmgr_stress_all.3939385387155368239320647297747694062675120136200719402884371217114007819873","seed":3939385387155368239320647297747694062675120136200719402884371217114007819873,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   8150157 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   8150157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"36.clkmgr_frequency_timeout.22553067677165909395689140402553646278809040941259019776678519533370974992008","seed":22553067677165909395689140402553646278809040941259019776678519533370974992008,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   7674243 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7674243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"37.clkmgr_frequency_timeout.73289209935563472164728968709482291788439008831332089665460354160777395175921","seed":73289209935563472164728968709482291788439008831332089665460354160777395175921,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6066806 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6066806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"37.clkmgr_stress_all_with_rand_reset.29517575564166916440391809160498511354912438144342019585452205041342341518227","seed":29517575564166916440391809160498511354912438144342019585452205041342341518227,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   9974069 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   9974069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"38.clkmgr_frequency_timeout.25764791972891602626466959573425543628534755656517275237902957281934387359023","seed":25764791972891602626466959573425543628534755656517275237902957281934387359023,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2617328 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2617328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"39.clkmgr_frequency_timeout.33315291829711491653849016865786142956234227745245592530453414185622223276925","seed":33315291829711491653849016865786142956234227745245592530453414185622223276925,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   7203936 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7203936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"39.clkmgr_stress_all_with_rand_reset.62180568850702326638428251142293353252538994343846598222919773064017414620216","seed":62180568850702326638428251142293353252538994343846598222919773064017414620216,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   3830638 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3830638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"39.clkmgr_stress_all.108114907997533834183278040202680444827289110842654094231243492628063526706922","seed":108114907997533834183278040202680444827289110842654094231243492628063526706922,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   3871371 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3871371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"40.clkmgr_frequency_timeout.106298913468865071363774130000385434484389751061788585806764116186193139708984","seed":106298913468865071363774130000385434484389751061788585806764116186193139708984,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5854216 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5854216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"41.clkmgr_frequency_timeout.63108514278894409373341646369586472907290248992342147598147743288481459966183","seed":63108514278894409373341646369586472907290248992342147598147743288481459966183,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2931018 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2931018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"41.clkmgr_stress_all.93540561779398911088201795229225315957915767371582575764687466578656915029567","seed":93540561779398911088201795229225315957915767371582575764687466578656915029567,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   5626407 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5626407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"42.clkmgr_frequency_timeout.20594410079752810613554689793355792065153308806269872154932363907701583887173","seed":20594410079752810613554689793355792065153308806269872154932363907701583887173,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @  17480467 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  17480467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"42.clkmgr_stress_all_with_rand_reset.41637386059082410845903456598301979483859513381018279763160301866465737860726","seed":41637386059082410845903456598301979483859513381018279763160301866465737860726,"line":127,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 156267642 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 156267642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"42.clkmgr_stress_all.39262371274590296011852080075516551189390423209017668281178544179058433253581","seed":39262371274590296011852080075516551189390423209017668281178544179058433253581,"line":97,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 249115852 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 249115852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"43.clkmgr_frequency_timeout.76384610265233120685054165173153021414034364859678518490971357802157287367412","seed":76384610265233120685054165173153021414034364859678518490971357802157287367412,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @  12638375 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  12638375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"43.clkmgr_stress_all_with_rand_reset.33225132976241174293160956403378159199393723819163154664393864735398320823587","seed":33225132976241174293160956403378159199393723819163154664393864735398320823587,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 119114990 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 119114990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"43.clkmgr_stress_all.17409888106520811680013282943201468223762640822374740801398118918118323024815","seed":17409888106520811680013282943201468223762640822374740801398118918118323024815,"line":102,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  22884347 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  22884347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"44.clkmgr_frequency_timeout.65669849620128586700469098462311073557330981294420730929862113607652323950142","seed":65669849620128586700469098462311073557330981294420730929862113607652323950142,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2290788 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2290788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"44.clkmgr_stress_all_with_rand_reset.71051815964161163877288609560956394573151233218546122542497661472245578070925","seed":71051815964161163877288609560956394573151233218546122542497661472245578070925,"line":165,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3208113020 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 3208113020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"45.clkmgr_frequency_timeout.96209911433417790956454169221856344461676267465616222604994487069246870213937","seed":96209911433417790956454169221856344461676267465616222604994487069246870213937,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2026230 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2026230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"46.clkmgr_frequency_timeout.82961045203804548585132854191648725342161007452396096392511454284379690796018","seed":82961045203804548585132854191648725342161007452396096392511454284379690796018,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3253517 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3253517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"46.clkmgr_stress_all_with_rand_reset.96383822358664290510995395107455609424719940740707665620712192402454314970553","seed":96383822358664290510995395107455609424719940740707665620712192402454314970553,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  40734679 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  40734679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"47.clkmgr_frequency_timeout.97273531136024748954996703109032677579901850552004599830174436942379863148066","seed":97273531136024748954996703109032677579901850552004599830174436942379863148066,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3591654 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3591654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"47.clkmgr_stress_all_with_rand_reset.70942693875228689764154962650850902652961383269439775892814525129181494101153","seed":70942693875228689764154962650850902652961383269439775892814525129181494101153,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   3685372 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3685372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"47.clkmgr_stress_all.48431731396537909716493040608287873809129490531301989537994783031349688339556","seed":48431731396537909716493040608287873809129490531301989537994783031349688339556,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   5042886 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5042886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"48.clkmgr_frequency_timeout.89535699440869363424605412331496172622932642692831250312438648196051056242345","seed":89535699440869363424605412331496172622932642692831250312438648196051056242345,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3331454 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3331454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"48.clkmgr_stress_all_with_rand_reset.69983889486445195389875238820881530823413784270044457010150867461097097275872","seed":69983889486445195389875238820881530823413784270044457010150867461097097275872,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   3535426 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3535426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"49.clkmgr_frequency_timeout.37021779303165492480547373497766722290475125645670444721052729968451957228220","seed":37021779303165492480547373497766722290475125645670444721052729968451957228220,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3058334 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3058334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"49.clkmgr_stress_all_with_rand_reset.4707879662325348724518711076217615298970433964913254748688667000610342146994","seed":4707879662325348724518711076217615298970433964913254748688667000610342146994,"line":204,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  65883457 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  65883457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"49.clkmgr_stress_all.81248371919585524051480238149567544883922770307070642376406096137193873621137","seed":81248371919585524051480238149567544883922770307070642376406096137193873621137,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 218601134 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 218601134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en":[{"name":"clkmgr_regwen","qual_name":"0.clkmgr_regwen.41798132301501666433517418524003965128187552220411050023328225881420200742618","seed":41798132301501666433517418524003965128187552220411050023328225881420200742618,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6181876 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   6181876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"2.clkmgr_regwen.112244208378503089469156922729877873431843377399384142300866094273035742251288","seed":112244208378503089469156922729877873431843377399384142300866094273035742251288,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  12132465 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (7 [0x7] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @  12132465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"3.clkmgr_regwen.31886175734887948047989243865136190442459793569239319288808972936107592423058","seed":31886175734887948047989243865136190442459793569239319288808972936107592423058,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2971105 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (8 [0x8] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2971105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"5.clkmgr_regwen.2431612690434536722337428417732290947412815776666216066509556681707942198525","seed":2431612690434536722337428417732290947412815776666216066509556681707942198525,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2188746 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2188746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"6.clkmgr_regwen.72399189785455116126295726807973800623775798448525930481603765985859963283921","seed":72399189785455116126295726807973800623775798448525930481603765985859963283921,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  14391130 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @  14391130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"7.clkmgr_regwen.79228663541112923202512802106117015710448458784074500957420059561126931084755","seed":79228663541112923202512802106117015710448458784074500957420059561126931084755,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4554443 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 13 [0xd]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   4554443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"10.clkmgr_regwen.100565363845878832978951850730808342720594210881164303963127132197759448460499","seed":100565363845878832978951850730808342720594210881164303963127132197759448460499,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4036982 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   4036982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"11.clkmgr_regwen.14737533917698191290069812686702053930902009263422400041738907366103868599415","seed":14737533917698191290069812686702053930902009263422400041738907366103868599415,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2473889 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2473889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"14.clkmgr_regwen.46835939580974452051799722138120233295472512759533959188250627915970398139845","seed":46835939580974452051799722138120233295472512759533959188250627915970398139845,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2636240 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 12 [0xc]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2636240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"15.clkmgr_regwen.85754143492725400108059753358653051038916907573580373696383792509138648909964","seed":85754143492725400108059753358653051038916907573580373696383792509138648909964,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5455732 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   5455732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"16.clkmgr_regwen.90095071878164493798106777105548844592579814066053569412343122924718426538920","seed":90095071878164493798106777105548844592579814066053569412343122924718426538920,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5709955 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 15 [0xf]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   5709955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"18.clkmgr_regwen.96441164542614201434745873305988995776711688327811446881832062080894166393715","seed":96441164542614201434745873305988995776711688327811446881832062080894166393715,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5126458 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   5126458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"19.clkmgr_regwen.77544961106959812992896147591099530139602319032117439324368972790197287155407","seed":77544961106959812992896147591099530139602319032117439324368972790197287155407,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  35644806 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 13 [0xd]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @  35644806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"20.clkmgr_regwen.14426794422225605036061875963925143496621240516391711977379275335466271613356","seed":14426794422225605036061875963925143496621240516391711977379275335466271613356,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4947883 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 4 [0x4]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   4947883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"21.clkmgr_regwen.27631998517824188857683388701112628565064785009744608589823137977510847970646","seed":27631998517824188857683388701112628565064785009744608589823137977510847970646,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2046265 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 4 [0x4]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2046265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"23.clkmgr_regwen.40001419206823970085903534021756206928198447013599906660125151598708827750955","seed":40001419206823970085903534021756206928198447013599906660125151598708827750955,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6241023 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 3 [0x3]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   6241023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"25.clkmgr_regwen.88965037892397054966788408486843847877792919135305939482295963797879901276669","seed":88965037892397054966788408486843847877792919135305939482295963797879901276669,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4145387 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (14 [0xe] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   4145387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"28.clkmgr_regwen.57666484087509383204831133676307974912582605421706877212722135690693447425690","seed":57666484087509383204831133676307974912582605421706877212722135690693447425690,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/28.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2453526 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 0 [0x0]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2453526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"30.clkmgr_regwen.8419831867062192848513694333741651028262500440659406219461551216223593104218","seed":8419831867062192848513694333741651028262500440659406219461551216223593104218,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3417105 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 2 [0x2]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3417105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"31.clkmgr_regwen.43673958720604526279162584609140468761034781812524097765769772781548282567142","seed":43673958720604526279162584609140468761034781812524097765769772781548282567142,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   7021961 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 1 [0x1]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   7021961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"36.clkmgr_regwen.100637977730453265898599664255987756834654872976221409006585123668395555762915","seed":100637977730453265898599664255987756834654872976221409006585123668395555762915,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3379577 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 1 [0x1]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3379577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"37.clkmgr_regwen.73597363758495674356853163931420033253696403880166919072630982018122933510414","seed":73597363758495674356853163931420033253696403880166919072630982018122933510414,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2847284 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 8 [0x8]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2847284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"38.clkmgr_regwen.41519524498033752300946907638827889062286961910451927124326789451305552707737","seed":41519524498033752300946907638827889062286961910451927124326789451305552707737,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3610652 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 0 [0x0]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3610652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"40.clkmgr_regwen.18618311036974820641251248278200067247649109099123360229542859604440983262425","seed":18618311036974820641251248278200067247649109099123360229542859604440983262425,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2842610 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2842610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"42.clkmgr_regwen.74365517183906555714965542745497476498142308131411231289806542616607382475652","seed":74365517183906555714965542745497476498142308131411231289806542616607382475652,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   8960165 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 13 [0xd]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   8960165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"43.clkmgr_regwen.61113889992875354744312841045012367559188392973210555715971529063811168830107","seed":61113889992875354744312841045012367559188392973210555715971529063811168830107,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2792565 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2792565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"44.clkmgr_regwen.31543793429623794784664485261015802260128057850260284173143274435721707988700","seed":31543793429623794784664485261015802260128057850260284173143274435721707988700,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   7273563 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   7273563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"46.clkmgr_regwen.85637582714753821204048032641555982634558610550404736294120031816476498486603","seed":85637582714753821204048032641555982634558610550404736294120031816476498486603,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6731812 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   6731812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"49.clkmgr_regwen.91547107454564602967277084466681508494407607362241727419631509366095952266148","seed":91547107454564602967277084466681508494407607362241727419631509366095952266148,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5933226 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   5933226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.main_meas_ctrl_en":[{"name":"clkmgr_regwen","qual_name":"1.clkmgr_regwen.113161891756420860230796889652540892349165552172538669236194378854131813426894","seed":113161891756420860230796889652540892349165552172538669236194378854131813426894,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3216400 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @   3216400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"4.clkmgr_regwen.45866291426983739765432760730753904414479871473318306630400029909456524507376","seed":45866291426983739765432760730753904414479871473318306630400029909456524507376,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  11133974 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @  11133974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"24.clkmgr_regwen.92705723769373406521417517548249146501692889871012197371543031885262523958598","seed":92705723769373406521417517548249146501692889871012197371543031885262523958598,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4016332 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @   4016332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"29.clkmgr_regwen.10574226710357882592533241066830745255833439163369101890016333332105377777321","seed":10574226710357882592533241066830745255833439163369101890016333332105377777321,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  11536243 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (13 [0xd] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @  11536243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"34.clkmgr_regwen.39663942324935633152407831438485627050784257506810276884230383100435064584373","seed":39663942324935633152407831438485627050784257506810276884230383100435064584373,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  11414802 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (8 [0x8] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @  11414802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"41.clkmgr_regwen.60874390613217397290888276125537162435590513063273878914898513903617754904406","seed":60874390613217397290888276125537162435590513063273878914898513903617754904406,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   9429022 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (15 [0xf] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @   9429022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed":[{"name":"clkmgr_regwen","qual_name":"8.clkmgr_regwen.70233976906095240608531165486560293825894653903439401236506308789712893198573","seed":70233976906095240608531165486560293825894653903439401236506308789712893198573,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2980720 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   2980720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"12.clkmgr_regwen.94380519061087533375445986087443329765807756343007344829817099609377033259708","seed":94380519061087533375445986087443329765807756343007344829817099609377033259708,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5838319 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   5838319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"13.clkmgr_regwen.90838895340428415473110218838499282732320851141365755321298337783602958776728","seed":90838895340428415473110218838499282732320851141365755321298337783602958776728,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2049513 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   2049513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"17.clkmgr_regwen.66853377478701567391554522683042837793836114805375108730437245119919267478734","seed":66853377478701567391554522683042837793836114805375108730437245119919267478734,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4236950 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   4236950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"22.clkmgr_regwen.106931435832703226072209575521498643913202200111569402039793464352572788689929","seed":106931435832703226072209575521498643913202200111569402039793464352572788689929,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4203514 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   4203514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"26.clkmgr_regwen.44814280220994485833628781760846073080125146163252626285294357478593134004781","seed":44814280220994485833628781760846073080125146163252626285294357478593134004781,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4734226 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   4734226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"27.clkmgr_regwen.6168418356542609609788269796073612366813286967628247552057118942930945382034","seed":6168418356542609609788269796073612366813286967628247552057118942930945382034,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2680191 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   2680191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"32.clkmgr_regwen.28119363085623020897275739779935225989470607567729670169181801418487354585670","seed":28119363085623020897275739779935225989470607567729670169181801418487354585670,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   8228726 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   8228726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"33.clkmgr_regwen.77449413651011003474691225263434387471930000559647517235333736339476696025365","seed":77449413651011003474691225263434387471930000559647517235333736339476696025365,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6836181 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   6836181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"35.clkmgr_regwen.77463440944243908640682210506687801146883065808638761311610256770699526261138","seed":77463440944243908640682210506687801146883065808638761311610256770699526261138,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  28835347 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @  28835347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"39.clkmgr_regwen.14764732419471633393398913185295234069549598772404852423313505470869458255326","seed":14764732419471633393398913185295234069549598772404852423313505470869458255326,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5373671 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   5373671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"45.clkmgr_regwen.31566561357673955718704894863803663682230007413312322084928119113367044729637","seed":31566561357673955718704894863803663682230007413312322084928119113367044729637,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   8206296 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   8206296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"47.clkmgr_regwen.42786281325933281277509256314356256153698260426885783395880006159987396037981","seed":42786281325933281277509256314356256153698260426885783395880006159987396037981,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   7322905 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   7322905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"48.clkmgr_regwen.50970557108963933288225963349861116804641195329918003609337978286032812032313","seed":50970557108963933288225963349861116804641195329918003609337978286032812032313,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2162101 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   2162101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":381,"total":710,"percent":53.66197183098591}