{"block":{"name":"dma","variant":null,"commit":"5b8f6746131e231116e685585432b70359d2c727","commit_short":"5b8f674","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/5b8f6746131e231116e685585432b70359d2c727","revision_info":"GitHub Revision: [`5b8f674`](https://github.com/lowrisc/opentitan/tree/5b8f6746131e231116e685585432b70359d2c727)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-04-20T00:07:04Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/dma/data/dma_testplan.html","stages":{"V1":{"testpoints":{"dma_memory_smoke":{"tests":{"dma_memory_smoke":{"max_time":32.0,"sim_time":456.958532,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"dma_handshake_smoke":{"tests":{"dma_handshake_smoke":{"max_time":32.0,"sim_time":316.49013299999996,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"dma_generic_smoke":{"tests":{"dma_generic_smoke":{"max_time":35.0,"sim_time":320.60881900000004,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"dma_csr_hw_reset":{"max_time":2.0,"sim_time":15.431379000000002,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"dma_csr_rw":{"max_time":2.0,"sim_time":20.580232,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"dma_csr_bit_bash":{"max_time":15.0,"sim_time":1035.080557,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"dma_csr_aliasing":{"max_time":9.0,"sim_time":1181.86148,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"dma_csr_mem_rw_with_rand_reset":{"max_time":3.0,"sim_time":31.393587,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"dma_csr_rw":{"max_time":2.0,"sim_time":20.580232,"passed":20,"total":20,"percent":100.0},"dma_csr_aliasing":{"max_time":9.0,"sim_time":1181.86148,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":155,"total":155,"percent":100.0},"V2":{"testpoints":{"dma_memory_region_lock":{"tests":{"dma_memory_region_lock":{"max_time":74.0,"sim_time":10282.691899,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"dma_memory_tl_error":{"tests":{"dma_memory_stress":{"max_time":655.0,"sim_time":832685.9843830001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"dma_handshake_tl_error":{"tests":{"dma_handshake_stress":{"max_time":698.0,"sim_time":742031.06886,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"dma_handshake_stress":{"tests":{"dma_handshake_stress":{"max_time":698.0,"sim_time":742031.06886,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"dma_memory_stress":{"tests":{"dma_memory_stress":{"max_time":655.0,"sim_time":832685.9843830001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"dma_generic_stress":{"tests":{"dma_generic_stress":{"max_time":1489.0,"sim_time":863951.48252,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"dma_handshake_mem_buffer_overflow":{"tests":{"dma_handshake_stress":{"max_time":698.0,"sim_time":742031.06886,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"dma_abort":{"tests":{"dma_abort":{"max_time":26.0,"sim_time":472.110397,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"dma_stress_all":{"tests":{"dma_stress_all":{"max_time":311.0,"sim_time":83179.680586,"passed":2,"total":3,"percent":66.66666666666667}},"passed":2,"total":3,"percent":66.66666666666667},"alert_test":{"tests":{"dma_alert_test":{"max_time":2.0,"sim_time":26.155403999999997,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"dma_intr_test":{"max_time":2.0,"sim_time":11.110306000000001,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"dma_tl_errors":{"max_time":4.0,"sim_time":174.21636900000001,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"dma_tl_errors":{"max_time":4.0,"sim_time":174.21636900000001,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"dma_csr_hw_reset":{"max_time":2.0,"sim_time":15.431379000000002,"passed":5,"total":5,"percent":100.0},"dma_csr_rw":{"max_time":2.0,"sim_time":20.580232,"passed":20,"total":20,"percent":100.0},"dma_csr_aliasing":{"max_time":9.0,"sim_time":1181.86148,"passed":5,"total":5,"percent":100.0},"dma_same_csr_outstanding":{"max_time":3.0,"sim_time":75.285391,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"dma_csr_hw_reset":{"max_time":2.0,"sim_time":15.431379000000002,"passed":5,"total":5,"percent":100.0},"dma_csr_rw":{"max_time":2.0,"sim_time":20.580232,"passed":20,"total":20,"percent":100.0},"dma_csr_aliasing":{"max_time":9.0,"sim_time":1181.86148,"passed":5,"total":5,"percent":100.0},"dma_same_csr_outstanding":{"max_time":3.0,"sim_time":75.285391,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":193,"total":194,"percent":99.48453608247422},"V2S":{"testpoints":{"dma_illegal_addr_range":{"tests":{"dma_mem_enabled":{"max_time":29.0,"sim_time":181.39265799999998,"passed":5,"total":5,"percent":100.0},"dma_generic_stress":{"max_time":1489.0,"sim_time":863951.48252,"passed":5,"total":5,"percent":100.0},"dma_handshake_stress":{"max_time":698.0,"sim_time":742031.06886,"passed":3,"total":3,"percent":100.0}},"passed":13,"total":13,"percent":100.0},"dma_config_lock":{"tests":{"dma_config_lock":{"max_time":11.0,"sim_time":298.731147,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"tl_intg_err":{"tests":{"dma_sec_cm":{"max_time":2.0,"sim_time":37.277724,"passed":5,"total":5,"percent":100.0},"dma_tl_intg_err":{"max_time":4.0,"sim_time":103.862316,"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":53,"total":53,"percent":100.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"dma_short_transfer":{"max_time":166.0,"sim_time":200000.0,"passed":24,"total":25,"percent":96.0},"dma_longer_transfer":{"max_time":6.0,"sim_time":530.801147,"passed":5,"total":5,"percent":100.0},"dma_stress_all_with_rand_reset":{"max_time":4.0,"sim_time":1315.468679,"passed":0,"total":1,"percent":0.0}},"passed":29,"total":31,"percent":93.54838709677419}},"passed":29,"total":31,"percent":93.54838709677419}},"coverage":{"code":{"block":97.38,"line_statement":96.89,"branch":95.83,"condition_expression":null,"toggle":83.12,"fsm":92.96},"assertion":95.97,"functional":77.82},"cov_report_page":"/nightly/current_run/scratch/master/dma-sim-xcelium/cov_report/index.html","failed_jobs":{"buckets":{"UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"dma_stress_all_with_rand_reset","qual_name":"0.dma_stress_all_with_rand_reset.109398907714705168686527565664996096877470271119899293080959599118313903380366","seed":109398907714705168686527565664996096877470271119899293080959599118313903380366,"line":95,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1315468679ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1315468679ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ *ps: (dma_scoreboard.sv:698) [scoreboard] Check failed curr_intr == exp_intr (* [*] vs * [*]) Unexpected state of interrupt signals (Mismatched: ChunkDone )":[{"name":"dma_stress_all","qual_name":"2.dma_stress_all.30605854150555788744381530550367049854335402723255661693149196197853763145617","seed":30605854150555788744381530550367049854335402723255661693149196197853763145617,"line":269,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/2.dma_stress_all/latest/run.log","log_context":["UVM_ERROR @ 11927200575ps: (dma_scoreboard.sv:698) [uvm_test_top.env.scoreboard] Check failed curr_intr == exp_intr (0 [0x0] vs 2 [0x2]) Unexpected state of interrupt signals (Mismatched: ChunkDone )\n","UVM_INFO @ 11927200575ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ *ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of *ps hit, indicating a probable testbench issue":[{"name":"dma_short_transfer","qual_name":"6.dma_short_transfer.52077021310823914443662803887223132108483384147476657605320297246578377923920","seed":52077021310823914443662803887223132108483384147476657605320297246578377923920,"line":2185,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/6.dma_short_transfer/latest/run.log","log_context":["UVM_FATAL @ 200000000000ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000ps hit, indicating a probable testbench issue\n","UVM_INFO @ 200000000000ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":392,"total":395,"percent":99.24050632911393}