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[`5b8f674`](https://github.com/lowrisc/opentitan/tree/5b8f6746131e231116e685585432b70359d2c727)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-20T00:07:04Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/edn_edn0/data/edn_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"edn_smoke":{"max_time":1.37,"sim_time":17.451306,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"edn_csr_hw_reset":{"max_time":1.28,"sim_time":15.46977,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"edn_csr_rw":{"max_time":1.36,"sim_time":24.213905999999998,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"edn_csr_bit_bash":{"max_time":3.37,"sim_time":139.182714,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"edn_csr_aliasing":{"max_time":1.98,"sim_time":67.726123,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"edn_csr_mem_rw_with_rand_reset":{"max_time":2.06,"sim_time":69.88009600000001,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"edn_csr_rw":{"max_time":1.36,"sim_time":24.213905999999998,"passed":20,"total":20,"percent":100.0},"edn_csr_aliasing":{"max_time":1.98,"sim_time":67.726123,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":105,"total":105,"percent":100.0},"V2":{"testpoints":{"firmware":{"tests":{"edn_genbits":{"max_time":173.92,"sim_time":14579.981388,"passed":300,"total":300,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"csrng_commands":{"tests":{"edn_genbits":{"max_time":173.92,"sim_time":14579.981388,"passed":300,"total":300,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"genbits":{"tests":{"edn_genbits":{"max_time":173.92,"sim_time":14579.981388,"passed":300,"total":300,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"interrupts":{"tests":{"edn_intr":{"max_time":1.47,"sim_time":20.603163000000002,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"alerts":{"tests":{"edn_alert":{"max_time":1.86,"sim_time":176.20632500000002,"passed":200,"total":200,"percent":100.0}},"passed":200,"total":200,"percent":100.0},"errs":{"tests":{"edn_err":{"max_time":1.53,"sim_time":20.353128,"passed":100,"total":100,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"disable":{"tests":{"edn_disable":{"max_time":1.3,"sim_time":13.318175,"passed":50,"total":50,"percent":100.0},"edn_disable_auto_req_mode":{"max_time":4.37,"sim_time":500.0,"passed":42,"total":50,"percent":84.0}},"passed":92,"total":100,"percent":92.0},"stress_all":{"tests":{"edn_stress_all":{"max_time":6.76,"sim_time":388.341856,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"edn_intr_test":{"max_time":1.32,"sim_time":15.566947,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"alert_test":{"tests":{"edn_alert_test":{"max_time":1.67,"sim_time":59.202833,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"edn_tl_errors":{"max_time":3.66,"sim_time":101.12130400000001,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"edn_tl_errors":{"max_time":3.66,"sim_time":101.12130400000001,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"edn_csr_hw_reset":{"max_time":1.28,"sim_time":15.46977,"passed":5,"total":5,"percent":100.0},"edn_csr_rw":{"max_time":1.36,"sim_time":24.213905999999998,"passed":20,"total":20,"percent":100.0},"edn_csr_aliasing":{"max_time":1.98,"sim_time":67.726123,"passed":5,"total":5,"percent":100.0},"edn_same_csr_outstanding":{"max_time":1.63,"sim_time":71.733358,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"edn_csr_hw_reset":{"max_time":1.28,"sim_time":15.46977,"passed":5,"total":5,"percent":100.0},"edn_csr_rw":{"max_time":1.36,"sim_time":24.213905999999998,"passed":20,"total":20,"percent":100.0},"edn_csr_aliasing":{"max_time":1.98,"sim_time":67.726123,"passed":5,"total":5,"percent":100.0},"edn_same_csr_outstanding":{"max_time":1.63,"sim_time":71.733358,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":962,"total":970,"percent":99.17525773195877},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"edn_tl_intg_err":{"max_time":4.83,"sim_time":762.9868349999999,"passed":20,"total":20,"percent":100.0},"edn_sec_cm":{"max_time":6.99,"sim_time":563.8356040000001,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_config_regwen":{"t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Illegal bin hit":[{"name":"edn_stress_all_with_rand_reset","qual_name":"2.edn_stress_all_with_rand_reset.7446761899949227856477279120269579193221947949440236816199348766252112092656","seed":7446761899949227856477279120269579193221947949440236816199348766252112092656,"line":285,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/2.edn_stress_all_with_rand_reset/latest/run.log","log_context":["Error-[FCIBH] Illegal bin hit\n","/nightly/current_run/scratch/master/edn_edn0-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25\n","csrng_agent_pkg, \"csrng_agent_pkg::device_cmd_cg\"\n","  VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 2289985228 ps, Illegal \n","  state bin il of coverpoint csrng_cmd_cp in covergroup \n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"27.edn_stress_all_with_rand_reset.111141377731527693212659302327772154953665070435995250520246084533373235297867","seed":111141377731527693212659302327772154953665070435995250520246084533373235297867,"line":184,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/27.edn_stress_all_with_rand_reset/latest/run.log","log_context":["Error-[FCIBH] Illegal bin hit\n","/nightly/current_run/scratch/master/edn_edn0-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25\n","csrng_agent_pkg, \"csrng_agent_pkg::device_cmd_cg\"\n","  VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 1707944834 ps, Illegal \n","  state bin il of coverpoint csrng_cmd_cp in covergroup \n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"edn_disable_auto_req_mode","qual_name":"2.edn_disable_auto_req_mode.104882714482227820317387405077013264771037123294902516853832492923516323789640","seed":104882714482227820317387405077013264771037123294902516853832492923516323789640,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/2.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"44.edn_disable_auto_req_mode.106665988669935475353994647236580174139863948948492077704456383555777018102060","seed":106665988669935475353994647236580174139863948948492077704456383555777018102060,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/44.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"45.edn_disable_auto_req_mode.106723767699515367200129365803923669488950150219552065310891979160339232842993","seed":106723767699515367200129365803923669488950150219552065310891979160339232842993,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/45.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"edn_stress_all_with_rand_reset","qual_name":"8.edn_stress_all_with_rand_reset.19066644602269545803121260888680045539052797977360290526896295593310139415423","seed":19066644602269545803121260888680045539052797977360290526896295593310139415423,"line":166,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/8.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 280350867 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 280350867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"18.edn_stress_all_with_rand_reset.79246333596541061890129337072784328564534959559813609696554389692166223059256","seed":79246333596541061890129337072784328564534959559813609696554389692166223059256,"line":144,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/18.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1110510703 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1110510703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"25.edn_stress_all_with_rand_reset.111939691399757942708557022292313152208270184187483148395407535418159823941954","seed":111939691399757942708557022292313152208270184187483148395407535418159823941954,"line":204,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/25.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1355265250 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1355265250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"35.edn_stress_all_with_rand_reset.89339851153703757670683798247116200086692234222439924886081811246680313199177","seed":89339851153703757670683798247116200086692234222439924886081811246680313199177,"line":407,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/35.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5862723391 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5862723391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"43.edn_stress_all_with_rand_reset.68109741801390691573278712917927880467981765988107544545297085930003678228765","seed":68109741801390691573278712917927880467981765988107544545297085930003678228765,"line":131,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/43.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 150409990 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 150409990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1149) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.":[{"name":"edn_stress_all_with_rand_reset","qual_name":"9.edn_stress_all_with_rand_reset.41319399379544910026025351188681872645862257944034161280777670329040326594204","seed":41319399379544910026025351188681872645862257944034161280777670329040326594204,"line":309,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/9.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3248703754 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3248703754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.":[{"name":"edn_disable_auto_req_mode","qual_name":"9.edn_disable_auto_req_mode.335541376899832275685537090734682440711585936221345479958650196023159195463","seed":335541376899832275685537090734682440711585936221345479958650196023159195463,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/9.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @   8441252 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x000a7612 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @   8441252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"13.edn_disable_auto_req_mode.4841319934193151555556276654123245991825520540218460070596209149758603920903","seed":4841319934193151555556276654123245991825520540218460070596209149758603920903,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/13.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  34118858 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x001ed902 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  34118858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"19.edn_disable_auto_req_mode.41183652772661410294479473936193835890135312089099990469181531659268532592584","seed":41183652772661410294479473936193835890135312089099990469181531659268532592584,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/19.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  30031068 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x000009c2 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  30031068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"22.edn_disable_auto_req_mode.45640915695179567208682669604974450733133909107718899809808459445249431236237","seed":45640915695179567208682669604974450733133909107718899809808459445249431236237,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/22.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  43797705 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x0057a972 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  43797705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"32.edn_disable_auto_req_mode.44312325639293853275601207024642038630153997057553447887690596210634239194590","seed":44312325639293853275601207024642038630153997057553447887690596210634239194590,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/32.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  60492033 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00dd4602 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  60492033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1114,"total":1130,"percent":98.58407079646018}