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---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"4.keymgr_stress_all_with_rand_reset.25255788215567967869913741443636790728408906877378373463209685702969959159379","seed":25255788215567967869913741443636790728408906877378373463209685702969959159379,"line":112,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 605287374 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 605287374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"6.keymgr_stress_all_with_rand_reset.105235291587250573699678968824562970535049720477272589330793119831560849198637","seed":105235291587250573699678968824562970535049720477272589330793119831560849198637,"line":1222,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1293821158 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1293821158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"8.keymgr_stress_all_with_rand_reset.32029666273893049187568196576576726400957424379486932153072637301002103804264","seed":32029666273893049187568196576576726400957424379486932153072637301002103804264,"line":368,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/8.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 791483781 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 791483781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"9.keymgr_stress_all_with_rand_reset.79733379221601412208470387305530096185149110462275187753261797745876001101187","seed":79733379221601412208470387305530096185149110462275187753261797745876001101187,"line":192,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/9.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 162965719 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 162965719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"10.keymgr_stress_all_with_rand_reset.34035193064070082438919277658530402838283163871953853478425103938258742608394","seed":34035193064070082438919277658530402838283163871953853478425103938258742608394,"line":302,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 241943277 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 241943277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"11.keymgr_stress_all_with_rand_reset.100022633431488723098498839877516799066391898875707064841934264956910794476483","seed":100022633431488723098498839877516799066391898875707064841934264956910794476483,"line":782,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1402854843 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1402854843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"14.keymgr_stress_all_with_rand_reset.18459363628756229347184275731889694095081702258834405697671437337872744756998","seed":18459363628756229347184275731889694095081702258834405697671437337872744756998,"line":242,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/14.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 202246826 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 202246826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"15.keymgr_stress_all_with_rand_reset.53533182939987819261373677448468051828114853736274760805102994567601213523955","seed":53533182939987819261373677448468051828114853736274760805102994567601213523955,"line":1019,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/15.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 459239510 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 459239510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"19.keymgr_stress_all_with_rand_reset.61245692627681503130988394964484692535301573976350769835588865138706679588042","seed":61245692627681503130988394964484692535301573976350769835588865138706679588042,"line":220,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/19.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 626498460 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 626498460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"20.keymgr_stress_all_with_rand_reset.48255316482152232213401407948269267146580193794243336129820496113629806517418","seed":48255316482152232213401407948269267146580193794243336129820496113629806517418,"line":509,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/20.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 164977226 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 164977226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"22.keymgr_stress_all_with_rand_reset.16232565828425829170957659712534803477903557288348671413303696353101004699368","seed":16232565828425829170957659712534803477903557288348671413303696353101004699368,"line":144,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/22.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 228427870 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 228427870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"23.keymgr_stress_all_with_rand_reset.46406744278450851917934766570969600526470676164725152092837232789126079944655","seed":46406744278450851917934766570969600526470676164725152092837232789126079944655,"line":163,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/23.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 517231337 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 517231337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"28.keymgr_stress_all_with_rand_reset.919005767305208803260484211321214600655773691189784234144736138446832899155","seed":919005767305208803260484211321214600655773691189784234144736138446832899155,"line":552,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/28.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 407437954 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 407437954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"29.keymgr_stress_all_with_rand_reset.13300843968770242645554134258385586422950629085903509799967875247135691345553","seed":13300843968770242645554134258385586422950629085903509799967875247135691345553,"line":636,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/29.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 332507870 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 332507870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"33.keymgr_stress_all_with_rand_reset.111620724600525956364105758213153347818695075796694353114116624625950594091673","seed":111620724600525956364105758213153347818695075796694353114116624625950594091673,"line":256,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/33.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 916217296 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 916217296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"34.keymgr_stress_all_with_rand_reset.45275293898918795949121087670891913926202155186103832303372154329969445654277","seed":45275293898918795949121087670891913926202155186103832303372154329969445654277,"line":253,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/34.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 867796057 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 867796057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"35.keymgr_stress_all_with_rand_reset.78572683560782664589467888649395636833191179396019705426861798047629562828097","seed":78572683560782664589467888649395636833191179396019705426861798047629562828097,"line":179,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/35.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 881908206 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 881908206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"36.keymgr_stress_all_with_rand_reset.7716572406743757791547740193107435185017227594061713384111898976279941104812","seed":7716572406743757791547740193107435185017227594061713384111898976279941104812,"line":173,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/36.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 227359126 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 227359126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"39.keymgr_stress_all_with_rand_reset.24660325251394842620812409486234858350562226414761410641277288007978178946666","seed":24660325251394842620812409486234858350562226414761410641277288007978178946666,"line":586,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/39.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 531570484 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 531570484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"43.keymgr_stress_all_with_rand_reset.1041671215673450332741198438788408979188368687067453679888470372960312325550","seed":1041671215673450332741198438788408979188368687067453679888470372960312325550,"line":625,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/43.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 950736629 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 950736629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"46.keymgr_stress_all_with_rand_reset.58919581799728345419751244333093630012770741487849737537815279776686241840443","seed":58919581799728345419751244333093630012770741487849737537815279776686241840443,"line":1152,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/46.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 520535663 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 520535663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"47.keymgr_stress_all_with_rand_reset.114402405821278714686166577848403907633051833307608532515272196819862733077233","seed":114402405821278714686166577848403907633051833307608532515272196819862733077233,"line":612,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/47.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 793246197 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 793246197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*":[{"name":"keymgr_stress_all","qual_name":"10.keymgr_stress_all.92207421666600463705231075100261795774455036197441009836088050503681955889664","seed":92207421666600463705231075100261795774455036197441009836088050503681955889664,"line":131,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/10.keymgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   5275397 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @   5275397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all","qual_name":"21.keymgr_stress_all.56901164254537007033215392191739329272429516722937090990369433025796857449210","seed":56901164254537007033215392191739329272429516722937090990369433025796857449210,"line":1645,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/21.keymgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 540654736 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @ 540654736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StDisabled for Attestation Aes":[{"name":"keymgr_lc_disable","qual_name":"23.keymgr_lc_disable.88607788255170393851090159016298875779008348225789125256346395828330794795466","seed":88607788255170393851090159016298875779008348225789125256346395828330794795466,"line":322,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/23.keymgr_lc_disable/latest/run.log","log_context":["UVM_ERROR @ 134036653 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (5871019733847025646337092295919802842118368242867584736796168660890482027417004349128113643086783037664983630185837532999677537660101708858395686811221891 [0x7018f259b30eb1a0cc8eac4e4a91badf38383f1382eaec71fe14792ca4feb61c7becdc5e5d59bba4154ea8ce4fa3ace66bdf8ad6513e7eaa7dfa20e706cc3f83] vs 5871019733847025646337092295919802842118368242867584736796168660890482027417004349128113643086783037664983630185837532999677537660101708858395686811221891 [0x7018f259b30eb1a0cc8eac4e4a91badf38383f1382eaec71fe14792ca4feb61c7becdc5e5d59bba4154ea8ce4fa3ace66bdf8ad6513e7eaa7dfa20e706cc3f83]) AES key at state StDisabled for Attestation Aes\n","UVM_INFO @ 134036653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_*":[{"name":"keymgr_stress_all","qual_name":"46.keymgr_stress_all.95185028010664053426339057780818456967136916452087202659567858461733742339186","seed":95185028010664053426339057780818456967136916452087202659567858461733742339186,"line":281,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/46.keymgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 334469249 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3341711553 [0xc72e78c1] vs 3341711553 [0xc72e78c1]) reg name: keymgr_reg_block.sw_share1_output_5\n","UVM_INFO @ 334469249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1083,"total":1110,"percent":97.56756756756756}