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(cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"0.alert_handler_stress_all_with_rand_reset.27518083803740519334719955585324755319714596021902421523996020710730015400056","seed":27518083803740519334719955585324755319714596021902421523996020710730015400056,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 108959607 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 108959607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"1.alert_handler_stress_all_with_rand_reset.94112507233109743186662216239180927245553841924540581478934937324369309381840","seed":94112507233109743186662216239180927245553841924540581478934937324369309381840,"line":118,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 811761805 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 811761805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"5.alert_handler_stress_all_with_rand_reset.37772336787601576042801074717755334577918833877366170343647388863392272905933","seed":37772336787601576042801074717755334577918833877366170343647388863392272905933,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 757459462 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 757459462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"11.alert_handler_stress_all_with_rand_reset.38102895738997285160012092235284424902199248455144297489548305967535752908087","seed":38102895738997285160012092235284424902199248455144297489548305967535752908087,"line":85,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 211819215 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 211819215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"17.alert_handler_stress_all_with_rand_reset.42307448732896209805225783903309933831229307468141765525402518892060698005834","seed":42307448732896209805225783903309933831229307468141765525402518892060698005834,"line":144,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4819559875 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4819559875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"18.alert_handler_stress_all_with_rand_reset.44642793225092773797211463492964904266604324435924724813392095794739270442466","seed":44642793225092773797211463492964904266604324435924724813392095794739270442466,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 217219626 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 217219626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"31.alert_handler_stress_all_with_rand_reset.101102758649174460111731231800127912288090258741841293285532094729215034801611","seed":101102758649174460111731231800127912288090258741841293285532094729215034801611,"line":83,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 115160799 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 115160799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"34.alert_handler_stress_all_with_rand_reset.28990680982176637617314344554126882035552205881109539995199864861256800867681","seed":28990680982176637617314344554126882035552205881109539995199864861256800867681,"line":83,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/34.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 430743781 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 430743781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"37.alert_handler_stress_all_with_rand_reset.64248895556539915553819620629520717965929364158773608845696192906995772313566","seed":64248895556539915553819620629520717965929364158773608845696192906995772313566,"line":121,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/37.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4871615902 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4871615902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"42.alert_handler_stress_all_with_rand_reset.94082511732178294477090933332584098315866806337150832469871737326233400278249","seed":94082511732178294477090933332584098315866806337150832469871737326233400278249,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/42.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2342940335 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2342940335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"44.alert_handler_stress_all_with_rand_reset.38003186701676416707210895761909332712616437173459481331185709663548271535206","seed":38003186701676416707210895761909332712616437173459481331185709663548271535206,"line":83,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/44.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2732464279 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2732464279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model.":[{"name":"alert_handler_ping_timeout","qual_name":"2.alert_handler_ping_timeout.76518366072973743082962645311916636407711907898205560596171977043083308814071","seed":76518366072973743082962645311916636407711907898205560596171977043083308814071,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 650046628 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 650046628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"3.alert_handler_ping_timeout.138010800364498495007308733188014908434584406371208714578771302356366835244","seed":138010800364498495007308733188014908434584406371208714578771302356366835244,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 318618014 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 318618014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_lpg","qual_name":"30.alert_handler_lpg.94513585046507334341654560198667241775811490755129592024895550387905928963611","seed":94513585046507334341654560198667241775811490755129592024895550387905928963611,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/30.alert_handler_lpg/latest/run.log","log_context":["UVM_ERROR @ 489498858 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 489498858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"35.alert_handler_ping_timeout.49749455068717393855376395420652470659272436667810619492686162628598198937635","seed":49749455068717393855376395420652470659272436667810619492686162628598198937635,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 262926353 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 262926353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"36.alert_handler_ping_timeout.9788585066317039210006372312401252645661867206880491660762618531725303043020","seed":9788585066317039210006372312401252645661867206880491660762618531725303043020,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/36.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 658293025 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 658293025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state":[{"name":"alert_handler_ping_timeout","qual_name":"4.alert_handler_ping_timeout.7874669433590081309833706565134151625056727827252584546349697705465353061530","seed":7874669433590081309833706565134151625056727827252584546349697705465353061530,"line":153,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 15406716701 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 15406716701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"5.alert_handler_ping_timeout.113470014760215382262710115840901498721674890313464626221436926195329346959246","seed":113470014760215382262710115840901498721674890313464626221436926195329346959246,"line":135,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 9148727408 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 9148727408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"7.alert_handler_ping_timeout.108142059884271658781519280079848138794225548201028191914727012198885074081172","seed":108142059884271658781519280079848138794225548201028191914727012198885074081172,"line":87,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 4228745664 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 4228745664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"9.alert_handler_ping_timeout.113987997505464629647356643034703497161501306266572900915352946136817851376164","seed":113987997505464629647356643034703497161501306266572900915352946136817851376164,"line":96,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 5966040749 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 5966040749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"10.alert_handler_ping_timeout.106134937973677711018456588652166848371016653810628093069079236128625792430537","seed":106134937973677711018456588652166848371016653810628093069079236128625792430537,"line":102,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 14485963322 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 14485963322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"11.alert_handler_ping_timeout.57723754765613217856204467557066158643476402404161543949107708829911460578297","seed":57723754765613217856204467557066158643476402404161543949107708829911460578297,"line":147,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 9390676548 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 9390676548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"12.alert_handler_ping_timeout.228653712501165729806565265975246488566647092474433853078159159585634254989","seed":228653712501165729806565265975246488566647092474433853078159159585634254989,"line":102,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 19876302530 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 19876302530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"17.alert_handler_ping_timeout.110053592377401539237871443622840044554924839692816098302941643950230631969990","seed":110053592377401539237871443622840044554924839692816098302941643950230631969990,"line":111,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 20862709195 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 20862709195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"19.alert_handler_ping_timeout.35256806258907692196381263653655247384199680556260140989695512277600329989615","seed":35256806258907692196381263653655247384199680556260140989695512277600329989615,"line":120,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 49181072647 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 49181072647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"21.alert_handler_ping_timeout.81773230345533247437613901307799585066308567043498206664080029414841199771075","seed":81773230345533247437613901307799585066308567043498206664080029414841199771075,"line":111,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 18593227170 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 18593227170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"22.alert_handler_ping_timeout.23345511474350489781108094031278259607270666771230089417628948626185174819453","seed":23345511474350489781108094031278259607270666771230089417628948626185174819453,"line":126,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 12773883628 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 12773883628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"23.alert_handler_ping_timeout.33662668894551501312842052701894296787196913106159409856293667333255005752548","seed":33662668894551501312842052701894296787196913106159409856293667333255005752548,"line":118,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 8324987461 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 8324987461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"24.alert_handler_ping_timeout.51404871021933436425955914664339770693174944993464510959349697658406786575440","seed":51404871021933436425955914664339770693174944993464510959349697658406786575440,"line":105,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 18276199288 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 18276199288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"25.alert_handler_ping_timeout.46594976362462614340929966032748292896791323124663584462106298905256110477172","seed":46594976362462614340929966032748292896791323124663584462106298905256110477172,"line":141,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/25.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 10066467894 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 10066467894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"26.alert_handler_ping_timeout.20812779933318746843557628776953963365518905398796511685577725539601679167812","seed":20812779933318746843557628776953963365518905398796511685577725539601679167812,"line":93,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 4976631360 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 4976631360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"28.alert_handler_ping_timeout.75156738276061934428345090102927395887222479222018911533565713184996643369307","seed":75156738276061934428345090102927395887222479222018911533565713184996643369307,"line":90,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 6132096715 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 6132096715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"32.alert_handler_ping_timeout.58829660405816967307164300630032102686130346433059728195443057820993939047910","seed":58829660405816967307164300630032102686130346433059728195443057820993939047910,"line":113,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 15584125837 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 15584125837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"33.alert_handler_ping_timeout.51477421989867331643087427012868093770775335725719475917671821716625137777027","seed":51477421989867331643087427012868093770775335725719475917671821716625137777027,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 10876941853 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 10876941853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"37.alert_handler_ping_timeout.101917105448032293408949578540563686850935519858477490986701646319268130773034","seed":101917105448032293408949578540563686850935519858477490986701646319268130773034,"line":87,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 4804959011 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 4804959011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"39.alert_handler_ping_timeout.2066148722639151641321885968821757820711845334599629687518287037719029740132","seed":2066148722639151641321885968821757820711845334599629687518287037719029740132,"line":99,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/39.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 7942188489 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 7942188489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"40.alert_handler_ping_timeout.83626682106719006612582494482566128415731994577562153711086510586473881289663","seed":83626682106719006612582494482566128415731994577562153711086510586473881289663,"line":113,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 16648133774 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 16648133774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"41.alert_handler_ping_timeout.34891116879438552813400597796974424040648479976355303693127593322369936975471","seed":34891116879438552813400597796974424040648479976355303693127593322369936975471,"line":114,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 9853125837 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 9853125837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"42.alert_handler_ping_timeout.79557178161952307849577036443486970744648183805653686592581459234162336394328","seed":79557178161952307849577036443486970744648183805653686592581459234162336394328,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/42.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 964171914 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 964171914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"44.alert_handler_ping_timeout.66546852493457308062619942924133689457810365064177828896735980156035561943541","seed":66546852493457308062619942924133689457810365064177828896735980156035561943541,"line":93,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/44.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 18534776713 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 18534776713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"45.alert_handler_ping_timeout.8111851973930742884775126540726624993455017241064720785456074785013190521240","seed":8111851973930742884775126540726624993455017241064720785456074785013190521240,"line":114,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 26391471903 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 26391471903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"46.alert_handler_ping_timeout.87220875264729838329552809345059515793123943968853187846755204971307060427651","seed":87220875264729838329552809345059515793123943968853187846755204971307060427651,"line":96,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 3844945879 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 3844945879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"48.alert_handler_ping_timeout.97889245729222035928276313557316686509669340672193474162277501505145443796887","seed":97889245729222035928276313557316686509669340672193474162277501505145443796887,"line":117,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/48.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 11672841050 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 11672841050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalEscIntFail)":[{"name":"alert_handler_stress_all","qual_name":"11.alert_handler_stress_all.8326280675070913778772056749752047581553610494700505346723191253464644694031","seed":8326280675070913778772056749752047581553610494700505346723191253464644694031,"line":172,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_stress_all/latest/run.log","log_context":["UVM_ERROR @ 4852808454 ps: (alert_handler_scoreboard.sv:258) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[2]: saw 0, but expected 1. (is_int_err = 1, local_alert_type = LocalEscIntFail)\n","UVM_INFO @ 4852808454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_accum_cnt":[{"name":"alert_handler_lpg","qual_name":"17.alert_handler_lpg.105918362702247839608750838513008017197215931028456273661329835211306633539101","seed":105918362702247839608750838513008017197215931028456273661329835211306633539101,"line":82,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_lpg/latest/run.log","log_context":["UVM_ERROR @ 30063022163 ps: (alert_handler_scoreboard.sv:490) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (860 [0x35c] vs 861 [0x35d]) reg name: alert_handler_reg_block.classc_accum_cnt\n","UVM_INFO @ 30063022163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1149) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.":[{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"20.alert_handler_stress_all_with_rand_reset.108073355643845226824786035391775714716040325107194713090703610634122539227133","seed":108073355643845226824786035391775714716040325107194713090703610634122539227133,"line":82,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 205596376 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 205596376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"48.alert_handler_stress_all_with_rand_reset.54186010225240033401778450785704983340371804245134880540659314293910630550389","seed":54186010225240033401778450785704983340371804245134880540659314293910630550389,"line":119,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/48.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5722089283 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 5722089283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job timed out after * minutes":[{"name":"alert_handler_entropy","qual_name":"46.alert_handler_entropy.73312309159910464661084976590852060267163781208918679477116638998988935539066","seed":73312309159910464661084976590852060267163781208918679477116638998988935539066,"line":null,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_entropy/latest/run.log","log_context":["Job timed out after 60 minutes"]}]}},"passed":802,"total":850,"percent":94.3529411764706}