{"block":{"name":"clkmgr","variant":null,"commit":"8007f614bd52d7ac557e5e3253489f0bf7b820c5","commit_short":"8007f61","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/8007f614bd52d7ac557e5e3253489f0bf7b820c5","revision_info":"GitHub Revision: [`8007f61`](https://github.com/lowrisc/opentitan/tree/8007f614bd52d7ac557e5e3253489f0bf7b820c5)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-24T16:00:28Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"clkmgr_smoke":{"max_time":2.81,"sim_time":253.33103,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.71,"sim_time":167.045716,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"clkmgr_csr_rw":{"max_time":0.93,"sim_time":43.942339999999994,"passed":8,"total":20,"percent":40.0}},"passed":8,"total":20,"percent":40.0},"csr_bit_bash":{"tests":{"clkmgr_csr_bit_bash":{"max_time":2.43,"sim_time":196.22575700000002,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"csr_aliasing":{"tests":{"clkmgr_csr_aliasing":{"max_time":1.04,"sim_time":39.02343,"passed":2,"total":5,"percent":40.0}},"passed":2,"total":5,"percent":40.0},"csr_mem_rw_with_rand_reset":{"tests":{"clkmgr_csr_mem_rw_with_rand_reset":{"max_time":1.49,"sim_time":99.78101099999999,"passed":7,"total":20,"percent":35.0}},"passed":7,"total":20,"percent":35.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"clkmgr_csr_rw":{"max_time":0.93,"sim_time":43.942339999999994,"passed":8,"total":20,"percent":40.0},"clkmgr_csr_aliasing":{"max_time":1.04,"sim_time":39.02343,"passed":2,"total":5,"percent":40.0}},"passed":10,"total":25,"percent":40.0}},"passed":72,"total":105,"percent":68.57142857142857},"V2":{"testpoints":{"peri_enables":{"tests":{"clkmgr_peri":{"max_time":1.71,"sim_time":132.097452,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"trans_enables":{"tests":{"clkmgr_trans":{"max_time":3.26,"sim_time":368.994288,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"clk_status":{"tests":{"clkmgr_clk_status":{"max_time":2.24,"sim_time":202.683766,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"jitter":{"tests":{"clkmgr_smoke":{"max_time":2.81,"sim_time":253.33103,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"frequency":{"tests":{"clkmgr_frequency":{"max_time":0.98,"sim_time":15.349174000000001,"passed":1,"total":50,"percent":2.0}},"passed":1,"total":50,"percent":2.0},"frequency_timeout":{"tests":{"clkmgr_frequency_timeout":{"max_time":0.89,"sim_time":13.98792,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":50,"percent":0.0},"frequency_overflow":{"tests":{"clkmgr_frequency":{"max_time":0.98,"sim_time":15.349174000000001,"passed":1,"total":50,"percent":2.0}},"passed":1,"total":50,"percent":2.0},"stress_all":{"tests":{"clkmgr_stress_all":{"max_time":4.54,"sim_time":474.522195,"passed":3,"total":50,"percent":6.0}},"passed":3,"total":50,"percent":6.0},"alert_test":{"tests":{"clkmgr_alert_test":{"max_time":2.63,"sim_time":251.892324,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"clkmgr_tl_errors":{"max_time":16.74,"sim_time":1776.8502839999999,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"clkmgr_tl_errors":{"max_time":16.74,"sim_time":1776.8502839999999,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.71,"sim_time":167.045716,"passed":5,"total":5,"percent":100.0},"clkmgr_csr_rw":{"max_time":0.93,"sim_time":43.942339999999994,"passed":8,"total":20,"percent":40.0},"clkmgr_csr_aliasing":{"max_time":1.04,"sim_time":39.02343,"passed":2,"total":5,"percent":40.0},"clkmgr_same_csr_outstanding":{"max_time":1.31,"sim_time":81.2475,"passed":2,"total":20,"percent":10.0}},"passed":17,"total":50,"percent":34.0},"tl_d_partial_access":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.71,"sim_time":167.045716,"passed":5,"total":5,"percent":100.0},"clkmgr_csr_rw":{"max_time":0.93,"sim_time":43.942339999999994,"passed":8,"total":20,"percent":40.0},"clkmgr_csr_aliasing":{"max_time":1.04,"sim_time":39.02343,"passed":2,"total":5,"percent":40.0},"clkmgr_same_csr_outstanding":{"max_time":1.31,"sim_time":81.2475,"passed":2,"total":20,"percent":10.0}},"passed":17,"total":50,"percent":34.0}},"passed":291,"total":470,"percent":61.91489361702128},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"clkmgr_sec_cm":{"max_time":6.78,"sim_time":585.354348,"passed":3,"total":5,"percent":60.0},"clkmgr_tl_intg_err":{"max_time":0.85,"sim_time":30.989100999999998,"passed":0,"total":20,"percent":0.0}},"passed":3,"total":25,"percent":12.0},"shadow_reg_update_error":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":4.09,"sim_time":450.61773,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_read_clear_staged_value":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":4.09,"sim_time":450.61773,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_storage_error":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":4.09,"sim_time":450.61773,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadowed_reset_glitch":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":4.09,"sim_time":450.61773,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_update_error_with_csr_rw":{"tests":{"clkmgr_shadow_reg_errors_with_csr_rw":{"max_time":0.91,"sim_time":31.258428,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"sec_cm_bus_integrity":{"tests":{"clkmgr_tl_intg_err":{"max_time":0.85,"sim_time":30.989100999999998,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"sec_cm_meas_clk_bkgn_chk":{"tests":{"clkmgr_frequency":{"max_time":0.98,"sim_time":15.349174000000001,"passed":1,"total":50,"percent":2.0}},"passed":1,"total":50,"percent":2.0},"sec_cm_timeout_clk_bkgn_chk":{"tests":{"clkmgr_frequency_timeout":{"max_time":0.89,"sim_time":13.98792,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":50,"percent":0.0},"sec_cm_meas_config_shadow":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":4.09,"sim_time":450.61773,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_idle_intersig_mubi":{"tests":{"clkmgr_idle_intersig_mubi":{"max_time":3.17,"sim_time":317.829941,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_jitter_config_mubi":{"tests":{"clkmgr_csr_rw":{"max_time":0.93,"sim_time":43.942339999999994,"passed":8,"total":20,"percent":40.0}},"passed":8,"total":20,"percent":40.0},"sec_cm_idle_ctr_redun":{"tests":{"clkmgr_sec_cm":{"max_time":6.78,"sim_time":585.354348,"passed":3,"total":5,"percent":60.0}},"passed":3,"total":5,"percent":60.0},"sec_cm_meas_config_regwen":{"tests":{"clkmgr_csr_rw":{"max_time":0.93,"sim_time":43.942339999999994,"passed":8,"total":20,"percent":40.0}},"passed":8,"total":20,"percent":40.0},"sec_cm_clk_ctrl_config_regwen":{"tests":{"clkmgr_csr_rw":{"max_time":0.93,"sim_time":43.942339999999994,"passed":8,"total":20,"percent":40.0}},"passed":8,"total":20,"percent":40.0},"prim_count_check":{"tests":{"clkmgr_sec_cm":{"max_time":6.78,"sim_time":585.354348,"passed":3,"total":5,"percent":60.0}},"passed":3,"total":5,"percent":60.0}},"passed":82,"total":235,"percent":34.8936170212766},"V3":{"testpoints":{"regwen":{"tests":{"clkmgr_regwen":{"max_time":0.89,"sim_time":24.402092,"passed":2,"total":50,"percent":4.0}},"passed":2,"total":50,"percent":4.0},"stress_all_with_rand_reset":{"tests":{"clkmgr_stress_all_with_rand_reset":{"max_time":123.78000000000002,"sim_time":12909.779823,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":50,"percent":0.0}},"passed":2,"total":100,"percent":2.0}},"coverage":{"code":{"block":null,"line_statement":92.16,"branch":95.28,"condition_expression":90.37,"toggle":100.0,"fsm":62.5},"assertion":94.42,"functional":78.32},"cov_report_page":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*":[{"name":"clkmgr_frequency","qual_name":"0.clkmgr_frequency.25815634011093591265640749225643585391062157194167773948929187963839714155673","seed":25815634011093591265640749225643585391062157194167773948929187963839714155673,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  15349174 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  15349174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"0.clkmgr_stress_all_with_rand_reset.57103913710071883066915252846672442262307961579058141044402658096440804175528","seed":57103913710071883066915252846672442262307961579058141044402658096440804175528,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  35977359 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  35977359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"1.clkmgr_frequency.111805124673539535443748873190791523567842510708865505910624362213223104826755","seed":111805124673539535443748873190791523567842510708865505910624362213223104826755,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6113657 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6113657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"1.clkmgr_stress_all_with_rand_reset.97733484077758528557244518007425845591278040713611502286362867870468281762444","seed":97733484077758528557244518007425845591278040713611502286362867870468281762444,"line":84,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  19855973 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  19855973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"1.clkmgr_stress_all.31853391633010202025103971373752356410130545040141924995260706146218408071904","seed":31853391633010202025103971373752356410130545040141924995260706146218408071904,"line":128,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 127048673 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 127048673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"2.clkmgr_frequency.90180453767714251513223133386583018803339734676673191108386276554872989750303","seed":90180453767714251513223133386583018803339734676673191108386276554872989750303,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6763399 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6763399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"2.clkmgr_stress_all_with_rand_reset.24198103155505515827722425823137292240651686480440760465972921601166652620063","seed":24198103155505515827722425823137292240651686480440760465972921601166652620063,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  11303303 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  11303303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"2.clkmgr_stress_all.71445270696736818350927373470197803856572473648624162139865689783772925377725","seed":71445270696736818350927373470197803856572473648624162139865689783772925377725,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  56860047 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  56860047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"3.clkmgr_frequency.29282377366421676427996940863802759881324619840211272970199154243673210673360","seed":29282377366421676427996940863802759881324619840211272970199154243673210673360,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5868769 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5868769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"3.clkmgr_stress_all_with_rand_reset.21490223346998019239131589866905719097295146306785549223789509511442312490597","seed":21490223346998019239131589866905719097295146306785549223789509511442312490597,"line":155,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 300321568 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 300321568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"3.clkmgr_stress_all.38619913794799025227144925078525236234717053210061321068191770160062672239300","seed":38619913794799025227144925078525236234717053210061321068191770160062672239300,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  24769945 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  24769945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"4.clkmgr_frequency.66533770143253585921588845997028361933960517519446410764556843961358847052063","seed":66533770143253585921588845997028361933960517519446410764556843961358847052063,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7233408 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7233408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"4.clkmgr_stress_all_with_rand_reset.94923511390448172672241230356352915391415889947264496430173171171689375511189","seed":94923511390448172672241230356352915391415889947264496430173171171689375511189,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  10271141 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  10271141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"5.clkmgr_frequency.114771079517656073769146329440527486131038131392723380625076095485031936339171","seed":114771079517656073769146329440527486131038131392723380625076095485031936339171,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   8156297 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8156297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"6.clkmgr_frequency.37896876308310642891141844727614816449371023410985939867234057902831291101652","seed":37896876308310642891141844727614816449371023410985939867234057902831291101652,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  23726228 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  23726228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"6.clkmgr_stress_all_with_rand_reset.109148922582235642378193101675173306767915043364958975002584891199917535345142","seed":109148922582235642378193101675173306767915043364958975002584891199917535345142,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  58625334 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  58625334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"6.clkmgr_stress_all.71818921321618596492789630987950002819956706459150537591646033226049610576578","seed":71818921321618596492789630987950002819956706459150537591646033226049610576578,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  22560470 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  22560470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"7.clkmgr_frequency.10368014055397454092478956657700598841760600831003531645518791098302104131353","seed":10368014055397454092478956657700598841760600831003531645518791098302104131353,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   8041559 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   8041559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"7.clkmgr_stress_all_with_rand_reset.42380650102633706207043888832025269877860943491778810892636034216206544955069","seed":42380650102633706207043888832025269877860943491778810892636034216206544955069,"line":86,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  30617453 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  30617453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"8.clkmgr_frequency.81304632913401740440296131666149848033397427754440840187110842892396342496247","seed":81304632913401740440296131666149848033397427754440840187110842892396342496247,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7027100 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7027100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"8.clkmgr_stress_all.61273991411926367775774670767468596623277685046187374474424249651383871757122","seed":61273991411926367775774670767468596623277685046187374474424249651383871757122,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  10077254 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  10077254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"9.clkmgr_frequency.53379069617609657182941274868366954041463212314682496414124742978281587629461","seed":53379069617609657182941274868366954041463212314682496414124742978281587629461,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6960445 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6960445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"9.clkmgr_stress_all_with_rand_reset.82109079284743597112764032440572061054029614064962340712293785535578538144739","seed":82109079284743597112764032440572061054029614064962340712293785535578538144739,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   4913961 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4913961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"9.clkmgr_stress_all.102000913814968033098358928165855428782957815652519731788934800331541014897705","seed":102000913814968033098358928165855428782957815652519731788934800331541014897705,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  24774492 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  24774492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"10.clkmgr_frequency.94019408401354574726128223623685159267429475006963554439961981354323417567863","seed":94019408401354574726128223623685159267429475006963554439961981354323417567863,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6886210 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6886210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"11.clkmgr_frequency.79463650582603234193197219813816780482810596698123959433278878275535724046508","seed":79463650582603234193197219813816780482810596698123959433278878275535724046508,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6638806 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6638806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"11.clkmgr_stress_all_with_rand_reset.37834636976811184703526768061796253124694621239543498033258128393737716967100","seed":37834636976811184703526768061796253124694621239543498033258128393737716967100,"line":91,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 361741105 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 361741105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"12.clkmgr_frequency.13274771264761304177343164784760697561880963149747357377595205812595951227139","seed":13274771264761304177343164784760697561880963149747357377595205812595951227139,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4870525 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4870525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"12.clkmgr_stress_all_with_rand_reset.10888603244305820545123103369965456725553921357351388474691561373672448190182","seed":10888603244305820545123103369965456725553921357351388474691561373672448190182,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  47781196 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  47781196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"13.clkmgr_frequency.111161063349532641079697768080772126168426038967570075514027819738948967333878","seed":111161063349532641079697768080772126168426038967570075514027819738948967333878,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5761351 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5761351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"13.clkmgr_stress_all.74672710751675811587412264669235434440328870967657133379468748685243564861088","seed":74672710751675811587412264669235434440328870967657133379468748685243564861088,"line":120,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  52408766 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  52408766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"14.clkmgr_frequency.32137664876392516291482669060097507965991998421085761317171087282009086755766","seed":32137664876392516291482669060097507965991998421085761317171087282009086755766,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   8468211 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8468211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"14.clkmgr_stress_all_with_rand_reset.3978342182262372731681733569643339269374983794404309471867923691925125064908","seed":3978342182262372731681733569643339269374983794404309471867923691925125064908,"line":90,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 349883617 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 349883617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"14.clkmgr_stress_all.73739981944703461262503957530617410644858330156667339924902766603430996497506","seed":73739981944703461262503957530617410644858330156667339924902766603430996497506,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  19912834 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  19912834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"15.clkmgr_frequency.77328156990923064095522652717786332233332963709608677175359558363646236389642","seed":77328156990923064095522652717786332233332963709608677175359558363646236389642,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  20086243 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  20086243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"16.clkmgr_frequency.86604769606494167470219489117872379317576422568275836246750250547816130088566","seed":86604769606494167470219489117872379317576422568275836246750250547816130088566,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4390301 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4390301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"16.clkmgr_stress_all_with_rand_reset.36854616786400768871959312769208830310024104046905750525183858563628913558586","seed":36854616786400768871959312769208830310024104046905750525183858563628913558586,"line":209,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 130656704 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 130656704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"17.clkmgr_frequency.38583743983618662923660979541835310552987457823996465606994363204859719054959","seed":38583743983618662923660979541835310552987457823996465606994363204859719054959,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   9578999 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   9578999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"18.clkmgr_frequency.84994684713978762373319766546798677440262973167191784173211969811872007695762","seed":84994684713978762373319766546798677440262973167191784173211969811872007695762,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  15952354 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  15952354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"19.clkmgr_frequency.88654785904271609149261600878454292788166728296480769288831515447619081874818","seed":88654785904271609149261600878454292788166728296480769288831515447619081874818,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   8220066 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8220066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"19.clkmgr_stress_all_with_rand_reset.20161743340735920328407775053880859464653122709743085203876408314632293575257","seed":20161743340735920328407775053880859464653122709743085203876408314632293575257,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  14138411 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  14138411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"20.clkmgr_frequency.23336721264695858757833854827388581948028892514625638623778562780781294106392","seed":23336721264695858757833854827388581948028892514625638623778562780781294106392,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  15672527 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  15672527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"20.clkmgr_stress_all.50379118182516603427969086066891962917646146997028211323695983876755042981715","seed":50379118182516603427969086066891962917646146997028211323695983876755042981715,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  20564048 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  20564048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"21.clkmgr_frequency.21637418288326369804751165501265846989842811174899613429196911826586135544620","seed":21637418288326369804751165501265846989842811174899613429196911826586135544620,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   8007501 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   8007501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"21.clkmgr_stress_all.40458828812035895830118069372206453372973042754641759085683623195758731314831","seed":40458828812035895830118069372206453372973042754641759085683623195758731314831,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   6709668 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6709668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"22.clkmgr_frequency.10508438997520650210095946948318806316472068533492636918673860884204121477245","seed":10508438997520650210095946948318806316472068533492636918673860884204121477245,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  12124491 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  12124491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"22.clkmgr_stress_all.17732427501830834166769383238822108233140359334493983819204299491269927179525","seed":17732427501830834166769383238822108233140359334493983819204299491269927179525,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  31267682 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  31267682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"23.clkmgr_frequency.80863626643804908080143590571213310596379064692388738625251079716134372180377","seed":80863626643804908080143590571213310596379064692388738625251079716134372180377,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5442195 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5442195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"23.clkmgr_stress_all.70395156650286721284931063023200320777761151876287510622570343161006628725581","seed":70395156650286721284931063023200320777761151876287510622570343161006628725581,"line":119,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  48425523 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  48425523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"24.clkmgr_frequency.38279242798257535314896115173901697951028576460515889355652674958048811400186","seed":38279242798257535314896115173901697951028576460515889355652674958048811400186,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   8419905 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   8419905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"24.clkmgr_stress_all.62735338485975442692380624260723816608298606353572874918493883627246757472620","seed":62735338485975442692380624260723816608298606353572874918493883627246757472620,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   8900111 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8900111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"25.clkmgr_frequency.55280576682013906940988266033619511070023471645991989007677072275932103690621","seed":55280576682013906940988266033619511070023471645991989007677072275932103690621,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6976667 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6976667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"25.clkmgr_stress_all_with_rand_reset.23244560690768652596787763191047973077746081608288759219578087703326938293062","seed":23244560690768652596787763191047973077746081608288759219578087703326938293062,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   7692449 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7692449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"26.clkmgr_frequency.84485951910461585281785893096591983721520789290857898469299675077496132554609","seed":84485951910461585281785893096591983721520789290857898469299675077496132554609,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  12824751 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  12824751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"26.clkmgr_stress_all.104069876107652258610706174526950500081525970533449382151403648903163222777940","seed":104069876107652258610706174526950500081525970533449382151403648903163222777940,"line":136,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 105254455 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 105254455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"27.clkmgr_frequency.72053797085719276381035219667096171450703875486178810954199607525102667117953","seed":72053797085719276381035219667096171450703875486178810954199607525102667117953,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4204586 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4204586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"27.clkmgr_stress_all_with_rand_reset.113062328093161215120133971363158240153463989681677188082897644868842422017675","seed":113062328093161215120133971363158240153463989681677188082897644868842422017675,"line":93,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 12909779823 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 12909779823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"28.clkmgr_frequency.53228229678446994678798619910972930618213605553192681156077669607904469847052","seed":53228229678446994678798619910972930618213605553192681156077669607904469847052,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/28.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4668807 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4668807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"28.clkmgr_stress_all_with_rand_reset.115416486428154212080597123620565427557582030826629070916177052441484042608300","seed":115416486428154212080597123620565427557582030826629070916177052441484042608300,"line":223,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/28.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 206593584 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 206593584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"29.clkmgr_frequency.51603403382673409771971849771473476599012397751296720428720988437449939149065","seed":51603403382673409771971849771473476599012397751296720428720988437449939149065,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5614618 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5614618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"29.clkmgr_stress_all_with_rand_reset.52192067929162705220831281114524840642496605637756034161100241322416738953733","seed":52192067929162705220831281114524840642496605637756034161100241322416738953733,"line":154,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  77924789 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  77924789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"30.clkmgr_frequency.74436863474137167286836007531719295752556600243119556767222770596913857210638","seed":74436863474137167286836007531719295752556600243119556767222770596913857210638,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6039683 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6039683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"30.clkmgr_stress_all_with_rand_reset.105446383759141307278578947400858828716301628802671594775146578466447521166614","seed":105446383759141307278578947400858828716301628802671594775146578466447521166614,"line":105,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  43962654 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  43962654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"31.clkmgr_frequency.61191442275032272095504118429629465013804493687637282893123667417547881142737","seed":61191442275032272095504118429629465013804493687637282893123667417547881142737,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   8921646 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8921646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"31.clkmgr_stress_all_with_rand_reset.74809379073596407786628192118782427031713600978114422451131934694719682937952","seed":74809379073596407786628192118782427031713600978114422451131934694719682937952,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 102774560 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 102774560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"31.clkmgr_stress_all.6173846262022037944543992026879939604953402622153297565263046507488304587662","seed":6173846262022037944543992026879939604953402622153297565263046507488304587662,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   4736971 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4736971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"32.clkmgr_frequency.82068293537005643038426254398279992179079249658049147665152339425875104131379","seed":82068293537005643038426254398279992179079249658049147665152339425875104131379,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6306738 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6306738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"32.clkmgr_stress_all_with_rand_reset.33605812701397291794266011258638219285191515086654746805354048837087796594742","seed":33605812701397291794266011258638219285191515086654746805354048837087796594742,"line":108,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  40597739 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  40597739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"32.clkmgr_stress_all.52043198595704083791099832935779683050405166910405761107061522994830964348274","seed":52043198595704083791099832935779683050405166910405761107061522994830964348274,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   8883223 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   8883223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"33.clkmgr_frequency.20332186516795435026936618155334015273466602760071502994926293682522622743469","seed":20332186516795435026936618155334015273466602760071502994926293682522622743469,"line":80,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7114838 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7114838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"33.clkmgr_stress_all_with_rand_reset.74338591306802429227279672754358402950466244095031782581275469381740463604901","seed":74338591306802429227279672754358402950466244095031782581275469381740463604901,"line":81,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  56534690 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  56534690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"34.clkmgr_frequency.30090325747589759043444807863787747657743848393944824822917060558650479450757","seed":30090325747589759043444807863787747657743848393944824822917060558650479450757,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7923849 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7923849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"34.clkmgr_stress_all_with_rand_reset.83181256601163872603656123165695019118600777130581391282259032225507077322853","seed":83181256601163872603656123165695019118600777130581391282259032225507077322853,"line":224,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1520415632 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 1520415632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"35.clkmgr_frequency.70306502085121242902267165175265166818107017216605014872555497742700191277554","seed":70306502085121242902267165175265166818107017216605014872555497742700191277554,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5314574 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5314574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"35.clkmgr_stress_all.77948609782748402324789664802338518400389155216155932624758676333163199363312","seed":77948609782748402324789664802338518400389155216155932624758676333163199363312,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   3807371 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3807371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"36.clkmgr_frequency.70695355346420145853414581938170946491624654920997424810268220310955873669468","seed":70695355346420145853414581938170946491624654920997424810268220310955873669468,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   8221212 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8221212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"37.clkmgr_frequency.6236816980550795471434524297810504246456223761503532373084613096433534282036","seed":6236816980550795471434524297810504246456223761503532373084613096433534282036,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  34906292 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  34906292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"37.clkmgr_stress_all_with_rand_reset.52658740661885887012075935736453426399916827215247953394623880579240861558433","seed":52658740661885887012075935736453426399916827215247953394623880579240861558433,"line":83,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  39085433 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  39085433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"38.clkmgr_frequency.52141834832205344267258195487980239760406937218282879450472535222671569751809","seed":52141834832205344267258195487980239760406937218282879450472535222671569751809,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  13649341 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  13649341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"39.clkmgr_frequency.80003428133259313003752802245823727781918144699908875164464313812957228576337","seed":80003428133259313003752802245823727781918144699908875164464313812957228576337,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5826405 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5826405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"39.clkmgr_stress_all_with_rand_reset.4679452255886369240098362547647842554513138732754469519689846229959921603073","seed":4679452255886369240098362547647842554513138732754469519689846229959921603073,"line":246,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  89868713 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  89868713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"39.clkmgr_stress_all.62061569544794422691942864816507766236908411946853715183894298677074297655065","seed":62061569544794422691942864816507766236908411946853715183894298677074297655065,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   5989005 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5989005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"40.clkmgr_frequency.61006006818851048960199890334744676928077380706060384691870096995611012550202","seed":61006006818851048960199890334744676928077380706060384691870096995611012550202,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6584577 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6584577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"40.clkmgr_stress_all_with_rand_reset.6809988810315564525815629426045804368140771423472001407706471324355147540071","seed":6809988810315564525815629426045804368140771423472001407706471324355147540071,"line":137,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2746779745 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 2746779745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"41.clkmgr_frequency.33307330997288989265973497049011977167665686886206076898391578829960985326853","seed":33307330997288989265973497049011977167665686886206076898391578829960985326853,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   9032126 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   9032126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"41.clkmgr_stress_all_with_rand_reset.42117396211234957396422238324695181773736422516615695100601645254150153392197","seed":42117396211234957396422238324695181773736422516615695100601645254150153392197,"line":223,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 114313101 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 114313101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"41.clkmgr_stress_all.46959028925167840505672639197876990518179061688225846404482330698746514958461","seed":46959028925167840505672639197876990518179061688225846404482330698746514958461,"line":147,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 108215393 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 108215393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"43.clkmgr_frequency.68036794710051107482143763834749932143263742477839892344316805154605405805669","seed":68036794710051107482143763834749932143263742477839892344316805154605405805669,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  24690194 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  24690194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"43.clkmgr_stress_all_with_rand_reset.39934862011397785487225230126983915883764902082199923100705361491903456617413","seed":39934862011397785487225230126983915883764902082199923100705361491903456617413,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   8778854 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   8778854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"43.clkmgr_stress_all.25890847137147350596054168843181705015946681823557313166247673210273544739812","seed":25890847137147350596054168843181705015946681823557313166247673210273544739812,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  12643177 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  12643177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"44.clkmgr_frequency.104527349713520890966500938546747540164934299477304877171040298426426751510477","seed":104527349713520890966500938546747540164934299477304877171040298426426751510477,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5923076 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5923076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"44.clkmgr_stress_all.58782469908688777378230453949884606275903303004229574153068484932859896022310","seed":58782469908688777378230453949884606275903303004229574153068484932859896022310,"line":95,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  54025311 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  54025311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"45.clkmgr_frequency.27364396690631655456010946399326809440662634770970438709052777042828886079277","seed":27364396690631655456010946399326809440662634770970438709052777042828886079277,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   8416875 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8416875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"46.clkmgr_frequency.39322068958007260267278870839880598928572994962879215529088911944382973707251","seed":39322068958007260267278870839880598928572994962879215529088911944382973707251,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6395866 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6395866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"46.clkmgr_stress_all_with_rand_reset.112197593102691794832654587512810547666608830985508587295064247569021067403243","seed":112197593102691794832654587512810547666608830985508587295064247569021067403243,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  20909583 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  20909583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"47.clkmgr_frequency.65286582117442268633222319932613806892393897676176441399647126596921230594261","seed":65286582117442268633222319932613806892393897676176441399647126596921230594261,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  10234393 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  10234393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"47.clkmgr_stress_all.96099442139577062972043626455565000023154340091872503671094963325233738874982","seed":96099442139577062972043626455565000023154340091872503671094963325233738874982,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  55332184 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  55332184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"48.clkmgr_frequency.24852688734576908077526713658060830745651737942422724305661278396327515859081","seed":24852688734576908077526713658060830745651737942422724305661278396327515859081,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7506645 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7506645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"49.clkmgr_frequency.53586272937731269141572494628719415299610993751161589853031239697512807723244","seed":53586272937731269141572494628719415299610993751161589853031239697512807723244,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  12361231 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  12361231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*":[{"name":"clkmgr_frequency_timeout","qual_name":"0.clkmgr_frequency_timeout.101346221007393359417801481456896583264776614347012858493302417907918340054815","seed":101346221007393359417801481456896583264776614347012858493302417907918340054815,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   8170440 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8170440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"0.clkmgr_stress_all.111288260441729020172959851243198659723148997956723466134280035808454039425254","seed":111288260441729020172959851243198659723148997956723466134280035808454039425254,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   6254305 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6254305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"1.clkmgr_frequency_timeout.85784743845403859397351839866315361584079998248010686260342439135080387511330","seed":85784743845403859397351839866315361584079998248010686260342439135080387511330,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   7551411 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7551411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"2.clkmgr_frequency_timeout.20553725306500223160873711172828083217669837326205374163461327652705668447324","seed":20553725306500223160873711172828083217669837326205374163461327652705668447324,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6702186 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6702186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"3.clkmgr_frequency_timeout.3638225117739527387245998098669073325866293142145495677355138480406327091893","seed":3638225117739527387245998098669073325866293142145495677355138480406327091893,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @  10708123 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  10708123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"4.clkmgr_frequency_timeout.17203966807551699710710668762680829718594289148779782435994461949240984833865","seed":17203966807551699710710668762680829718594289148779782435994461949240984833865,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @  13987920 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  13987920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"4.clkmgr_stress_all.114722515725805421388753757620142606503437177010422024375036176708866602486456","seed":114722515725805421388753757620142606503437177010422024375036176708866602486456,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  28882249 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  28882249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"5.clkmgr_frequency_timeout.57914467866621244711577033573544666471396683164328905184314351529828280364829","seed":57914467866621244711577033573544666471396683164328905184314351529828280364829,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5346157 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5346157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"5.clkmgr_stress_all_with_rand_reset.93825362493370013035278997374929661498571776240237198527897371100709101403562","seed":93825362493370013035278997374929661498571776240237198527897371100709101403562,"line":131,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  48301026 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  48301026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"5.clkmgr_stress_all.81522056846788223404949846177606565853139523286190947145752276066616423182248","seed":81522056846788223404949846177606565853139523286190947145752276066616423182248,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  13031278 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  13031278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"6.clkmgr_frequency_timeout.101337422145763138927362102326376471522274149367958888676817039746754167765721","seed":101337422145763138927362102326376471522274149367958888676817039746754167765721,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4088995 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4088995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"7.clkmgr_frequency_timeout.10325747225455018683134973612370523339096155422792937997386549165553570219352","seed":10325747225455018683134973612370523339096155422792937997386549165553570219352,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3492859 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3492859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"7.clkmgr_stress_all.83970679293446689514674608423624198109834098874067595127345216233357382411235","seed":83970679293446689514674608423624198109834098874067595127345216233357382411235,"line":189,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 138897913 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 138897913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"8.clkmgr_frequency_timeout.34671029373185984095221529515792524055440586005646576244999159463813325662899","seed":34671029373185984095221529515792524055440586005646576244999159463813325662899,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   7653656 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7653656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"8.clkmgr_stress_all_with_rand_reset.44678849268144331297723220433152448566169249015817626173834402146153148653176","seed":44678849268144331297723220433152448566169249015817626173834402146153148653176,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   3512707 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3512707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"9.clkmgr_frequency_timeout.85112497201872272571069415076814913113168218151449866098514345558019241468886","seed":85112497201872272571069415076814913113168218151449866098514345558019241468886,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3798659 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3798659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"10.clkmgr_frequency_timeout.37673141777205406762307331685877386062998049414545936957974427630911829007212","seed":37673141777205406762307331685877386062998049414545936957974427630911829007212,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @  12488939 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  12488939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"10.clkmgr_stress_all_with_rand_reset.46879211905543669024108319798090096262865676496964864521885503380213634789134","seed":46879211905543669024108319798090096262865676496964864521885503380213634789134,"line":128,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  69489713 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  69489713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"10.clkmgr_stress_all.67853020598037954424074836021673199726525663882961823738357145587233795018648","seed":67853020598037954424074836021673199726525663882961823738357145587233795018648,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  16048759 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  16048759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"11.clkmgr_frequency_timeout.40652621076486553481473943722672531232076114290967398826589660726344473719937","seed":40652621076486553481473943722672531232076114290967398826589660726344473719937,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3194699 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3194699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"11.clkmgr_stress_all.4127756532714419972997743451861625115527470251930030995957890788361617782338","seed":4127756532714419972997743451861625115527470251930030995957890788361617782338,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   6264968 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6264968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"12.clkmgr_frequency_timeout.93426012702965042354272933942238238604067511766434920083374309310160088177410","seed":93426012702965042354272933942238238604067511766434920083374309310160088177410,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   7615135 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7615135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"12.clkmgr_stress_all.97337853346891027807446525977585578526665959278843527110490381682923656700619","seed":97337853346891027807446525977585578526665959278843527110490381682923656700619,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  29790555 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  29790555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"13.clkmgr_frequency_timeout.81927594665372569548356652932436187748560969434557561343850693235060502383687","seed":81927594665372569548356652932436187748560969434557561343850693235060502383687,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3042744 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3042744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"13.clkmgr_stress_all_with_rand_reset.52244788950395123869853281379447703395750180524816143752692737525886048978847","seed":52244788950395123869853281379447703395750180524816143752692737525886048978847,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  10565272 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  10565272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"14.clkmgr_frequency_timeout.66926098683492930535886595013840698087312622683567306408396057818154061477888","seed":66926098683492930535886595013840698087312622683567306408396057818154061477888,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5326142 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5326142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"15.clkmgr_frequency_timeout.40411628175527488452864034378686010253138788498937659883120632990621505686308","seed":40411628175527488452864034378686010253138788498937659883120632990621505686308,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @  10396719 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  10396719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"15.clkmgr_stress_all_with_rand_reset.384065496383166330658305156308988316034499885675232524744792371252231615631","seed":384065496383166330658305156308988316034499885675232524744792371252231615631,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  96471932 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  96471932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"15.clkmgr_stress_all.86477981413326819749622847375922940922566161959097605056482012415479169302406","seed":86477981413326819749622847375922940922566161959097605056482012415479169302406,"line":134,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  43042113 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  43042113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"16.clkmgr_frequency_timeout.34837948339578528653073591485359774492534766493067529515007286667054280609454","seed":34837948339578528653073591485359774492534766493067529515007286667054280609454,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3431348 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3431348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"16.clkmgr_stress_all.100200622550619759273199802550279894858861116890302520201750724234459781334332","seed":100200622550619759273199802550279894858861116890302520201750724234459781334332,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  57240735 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  57240735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"17.clkmgr_frequency_timeout.22104215480381762773871419369058776502404019030602162869386728197283804368995","seed":22104215480381762773871419369058776502404019030602162869386728197283804368995,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5738145 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5738145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"17.clkmgr_stress_all_with_rand_reset.87844417064181930642394327675185914325919066693034754084006004058448200651230","seed":87844417064181930642394327675185914325919066693034754084006004058448200651230,"line":85,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  16859096 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  16859096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"17.clkmgr_stress_all.101750994737442848720215388005298575610818041963494762516599473225923725315760","seed":101750994737442848720215388005298575610818041963494762516599473225923725315760,"line":142,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 129872165 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 129872165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"18.clkmgr_frequency_timeout.38660909646788591561564338706115054649737026071707213498384313557835419200709","seed":38660909646788591561564338706115054649737026071707213498384313557835419200709,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @  12636308 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  12636308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"18.clkmgr_stress_all_with_rand_reset.30140372645445639823025016405388778411895477762648180290944867023680211868341","seed":30140372645445639823025016405388778411895477762648180290944867023680211868341,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  44634289 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  44634289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"18.clkmgr_stress_all.107853611046377839527305495810920846256897665006183990341082720155555475676672","seed":107853611046377839527305495810920846256897665006183990341082720155555475676672,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   7276306 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7276306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"19.clkmgr_frequency_timeout.81898300523118319700982816668199403613903510319880857191488135835472848285604","seed":81898300523118319700982816668199403613903510319880857191488135835472848285604,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @  12715699 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  12715699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"19.clkmgr_stress_all.88348373894023180934110626636842467625659962092803268759741607154421023656137","seed":88348373894023180934110626636842467625659962092803268759741607154421023656137,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   4040391 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4040391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"20.clkmgr_frequency_timeout.110076483529489098870907691784923100202592974454214270218154528112888293921502","seed":110076483529489098870907691784923100202592974454214270218154528112888293921502,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3535843 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3535843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"20.clkmgr_stress_all_with_rand_reset.5929374434953652392631967631151833613576767924660559242767136632948525377292","seed":5929374434953652392631967631151833613576767924660559242767136632948525377292,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  37856326 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  37856326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"21.clkmgr_frequency_timeout.43834982379268249121343332822270103119010628615812068704188709475151438933541","seed":43834982379268249121343332822270103119010628615812068704188709475151438933541,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3118660 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3118660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"21.clkmgr_stress_all_with_rand_reset.1718185014075560630114724557036932235543567357156383104471433583393415750469","seed":1718185014075560630114724557036932235543567357156383104471433583393415750469,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   6404151 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6404151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"22.clkmgr_frequency_timeout.28019666892424659493327941177406102100860492083736566792513888244431690890466","seed":28019666892424659493327941177406102100860492083736566792513888244431690890466,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2942599 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2942599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"22.clkmgr_stress_all_with_rand_reset.103196701487566388055091279066220059447343208256429287337839326289874627857624","seed":103196701487566388055091279066220059447343208256429287337839326289874627857624,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  77927994 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  77927994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"23.clkmgr_frequency_timeout.19327090837705505364000769972832405105478804486944106860862063535174520115325","seed":19327090837705505364000769972832405105478804486944106860862063535174520115325,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3442175 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3442175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"23.clkmgr_stress_all_with_rand_reset.73416437140232596657061665443499560817422933122400656492027377178979891384189","seed":73416437140232596657061665443499560817422933122400656492027377178979891384189,"line":113,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 467109100 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 467109100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"24.clkmgr_frequency_timeout.32316580848637723194756441862218232063395449102329015723353887352457861014121","seed":32316580848637723194756441862218232063395449102329015723353887352457861014121,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2752476 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2752476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"24.clkmgr_stress_all_with_rand_reset.90977915928799493962216244090388776056067204298695527125756094400157891394466","seed":90977915928799493962216244090388776056067204298695527125756094400157891394466,"line":90,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2562393389 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 2562393389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"25.clkmgr_frequency_timeout.17735222773882266020880888417011047748522024196211552067942394073508117950761","seed":17735222773882266020880888417011047748522024196211552067942394073508117950761,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   9249544 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   9249544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"26.clkmgr_frequency_timeout.3819592133675648466738174427629427834956630582595273052608136619397570418870","seed":3819592133675648466738174427629427834956630582595273052608136619397570418870,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6945541 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6945541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"26.clkmgr_stress_all_with_rand_reset.2348928697551780494883304029747415331643914908221188466038783942255709168649","seed":2348928697551780494883304029747415331643914908221188466038783942255709168649,"line":86,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  29062618 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  29062618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"27.clkmgr_frequency_timeout.48833520997890345350794616928632240549470643244843920781744992389871432835628","seed":48833520997890345350794616928632240549470643244843920781744992389871432835628,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   1429274 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   1429274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"27.clkmgr_stress_all.10207505328867552838136951837692136655249063354901690537683151098132158642238","seed":10207505328867552838136951837692136655249063354901690537683151098132158642238,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  19608298 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  19608298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"28.clkmgr_frequency_timeout.82456770090195441687212495643922808707708826946328979166943392711892779092481","seed":82456770090195441687212495643922808707708826946328979166943392711892779092481,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/28.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6930667 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6930667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"28.clkmgr_stress_all.72858819915575338147273110261347746127477056794623408019740210768776128113811","seed":72858819915575338147273110261347746127477056794623408019740210768776128113811,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/28.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   7754873 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7754873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"29.clkmgr_frequency_timeout.99900016816265629520433807743708664316672904682229017763352030887735914441467","seed":99900016816265629520433807743708664316672904682229017763352030887735914441467,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @  14350064 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  14350064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"29.clkmgr_stress_all.13854439038577522913402883035107560463799404527164793110095832501105568212452","seed":13854439038577522913402883035107560463799404527164793110095832501105568212452,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   2376497 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2376497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"30.clkmgr_frequency_timeout.62671957918258313305094412922608057631675923732534206306841181263984591612416","seed":62671957918258313305094412922608057631675923732534206306841181263984591612416,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3189710 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3189710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"30.clkmgr_stress_all.113583033396825262519839486382718181114650482437007316705236107212697216895979","seed":113583033396825262519839486382718181114650482437007316705236107212697216895979,"line":141,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 203139064 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 203139064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"31.clkmgr_frequency_timeout.45029620222353202579097094398628338430308635000286661207822520721116044232862","seed":45029620222353202579097094398628338430308635000286661207822520721116044232862,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2608920 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2608920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"32.clkmgr_frequency_timeout.102433229985461721154898453578809893619641576777877217325318519967998191144952","seed":102433229985461721154898453578809893619641576777877217325318519967998191144952,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6805026 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6805026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"33.clkmgr_frequency_timeout.49999497782898621922231505858495911051928729858967591237277945285566741250331","seed":49999497782898621922231505858495911051928729858967591237277945285566741250331,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5002641 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5002641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"34.clkmgr_frequency_timeout.60802404965443120721299389402673191510735075422016457458927575279601197453025","seed":60802404965443120721299389402673191510735075422016457458927575279601197453025,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5622378 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5622378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"34.clkmgr_stress_all.86737589702938722783446066263638201724974684193149612090061507834658760846774","seed":86737589702938722783446066263638201724974684193149612090061507834658760846774,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  76582610 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  76582610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"35.clkmgr_frequency_timeout.10016413696396000019505422463135735082511421845859357699336591667909072554785","seed":10016413696396000019505422463135735082511421845859357699336591667909072554785,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2015187 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2015187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"35.clkmgr_stress_all_with_rand_reset.88286604471374800906283223379118576751325464948667588832316348451995870754019","seed":88286604471374800906283223379118576751325464948667588832316348451995870754019,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   4369053 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4369053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"36.clkmgr_frequency_timeout.41560281016557834371027813586453576556888799458265377530032515607979190680197","seed":41560281016557834371027813586453576556888799458265377530032515607979190680197,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3046280 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3046280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"36.clkmgr_stress_all_with_rand_reset.106094511542722192968789798505205270055068891990550870609829856306265576755471","seed":106094511542722192968789798505205270055068891990550870609829856306265576755471,"line":160,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 881970079 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 881970079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"36.clkmgr_stress_all.43293354716520099031981341519631215775510735480083219349024826330829685768043","seed":43293354716520099031981341519631215775510735480083219349024826330829685768043,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  36256260 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  36256260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"37.clkmgr_frequency_timeout.25005342946634130322225619600114359777080402092960023669473105308177385807287","seed":25005342946634130322225619600114359777080402092960023669473105308177385807287,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2898121 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2898121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"37.clkmgr_stress_all.111566569587179200027729606893674004888826063767546263126392172495324990018410","seed":111566569587179200027729606893674004888826063767546263126392172495324990018410,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  41398307 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  41398307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"38.clkmgr_frequency_timeout.74787566678641878276087837133319554388497334493666936921651111914797529763699","seed":74787566678641878276087837133319554388497334493666936921651111914797529763699,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @  16067274 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  16067274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"38.clkmgr_stress_all_with_rand_reset.86094246600357769633521677207642240205837423360455859835512071232095561893702","seed":86094246600357769633521677207642240205837423360455859835512071232095561893702,"line":87,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  17980217 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  17980217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"38.clkmgr_stress_all.26046697947365111439852314871533732734236814621665978750253776553725571776269","seed":26046697947365111439852314871533732734236814621665978750253776553725571776269,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 110160813 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 110160813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"39.clkmgr_frequency_timeout.23378409362317706142754593594024336916583612670329147173800539308809839486402","seed":23378409362317706142754593594024336916583612670329147173800539308809839486402,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2331723 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2331723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"40.clkmgr_frequency_timeout.98601748197614357448206834531227368636766097998521869744527170473286741137233","seed":98601748197614357448206834531227368636766097998521869744527170473286741137233,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5342709 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5342709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"40.clkmgr_stress_all.85699519313067059429624659368509433957854446901711219140046466607809017209561","seed":85699519313067059429624659368509433957854446901711219140046466607809017209561,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   3397819 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3397819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"41.clkmgr_frequency_timeout.69614757081734420138414950562749421131705167865833223156533998940883608394925","seed":69614757081734420138414950562749421131705167865833223156533998940883608394925,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4600947 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4600947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"42.clkmgr_frequency_timeout.72168109357367592886399460070337128539380073370368157902731710435146721126090","seed":72168109357367592886399460070337128539380073370368157902731710435146721126090,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4486146 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4486146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"42.clkmgr_stress_all_with_rand_reset.10514153377078522813187130204091818058112270262011310072878818688160417758445","seed":10514153377078522813187130204091818058112270262011310072878818688160417758445,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   2695956 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2695956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"42.clkmgr_stress_all.35336585940474244623396584645062336425582862701182191552614208493265269990763","seed":35336585940474244623396584645062336425582862701182191552614208493265269990763,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  36745916 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  36745916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"43.clkmgr_frequency_timeout.21183092102309621797407603494976374983680797258747203825201194674203976346213","seed":21183092102309621797407603494976374983680797258747203825201194674203976346213,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4324990 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4324990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"44.clkmgr_frequency_timeout.92978266972608242407777314549709766257964140456337920098856612354130442104202","seed":92978266972608242407777314549709766257964140456337920098856612354130442104202,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3098277 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3098277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"44.clkmgr_stress_all_with_rand_reset.609141812003553078911402080545641295275898640712458000366518410254365938787","seed":609141812003553078911402080545641295275898640712458000366518410254365938787,"line":157,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  56785518 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  56785518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"45.clkmgr_frequency_timeout.58828651558207253700545195612679221637965181622808721494271305391296072131382","seed":58828651558207253700545195612679221637965181622808721494271305391296072131382,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3846646 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3846646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"45.clkmgr_stress_all_with_rand_reset.100531022485354634177971323851111893097650520132417830218739457146806341337628","seed":100531022485354634177971323851111893097650520132417830218739457146806341337628,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  26094280 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  26094280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"45.clkmgr_stress_all.106858483044914676712049144989961646838740672043396509508694900480621378221530","seed":106858483044914676712049144989961646838740672043396509508694900480621378221530,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  13193511 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  13193511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"46.clkmgr_frequency_timeout.110846137406665884126729053589226534847563934453550645190553326164269702683275","seed":110846137406665884126729053589226534847563934453550645190553326164269702683275,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   7045454 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7045454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"46.clkmgr_stress_all.68110570856325587270528090263756907931271195794207185625737591947356721587265","seed":68110570856325587270528090263756907931271195794207185625737591947356721587265,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   4874328 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4874328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"47.clkmgr_frequency_timeout.66617237417593613596305508064064609971361051504909539615505933780276546167477","seed":66617237417593613596305508064064609971361051504909539615505933780276546167477,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6730645 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6730645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"47.clkmgr_stress_all_with_rand_reset.29475812576911532652683572732639534330446249145016211450633397818351033578779","seed":29475812576911532652683572732639534330446249145016211450633397818351033578779,"line":193,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 305751371 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 305751371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"48.clkmgr_frequency_timeout.105328464884608018843829072641163399466888441922452783031802025259626352412419","seed":105328464884608018843829072641163399466888441922452783031802025259626352412419,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2572241 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2572241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"48.clkmgr_stress_all_with_rand_reset.50966401472613662381402688045648270540415172651180080887242059746381230701750","seed":50966401472613662381402688045648270540415172651180080887242059746381230701750,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 255827749 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 255827749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"49.clkmgr_frequency_timeout.109487435393071632087334697645077380718617230441702143728206747966224521618349","seed":109487435393071632087334697645077380718617230441702143728206747966224521618349,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3941801 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3941801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"49.clkmgr_stress_all_with_rand_reset.95793787821916383764643928616780522942477649747719057969106714271832470009770","seed":95793787821916383764643928616780522942477649747719057969106714271832470009770,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   4445610 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4445610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"49.clkmgr_stress_all.40356437436319011375900792941327768632008658284786104571949142609813505580189","seed":40356437436319011375900792941327768632008658284786104571949142609813505580189,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   9718373 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   9718373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.main_meas_ctrl_en":[{"name":"clkmgr_regwen","qual_name":"0.clkmgr_regwen.17641437333965889032261081169351854702051065165087221073701306446258693710882","seed":17641437333965889032261081169351854702051065165087221073701306446258693710882,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4755582 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @   4755582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"8.clkmgr_regwen.88433059040513929425702617713916610804466405414958665105461432528134485371051","seed":88433059040513929425702617713916610804466405414958665105461432528134485371051,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6218419 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @   6218419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"10.clkmgr_regwen.25412117990686061116288556318283966177912493144279512250047194286967772888937","seed":25412117990686061116288556318283966177912493144279512250047194286967772888937,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4170129 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @   4170129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"35.clkmgr_regwen.45538998852895743375207286404153052822726696645357095031050986899474335741891","seed":45538998852895743375207286404153052822726696645357095031050986899474335741891,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  15922355 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @  15922355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"38.clkmgr_regwen.19097415345151456642669683151140215085774901312207915997834717140157051524496","seed":19097415345151456642669683151140215085774901312207915997834717140157051524496,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   9977118 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @   9977118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire":[{"name":"clkmgr_sec_cm","qual_name":"0.clkmgr_sec_cm.51140378043372244831328010449897283396379875325851080280867357864768582481770","seed":51140378043372244831328010449897283396379875325851080280867357864768582481770,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_sec_cm/latest/run.log","log_context":["UVM_ERROR @   6964794 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire\n","UVM_INFO @   6964794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_sec_cm","qual_name":"4.clkmgr_sec_cm.67682166090268586611826721396034301700557791885748139428418795775277036989427","seed":67682166090268586611826721396034301700557791885748139428418795775277036989427,"line":169,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_sec_cm/latest/run.log","log_context":["UVM_ERROR @  96068174 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire\n","UVM_INFO @  96068174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en":[{"name":"clkmgr_regwen","qual_name":"1.clkmgr_regwen.15795859051802302063117231863465431356089193496340980038801841230731868193501","seed":15795859051802302063117231863465431356089193496340980038801841230731868193501,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2283491 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 3 [0x3]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2283491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"2.clkmgr_regwen.56506827310837034783695063542737081715144964668016091909710550454356413675840","seed":56506827310837034783695063542737081715144964668016091909710550454356413675840,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   7592300 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (13 [0xd] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   7592300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"3.clkmgr_regwen.111103428006975988432332552971288429979662196504456743324398329951213882691180","seed":111103428006975988432332552971288429979662196504456743324398329951213882691180,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   7902364 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   7902364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"4.clkmgr_regwen.57834019145252435403344852465919973782304041112184653947097607291081939694974","seed":57834019145252435403344852465919973782304041112184653947097607291081939694974,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5138004 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   5138004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"6.clkmgr_regwen.57839108984688005659734208073900180126917137938522784076464653947605142266465","seed":57839108984688005659734208073900180126917137938522784076464653947605142266465,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2108215 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2108215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"9.clkmgr_regwen.100379164493694553751345375905616109041216515777592069317925035711801103702590","seed":100379164493694553751345375905616109041216515777592069317925035711801103702590,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   9505602 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   9505602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"12.clkmgr_regwen.39806948484692126679138571250901141027198594392379103779242219902705636719873","seed":39806948484692126679138571250901141027198594392379103779242219902705636719873,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4179038 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   4179038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"13.clkmgr_regwen.45775945130865797117696054881213951857024262385120720968085316205419349423592","seed":45775945130865797117696054881213951857024262385120720968085316205419349423592,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3431598 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 13 [0xd]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3431598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"15.clkmgr_regwen.35252439759198545050338323703607254762664587675050114127779135134432178711856","seed":35252439759198545050338323703607254762664587675050114127779135134432178711856,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   9300426 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   9300426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"18.clkmgr_regwen.29447999434567225850057484189922352352103866821432895561210216990514886172695","seed":29447999434567225850057484189922352352103866821432895561210216990514886172695,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6906727 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 15 [0xf]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   6906727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"19.clkmgr_regwen.93639547019592146080427238322231547025327783155811937434405645494510451138654","seed":93639547019592146080427238322231547025327783155811937434405645494510451138654,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4588711 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 12 [0xc]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   4588711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"20.clkmgr_regwen.38226767589855812176744702942298616362734344732803088701000849832592444285127","seed":38226767589855812176744702942298616362734344732803088701000849832592444285127,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2379470 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 12 [0xc]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2379470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"22.clkmgr_regwen.32324018531868593831746906058216666039237498819155133939890073325361043934539","seed":32324018531868593831746906058216666039237498819155133939890073325361043934539,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3517958 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3517958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"23.clkmgr_regwen.76527003797012870728044901616969675851161399419500407738547596849846781079327","seed":76527003797012870728044901616969675851161399419500407738547596849846781079327,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   9197992 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   9197992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"24.clkmgr_regwen.76847942226301142317060827357801527472553097115870601884273856928258509732693","seed":76847942226301142317060827357801527472553097115870601884273856928258509732693,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   8671196 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 15 [0xf]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   8671196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"26.clkmgr_regwen.80820532390066149548021368389933147202330176574971468742749534785299244950922","seed":80820532390066149548021368389933147202330176574971468742749534785299244950922,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   7749812 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   7749812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"27.clkmgr_regwen.77182290309621459882669390591822920100673918662277576567338542739450667919195","seed":77182290309621459882669390591822920100673918662277576567338542739450667919195,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2715686 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2715686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"28.clkmgr_regwen.3946219476019218662778954507587313645678199094448672531254750940805708347263","seed":3946219476019218662778954507587313645678199094448672531254750940805708347263,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/28.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2337867 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2337867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"30.clkmgr_regwen.2574786070696222253802546242216414050328617419481379785535656725368766393349","seed":2574786070696222253802546242216414050328617419481379785535656725368766393349,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  16065723 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (15 [0xf] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @  16065723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"32.clkmgr_regwen.90823413140512193899108634029944008672978661059479594414140842002627770279081","seed":90823413140512193899108634029944008672978661059479594414140842002627770279081,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5196857 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (10 [0xa] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   5196857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"33.clkmgr_regwen.43524080301412912385033272650351608127404967092359518684938936354674734188171","seed":43524080301412912385033272650351608127404967092359518684938936354674734188171,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2428670 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2428670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"34.clkmgr_regwen.87320132398889422266637862654306789084734622532686784797728455878329125786273","seed":87320132398889422266637862654306789084734622532686784797728455878329125786273,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   9498245 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   9498245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"36.clkmgr_regwen.113618381650336539711203300605151928441368435211476125543720249575629208945280","seed":113618381650336539711203300605151928441368435211476125543720249575629208945280,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  12556930 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 15 [0xf]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @  12556930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"39.clkmgr_regwen.73484034328701306941585600103503844105291197893771972009507020284777990755401","seed":73484034328701306941585600103503844105291197893771972009507020284777990755401,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2116467 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 11 [0xb]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2116467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"43.clkmgr_regwen.47552575285539692728157035164847507788218799201929653161861353927128610086474","seed":47552575285539692728157035164847507788218799201929653161861353927128610086474,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5502374 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   5502374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"44.clkmgr_regwen.91926820045771701751959515676892351472259993266811188631666178685378511367154","seed":91926820045771701751959515676892351472259993266811188631666178685378511367154,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6011226 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   6011226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"45.clkmgr_regwen.78646166525903578404890698767743009319511909816488207162503177202609783849808","seed":78646166525903578404890698767743009319511909816488207162503177202609783849808,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   1622889 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   1622889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"46.clkmgr_regwen.46810016621129902041941768097462773273559163576498040938384344356766145675424","seed":46810016621129902041941768097462773273559163576498040938384344356766145675424,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  22893306 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @  22893306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"49.clkmgr_regwen.27655648031541035253223542208276189911475691736523987026400316189612412970572","seed":27655648031541035253223542208276189911475691736523987026400316189612412970572,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6284504 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   6284504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed":[{"name":"clkmgr_regwen","qual_name":"5.clkmgr_regwen.64429093282610654987121770609000629152924758877595813123569728313025575136357","seed":64429093282610654987121770609000629152924758877595813123569728313025575136357,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3948803 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   3948803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"7.clkmgr_regwen.106894885412865512153037590041986869786288498362042754896764548847800154174076","seed":106894885412865512153037590041986869786288498362042754896764548847800154174076,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6986011 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   6986011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"11.clkmgr_regwen.80849018201981071115812914951976275907157756154902637878117767162685820412784","seed":80849018201981071115812914951976275907157756154902637878117767162685820412784,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   7931763 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   7931763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"16.clkmgr_regwen.58924443488433686096473608442048996790463910200864547550698941174792137607916","seed":58924443488433686096473608442048996790463910200864547550698941174792137607916,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6492959 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   6492959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"17.clkmgr_regwen.113165643336819187361207810942175469084089720714512350389398393687758652760247","seed":113165643336819187361207810942175469084089720714512350389398393687758652760247,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  11173521 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @  11173521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"21.clkmgr_regwen.75937387333946900185232835559835004484673873444374925817457867655170618206099","seed":75937387333946900185232835559835004484673873444374925817457867655170618206099,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4156100 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   4156100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"25.clkmgr_regwen.111774067299102111548869266841232029711863657428269928035468600460690561354084","seed":111774067299102111548869266841232029711863657428269928035468600460690561354084,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6643710 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   6643710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"31.clkmgr_regwen.110715636347774137204510111671364475909960181834915889988362490477898074065756","seed":110715636347774137204510111671364475909960181834915889988362490477898074065756,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4558215 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   4558215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"37.clkmgr_regwen.112405536782710786933993870094051804041377058333911884865846905180994979855902","seed":112405536782710786933993870094051804041377058333911884865846905180994979855902,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4482872 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   4482872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"40.clkmgr_regwen.4998880894854594435850359501577514178142877667498061109218363777700367887495","seed":4998880894854594435850359501577514178142877667498061109218363777700367887495,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5214935 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   5214935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"41.clkmgr_regwen.92053054164053251459659943435760003589900935875909323931217005329290261678961","seed":92053054164053251459659943435760003589900935875909323931217005329290261678961,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2986911 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   2986911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"42.clkmgr_regwen.113309548489065581068322133600514095412439481687105356122263444510248871682855","seed":113309548489065581068322133600514095412439481687105356122263444510248871682855,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4770561 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   4770561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"47.clkmgr_regwen.114076555249882538238083517481846119884378358964110693651153787246774211579944","seed":114076555249882538238083517481846119884378358964110693651153787246774211579944,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   7388363 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   7388363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"48.clkmgr_regwen.59203267039827728479601060165964355990114662521646198669317567847454113439745","seed":59203267039827728479601060165964355990114662521646198669317567847454113439745,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   7597986 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   7597986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *":[{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"0.clkmgr_shadow_reg_errors_with_csr_rw.103674303300099125129755334761732386017765053360939907231397677175358062723635","seed":103674303300099125129755334761732386017765053360939907231397677175358062723635,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3257548 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   3257548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"0.clkmgr_tl_intg_err.99130719493465130813432334574194406809730902029987033428142116027968447631238","seed":99130719493465130813432334574194406809730902029987033428142116027968447631238,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  15083669 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  15083669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_aliasing","qual_name":"0.clkmgr_csr_aliasing.22927967029741417368640149748765247650013930462640179168479756927609171038693","seed":22927967029741417368640149748765247650013930462640179168479756927609171038693,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_aliasing/latest/run.log","log_context":["UVM_ERROR @   5996684 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   5996684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"0.clkmgr_csr_mem_rw_with_rand_reset.85440941258167117016982303975865838102026629931676535743308348765257216758638","seed":85440941258167117016982303975865838102026629931676535743308348765257216758638,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  63991613 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  63991613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"1.clkmgr_shadow_reg_errors_with_csr_rw.63322885996574293997815013430155077659742749038010800248955581155549277062896","seed":63322885996574293997815013430155077659742749038010800248955581155549277062896,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  18576310 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  18576310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"1.clkmgr_tl_intg_err.97987821592454941664572001063081665164823226479099103130374682693076343267019","seed":97987821592454941664572001063081665164823226479099103130374682693076343267019,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   1412285 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   1412285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"2.clkmgr_shadow_reg_errors_with_csr_rw.78921836557046715432471145206185954002601234223366117123626771982033150209706","seed":78921836557046715432471145206185954002601234223366117123626771982033150209706,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3940440 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   3940440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"2.clkmgr_tl_intg_err.45628881830335183534560575695016680234169100694011111807855036510582314753303","seed":45628881830335183534560575695016680234169100694011111807855036510582314753303,"line":101,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  26127119 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  26127119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_aliasing","qual_name":"2.clkmgr_csr_aliasing.92891003668309946038186832496646071476889975672181031800321262955316494277357","seed":92891003668309946038186832496646071476889975672181031800321262955316494277357,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_csr_aliasing/latest/run.log","log_context":["UVM_ERROR @   7045320 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   7045320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"3.clkmgr_shadow_reg_errors_with_csr_rw.48982341492063925355719842015762021020116864244058992308764137616290894657939","seed":48982341492063925355719842015762021020116864244058992308764137616290894657939,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   4357336 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   4357336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"3.clkmgr_tl_intg_err.108974879466853706755854351121330694804768136670749044860207237054554147219408","seed":108974879466853706755854351121330694804768136670749044860207237054554147219408,"line":83,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  17255419 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  17255419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_aliasing","qual_name":"3.clkmgr_csr_aliasing.60286834931325444115534518861948348625741256854223172972073110415736874992694","seed":60286834931325444115534518861948348625741256854223172972073110415736874992694,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_csr_aliasing/latest/run.log","log_context":["UVM_ERROR @   4872700 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   4872700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"3.clkmgr_csr_mem_rw_with_rand_reset.52937782967882002044094351904630997276066878079955793495416078745244637781192","seed":52937782967882002044094351904630997276066878079955793495416078745244637781192,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  42940533 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  42940533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"4.clkmgr_tl_intg_err.46893015437347039690912297802320412979461556984811361483462320905504855161880","seed":46893015437347039690912297802320412979461556984811361483462320905504855161880,"line":117,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  25241584 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  25241584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"4.clkmgr_csr_rw.13107012557709715944680984502383497181768926531151785433800850556312178359390","seed":13107012557709715944680984502383497181768926531151785433800850556312178359390,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @  13582428 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  13582428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"5.clkmgr_shadow_reg_errors_with_csr_rw.110928165249079473554012798188872287432407293239407542721389201193089389292283","seed":110928165249079473554012798188872287432407293239407542721389201193089389292283,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  17894449 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  17894449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"5.clkmgr_csr_rw.52214148286458305873714349142777137081114842922504360637085393263752687504958","seed":52214148286458305873714349142777137081114842922504360637085393263752687504958,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   1805577 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   1805577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"5.clkmgr_csr_mem_rw_with_rand_reset.104235350984838088781869315767599230384849835911475164346422597977966775104596","seed":104235350984838088781869315767599230384849835911475164346422597977966775104596,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  47464048 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  47464048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"6.clkmgr_shadow_reg_errors_with_csr_rw.26266739966770192536891416449362101781951116643791774924712261375293337444672","seed":26266739966770192536891416449362101781951116643791774924712261375293337444672,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   5468669 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   5468669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"6.clkmgr_csr_rw.16421652429029004934308924533498770778997710130413468794526615172209141901961","seed":16421652429029004934308924533498770778997710130413468794526615172209141901961,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   4198544 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   4198544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"6.clkmgr_csr_mem_rw_with_rand_reset.86861336603549505103989585607323701300418312678496680322336970825235810859441","seed":86861336603549505103989585607323701300418312678496680322336970825235810859441,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  41337263 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  41337263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"7.clkmgr_tl_intg_err.106976592089406272014719040058013126834525416187450063263943458996844224001846","seed":106976592089406272014719040058013126834525416187450063263943458996844224001846,"line":98,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  30989101 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  30989101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"9.clkmgr_shadow_reg_errors_with_csr_rw.108136973820533641301285057327967086530023741977104531174975251176155490194234","seed":108136973820533641301285057327967086530023741977104531174975251176155490194234,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2959213 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   2959213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"9.clkmgr_tl_intg_err.20648412654455750411562848968507873887155965799922690060311232448898980896841","seed":20648412654455750411562848968507873887155965799922690060311232448898980896841,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   1801968 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   1801968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"9.clkmgr_csr_rw.101797370676189317027476631060565839663239738478344514861307546496127164990587","seed":101797370676189317027476631060565839663239738478344514861307546496127164990587,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3008683 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   3008683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"9.clkmgr_csr_mem_rw_with_rand_reset.10234568790964402371052437937672841248499587971820438883924752373877794868883","seed":10234568790964402371052437937672841248499587971820438883924752373877794868883,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  99781011 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  99781011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"10.clkmgr_tl_intg_err.78571854866577858599940832272254063891952110870539903748041476694240200717023","seed":78571854866577858599940832272254063891952110870539903748041476694240200717023,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   1729585 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   1729585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"11.clkmgr_shadow_reg_errors_with_csr_rw.11783822365488061539198786571608793474036641709597605631649345483564474717144","seed":11783822365488061539198786571608793474036641709597605631649345483564474717144,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2816167 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   2816167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"12.clkmgr_csr_rw.27933139310880949874130599384908006451645213262362477866049309125703961303772","seed":27933139310880949874130599384908006451645213262362477866049309125703961303772,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2908921 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   2908921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"13.clkmgr_shadow_reg_errors_with_csr_rw.86381542535981850509730125628378496642191203416821385378300066979046800000595","seed":86381542535981850509730125628378496642191203416821385378300066979046800000595,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  25394328 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  25394328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"13.clkmgr_csr_mem_rw_with_rand_reset.4738467167859637873119154794473652422396805282150126195288791909434224830913","seed":4738467167859637873119154794473652422396805282150126195288791909434224830913,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   5620160 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   5620160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"15.clkmgr_shadow_reg_errors_with_csr_rw.67989003636372306400036315835155952587175181477534005602340858132640260394239","seed":67989003636372306400036315835155952587175181477534005602340858132640260394239,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   1805442 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   1805442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"15.clkmgr_tl_intg_err.14187029614414922566961554032371989851357105100504368636297499267161205184510","seed":14187029614414922566961554032371989851357105100504368636297499267161205184510,"line":93,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  14052828 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  14052828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"16.clkmgr_shadow_reg_errors_with_csr_rw.30062006302043367718303338510596999951734404445038119009186578574943912667051","seed":30062006302043367718303338510596999951734404445038119009186578574943912667051,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   8531624 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   8531624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"17.clkmgr_shadow_reg_errors_with_csr_rw.31191896316220918775958441383034481330708511373051139605928075166020907528692","seed":31191896316220918775958441383034481330708511373051139605928075166020907528692,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  13879022 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  13879022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"17.clkmgr_tl_intg_err.25476596132123438075028494722815149983442103183208483085904995898916862150529","seed":25476596132123438075028494722815149983442103183208483085904995898916862150529,"line":93,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  13669039 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  13669039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"18.clkmgr_shadow_reg_errors_with_csr_rw.42015141010913361246914748764623834080818329490310021417115436548091974973135","seed":42015141010913361246914748764623834080818329490310021417115436548091974973135,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  19481456 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  19481456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"19.clkmgr_shadow_reg_errors_with_csr_rw.98349493810507426871625693204085209737119563841408513535310826790712592779188","seed":98349493810507426871625693204085209737119563841408513535310826790712592779188,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   5760605 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   5760605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"19.clkmgr_csr_rw.32336797569007950411981050590707268330119748648093150502870557071611088638344","seed":32336797569007950411981050590707268330119748648093150502870557071611088638344,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @  10247298 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  10247298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"19.clkmgr_csr_mem_rw_with_rand_reset.76630584423643127675872026038985827466958462983287795964006739845909172495789","seed":76630584423643127675872026038985827466958462983287795964006739845909172495789,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  69621391 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  69621391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *":[{"name":"clkmgr_csr_bit_bash","qual_name":"0.clkmgr_csr_bit_bash.26879326514912327938301587536815469305090288141029442621938228003662261301891","seed":26879326514912327938301587536815469305090288141029442621938228003662261301891,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @  72949685 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @  72949685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_bit_bash","qual_name":"1.clkmgr_csr_bit_bash.108377977456989898358458714107794346850376471509280770632751151012286838922153","seed":108377977456989898358458714107794346850376471509280770632751151012286838922153,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @ 196225757 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @ 196225757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_bit_bash","qual_name":"2.clkmgr_csr_bit_bash.99183269002177300496003614432108826890916825494832140281542686966443962377540","seed":99183269002177300496003614432108826890916825494832140281542686966443962377540,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @  66152067 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @  66152067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_bit_bash","qual_name":"3.clkmgr_csr_bit_bash.109527720668599586337510060562128015888326630886434589173880010362035978881357","seed":109527720668599586337510060562128015888326630886434589173880010362035978881357,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @ 121648282 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @ 121648282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_bit_bash","qual_name":"4.clkmgr_csr_bit_bash.17253703045896369066690177560171970582115647400709462344754572334217730365511","seed":17253703045896369066690177560171970582115647400709462344754572334217730365511,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @  14802891 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @  14802891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch":[{"name":"clkmgr_same_csr_outstanding","qual_name":"0.clkmgr_same_csr_outstanding.81542458001307000092961726517193980140223670841752919354602887042618675575306","seed":81542458001307000092961726517193980140223670841752919354602887042618675575306,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   2342778 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x39e07fa4 read out mismatch\n","UVM_INFO @   2342778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"1.clkmgr_same_csr_outstanding.45126008606058730240591332482387224121171289171700205498929504492917124433185","seed":45126008606058730240591332482387224121171289171700205498929504492917124433185,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   2176967 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x5d1fc164 read out mismatch\n","UVM_INFO @   2176967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"2.clkmgr_same_csr_outstanding.19751839397405658189371276108377001780070401677898303105511430865529093073055","seed":19751839397405658189371276108377001780070401677898303105511430865529093073055,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   5851296 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x21ace9a4 read out mismatch\n","UVM_INFO @   5851296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"3.clkmgr_same_csr_outstanding.45321829125027547613020427213161814631663025339897986875992899136029668146243","seed":45321829125027547613020427213161814631663025339897986875992899136029668146243,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  13585899 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x5f7f8f64 read out mismatch\n","UVM_INFO @  13585899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"4.clkmgr_same_csr_outstanding.106457024762285934525345400047550666901987339025368862675141121250937090533500","seed":106457024762285934525345400047550666901987339025368862675141121250937090533500,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   2376757 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x6fb9ac64 read out mismatch\n","UVM_INFO @   2376757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"5.clkmgr_same_csr_outstanding.64453085395038373093984008890186213678523066746248122758772415526122453509190","seed":64453085395038373093984008890186213678523066746248122758772415526122453509190,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   3166253 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xe467e864 read out mismatch\n","UVM_INFO @   3166253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"6.clkmgr_same_csr_outstanding.98740662495142635517788891887034501390705232658685822907145004469749932345721","seed":98740662495142635517788891887034501390705232658685822907145004469749932345721,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   6277074 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xbce0f424 read out mismatch\n","UVM_INFO @   6277074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"7.clkmgr_same_csr_outstanding.46318704737383721896668898502937536221998355495339107680887176590429410587373","seed":46318704737383721896668898502937536221998355495339107680887176590429410587373,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   6218667 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x976df3e4 read out mismatch\n","UVM_INFO @   6218667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"8.clkmgr_same_csr_outstanding.44842931205836297224205418347445311851697315786351480022429475186667562219544","seed":44842931205836297224205418347445311851697315786351480022429475186667562219544,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   6676797 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xf4acd924 read out mismatch\n","UVM_INFO @   6676797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"9.clkmgr_same_csr_outstanding.33693962008120262175363931876342779994157999680101124667914176324316015999504","seed":33693962008120262175363931876342779994157999680101124667914176324316015999504,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   9186319 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x71ef6f64 read out mismatch\n","UVM_INFO @   9186319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"10.clkmgr_same_csr_outstanding.93627764901945919367260943381412811721749587039882446599594527287065570647707","seed":93627764901945919367260943381412811721749587039882446599594527287065570647707,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   8266909 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xfee82de4 read out mismatch\n","UVM_INFO @   8266909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"11.clkmgr_same_csr_outstanding.38050589416299818880467950354264513836178674429718436548064744351354299109625","seed":38050589416299818880467950354264513836178674429718436548064744351354299109625,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   3855806 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x1e42a124 read out mismatch\n","UVM_INFO @   3855806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"13.clkmgr_same_csr_outstanding.25449191121333743829987385101754137637875108598714366336885129440534387942559","seed":25449191121333743829987385101754137637875108598714366336885129440534387942559,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  45581696 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x1b71ea64 read out mismatch\n","UVM_INFO @  45581696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"14.clkmgr_same_csr_outstanding.67092517397868229214627927596878383093673506499358077248341710453293976079244","seed":67092517397868229214627927596878383093673506499358077248341710453293976079244,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   3546962 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x15e0c024 read out mismatch\n","UVM_INFO @   3546962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"15.clkmgr_same_csr_outstanding.76360345565310444686069150778851525568942407854717708420554178666228374957421","seed":76360345565310444686069150778851525568942407854717708420554178666228374957421,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   5417326 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xf265124 read out mismatch\n","UVM_INFO @   5417326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"17.clkmgr_same_csr_outstanding.34858806154412303040536852502417580239807396061064332497112004996051964032579","seed":34858806154412303040536852502417580239807396061064332497112004996051964032579,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  16231513 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xbc43324 read out mismatch\n","UVM_INFO @  16231513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"18.clkmgr_same_csr_outstanding.111142106597295203312298583175763635663572978212161205427568203847039807081879","seed":111142106597295203312298583175763635663572978212161205427568203847039807081879,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   9226058 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xd2cd80e4 read out mismatch\n","UVM_INFO @   9226058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"19.clkmgr_same_csr_outstanding.67218998731569993152306620238681844433308300064330525304980529876149134840075","seed":67218998731569993152306620238681844433308300064330525304980529876149134840075,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   3928351 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x185941a4 read out mismatch\n","UVM_INFO @   3928351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: *":[{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"1.clkmgr_csr_mem_rw_with_rand_reset.30064595143273415644210977127658358630254812252336872072314811539752921664639","seed":30064595143273415644210977127658358630254812252336872072314811539752921664639,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  35879543 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  35879543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"2.clkmgr_csr_rw.39824176097149545631373202744285626332897019852612487109589586637543361710450","seed":39824176097149545631373202744285626332897019852612487109589586637543361710450,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3994206 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   3994206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"2.clkmgr_csr_mem_rw_with_rand_reset.99639616395326161999259095553352629256586982253121529043848618611227618754308","seed":99639616395326161999259095553352629256586982253121529043848618611227618754308,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   4864545 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   4864545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"3.clkmgr_csr_rw.113852668016538825059370802206558879721050690458450888848090381512263300722964","seed":113852668016538825059370802206558879721050690458450888848090381512263300722964,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2537431 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2537431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"4.clkmgr_shadow_reg_errors_with_csr_rw.101307084534899860308353070509791806148285853941437361961911669916485951661840","seed":101307084534899860308353070509791806148285853941437361961911669916485951661840,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   5538222 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   5538222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"5.clkmgr_tl_intg_err.67546653138475040107817756577669739065023989574286870975697240613780766482930","seed":67546653138475040107817756577669739065023989574286870975697240613780766482930,"line":90,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  24897506 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  24897506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"6.clkmgr_tl_intg_err.46536006441986350553421903130822281811003556951777698970551807188229512802203","seed":46536006441986350553421903130822281811003556951777698970551807188229512802203,"line":86,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   7171483 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   7171483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"7.clkmgr_shadow_reg_errors_with_csr_rw.85180011826819082508520689806926384963877547253516191294426198191770017492326","seed":85180011826819082508520689806926384963877547253516191294426198191770017492326,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   8456421 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   8456421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"8.clkmgr_shadow_reg_errors_with_csr_rw.96484233003210512062899186784871240564780449694668514196895373483965947569583","seed":96484233003210512062899186784871240564780449694668514196895373483965947569583,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  31258428 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  31258428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"8.clkmgr_tl_intg_err.63714794849167395384597932826724037163411344585226090030672265833715815382614","seed":63714794849167395384597932826724037163411344585226090030672265833715815382614,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   3255702 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   3255702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"10.clkmgr_shadow_reg_errors_with_csr_rw.86737952950021942408977644178963928561715849385281374438408490325771059228412","seed":86737952950021942408977644178963928561715849385281374438408490325771059228412,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  30932945 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  30932945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"10.clkmgr_csr_rw.41761359021711078294168040159239918505937077262923939164280558849385700449512","seed":41761359021711078294168040159239918505937077262923939164280558849385700449512,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   5014808 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   5014808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"11.clkmgr_tl_intg_err.105039812828036880006318318354891952897861294378622366702666602291885820351435","seed":105039812828036880006318318354891952897861294378622366702666602291885820351435,"line":83,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   6739790 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   6739790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"11.clkmgr_csr_rw.92723954554018978454986663931851455915673269717488857603571731141810790509191","seed":92723954554018978454986663931851455915673269717488857603571731141810790509191,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   7869691 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   7869691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"11.clkmgr_csr_mem_rw_with_rand_reset.74557768023631006108909325640493387265285875484486914005233856260452485788368","seed":74557768023631006108909325640493387265285875484486914005233856260452485788368,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  71248915 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  71248915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"12.clkmgr_shadow_reg_errors_with_csr_rw.84007252060482306237638991885025998824369380341629572424808036945203463126996","seed":84007252060482306237638991885025998824369380341629572424808036945203463126996,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3475342 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   3475342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"12.clkmgr_tl_intg_err.5925761225157387367362973389131606603766357679434259499942473211748336350503","seed":5925761225157387367362973389131606603766357679434259499942473211748336350503,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  10056904 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  10056904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"12.clkmgr_csr_mem_rw_with_rand_reset.42846431743110625159434153119071502402741857439667611239527001491102807510817","seed":42846431743110625159434153119071502402741857439667611239527001491102807510817,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   1747185 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   1747185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"13.clkmgr_tl_intg_err.77950248267980243547019423512988683229097884062478767496422477623707006399963","seed":77950248267980243547019423512988683229097884062478767496422477623707006399963,"line":86,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  14915506 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  14915506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"14.clkmgr_shadow_reg_errors_with_csr_rw.62250948351888962274330325703372915012636134853357026820578497539246809865488","seed":62250948351888962274330325703372915012636134853357026820578497539246809865488,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  10569288 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  10569288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"14.clkmgr_tl_intg_err.19236430799237727321547318449009637121455729343626363883668172359322727858591","seed":19236430799237727321547318449009637121455729343626363883668172359322727858591,"line":87,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  19654612 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  19654612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"14.clkmgr_csr_mem_rw_with_rand_reset.88243178385419094166681547241671095301595170785318516905005229427682787104326","seed":88243178385419094166681547241671095301595170785318516905005229427682787104326,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  57919732 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  57919732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"16.clkmgr_tl_intg_err.115700111706616678098510196884682398247419391723288034332952213225373751166339","seed":115700111706616678098510196884682398247419391723288034332952213225373751166339,"line":87,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  15841913 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  15841913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"16.clkmgr_csr_rw.21930099591686613912771047294296073122074780697663597921693140300092706604092","seed":21930099591686613912771047294296073122074780697663597921693140300092706604092,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @  15873628 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  15873628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"17.clkmgr_csr_rw.70051702094861763215253913118874318085870488985466926648590626118382903185098","seed":70051702094861763215253913118874318085870488985466926648590626118382903185098,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   5616035 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   5616035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"18.clkmgr_tl_intg_err.8020364739343703396646849002153835937021352643008128171135866036337975224714","seed":8020364739343703396646849002153835937021352643008128171135866036337975224714,"line":93,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  17507427 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  17507427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"18.clkmgr_csr_mem_rw_with_rand_reset.68551633646051528634670774375077034612203838569422052861728681315951819656823","seed":68551633646051528634670774375077034612203838569422052861728681315951819656823,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   8629961 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   8629961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"19.clkmgr_tl_intg_err.6317162465912349791830841692185939492187158002708886721487860418949608483001","seed":6317162465912349791830841692185939492187158002708886721487860418949608483001,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   5389399 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   5389399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":373,"total":710,"percent":52.53521126760563}