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(cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"edn_stress_all_with_rand_reset","qual_name":"1.edn_stress_all_with_rand_reset.20898445304150793447808386548609299589703284634008112454412009456627246069252","seed":20898445304150793447808386548609299589703284634008112454412009456627246069252,"line":234,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/1.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1803201626 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1803201626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"16.edn_stress_all_with_rand_reset.2602679576450136225035344367884215783056531797357324463225953964121075103618","seed":2602679576450136225035344367884215783056531797357324463225953964121075103618,"line":132,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/16.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 786756698 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 786756698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"22.edn_stress_all_with_rand_reset.93298612767226473354167381892212364510014966096113090830159498293802514306468","seed":93298612767226473354167381892212364510014966096113090830159498293802514306468,"line":125,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/22.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 113252402 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 113252402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"30.edn_stress_all_with_rand_reset.6483888861767824038592600396964215402202027821794810584532287625147320621533","seed":6483888861767824038592600396964215402202027821794810584532287625147320621533,"line":185,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/30.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1312134808 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1312134808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"31.edn_stress_all_with_rand_reset.60717010448884248337305144068778277891771977229120161879163655789564333664542","seed":60717010448884248337305144068778277891771977229120161879163655789564333664542,"line":231,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/31.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 235882034 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 235882034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"33.edn_stress_all_with_rand_reset.64255274107976743744764440553353652046192646613134722944528696640348995874846","seed":64255274107976743744764440553353652046192646613134722944528696640348995874846,"line":332,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/33.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4502235829 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4502235829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"38.edn_stress_all_with_rand_reset.113544484855765717043488532102197283071683357796477740962269585015686605739762","seed":113544484855765717043488532102197283071683357796477740962269585015686605739762,"line":253,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/38.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2073640134 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2073640134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"39.edn_stress_all_with_rand_reset.1095990899116772140332977007744280821402328748427216605403930761740236044885","seed":1095990899116772140332977007744280821402328748427216605403930761740236044885,"line":209,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/39.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2188919361 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2188919361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"40.edn_stress_all_with_rand_reset.43340987360167637880691290534297366493960648574789049393002901838666755521111","seed":43340987360167637880691290534297366493960648574789049393002901838666755521111,"line":192,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/40.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1249666067 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1249666067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"48.edn_stress_all_with_rand_reset.91089613750754457030140488333725584543852189390801008866694625777419268098524","seed":91089613750754457030140488333725584543852189390801008866694625777419268098524,"line":237,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/48.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2867090569 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2867090569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.":[{"name":"edn_disable_auto_req_mode","qual_name":"5.edn_disable_auto_req_mode.17063611492133392553400327752972711794309500382547909248414018316669671105162","seed":17063611492133392553400327752972711794309500382547909248414018316669671105162,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/5.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  77894838 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x003019a2 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  77894838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"41.edn_disable_auto_req_mode.87187240959877120160470271311265754252587855752619820323447092622333635789631","seed":87187240959877120160470271311265754252587855752619820323447092622333635789631,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/41.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  39099012 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00001903 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  39099012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"edn_disable_auto_req_mode","qual_name":"8.edn_disable_auto_req_mode.55967285140359557222995276640015138832898307405952727938513084650386036728349","seed":55967285140359557222995276640015138832898307405952727938513084650386036728349,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/8.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"12.edn_disable_auto_req_mode.86458250712523596504750760212390513975014299038439847419465062375252492239186","seed":86458250712523596504750760212390513975014299038439847419465062375252492239186,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/12.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"17.edn_disable_auto_req_mode.91017226432553262813669964000249807492290552501535012137987518272214853519355","seed":91017226432553262813669964000249807492290552501535012137987518272214853519355,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/17.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"29.edn_disable_auto_req_mode.71661615612863336037799462854004213729156852357096426878661071396929021729266","seed":71661615612863336037799462854004213729156852357096426878661071396929021729266,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/29.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"32.edn_disable_auto_req_mode.97969361084011364272528754176499427311357178537120420427486336845610071240834","seed":97969361084011364272528754176499427311357178537120420427486336845610071240834,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/32.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"44.edn_disable_auto_req_mode.55705959344394551138371023343172852036377558221618454676411415131223015670904","seed":55705959344394551138371023343172852036377558221618454676411415131223015670904,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/44.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1112,"total":1130,"percent":98.40707964601769}