{"block":{"name":"edn","variant":"edn1","commit":"8007f614bd52d7ac557e5e3253489f0bf7b820c5","commit_short":"8007f61","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/8007f614bd52d7ac557e5e3253489f0bf7b820c5","revision_info":"GitHub Revision: [`8007f61`](https://github.com/lowrisc/opentitan/tree/8007f614bd52d7ac557e5e3253489f0bf7b820c5)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-24T16:00:28Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/edn_edn1/data/edn_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"edn_smoke":{"max_time":1.27,"sim_time":17.07897,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"edn_csr_hw_reset":{"max_time":0.82,"sim_time":37.922665,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"edn_csr_rw":{"max_time":0.82,"sim_time":18.662596,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"edn_csr_bit_bash":{"max_time":3.31,"sim_time":668.6071,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"edn_csr_aliasing":{"max_time":1.05,"sim_time":27.040663000000002,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"edn_csr_mem_rw_with_rand_reset":{"max_time":1.48,"sim_time":64.409708,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"edn_csr_rw":{"max_time":0.82,"sim_time":18.662596,"passed":20,"total":20,"percent":100.0},"edn_csr_aliasing":{"max_time":1.05,"sim_time":27.040663000000002,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":105,"total":105,"percent":100.0},"V2":{"testpoints":{"firmware":{"tests":{"edn_genbits":{"max_time":4.01,"sim_time":450.91153,"passed":300,"total":300,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"csrng_commands":{"tests":{"edn_genbits":{"max_time":4.01,"sim_time":450.91153,"passed":300,"total":300,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"genbits":{"tests":{"edn_genbits":{"max_time":4.01,"sim_time":450.91153,"passed":300,"total":300,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"interrupts":{"tests":{"edn_intr":{"max_time":1.36,"sim_time":24.525830000000003,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"alerts":{"tests":{"edn_alert":{"max_time":1.53,"sim_time":44.797684999999994,"passed":200,"total":200,"percent":100.0}},"passed":200,"total":200,"percent":100.0},"errs":{"tests":{"edn_err":{"max_time":1.5,"sim_time":29.011524,"passed":100,"total":100,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"disable":{"tests":{"edn_disable":{"max_time":1.19,"sim_time":35.680502999999995,"passed":50,"total":50,"percent":100.0},"edn_disable_auto_req_mode":{"max_time":16.65,"sim_time":500.0,"passed":43,"total":50,"percent":86.0}},"passed":93,"total":100,"percent":93.0},"stress_all":{"tests":{"edn_stress_all":{"max_time":5.31,"sim_time":401.880294,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"edn_intr_test":{"max_time":0.87,"sim_time":17.712076,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"alert_test":{"tests":{"edn_alert_test":{"max_time":2.92,"sim_time":420.512805,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"edn_tl_errors":{"max_time":2.88,"sim_time":275.881605,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"edn_tl_errors":{"max_time":2.88,"sim_time":275.881605,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"edn_csr_hw_reset":{"max_time":0.82,"sim_time":37.922665,"passed":5,"total":5,"percent":100.0},"edn_csr_rw":{"max_time":0.82,"sim_time":18.662596,"passed":20,"total":20,"percent":100.0},"edn_csr_aliasing":{"max_time":1.05,"sim_time":27.040663000000002,"passed":5,"total":5,"percent":100.0},"edn_same_csr_outstanding":{"max_time":1.12,"sim_time":41.662871,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"edn_csr_hw_reset":{"max_time":0.82,"sim_time":37.922665,"passed":5,"total":5,"percent":100.0},"edn_csr_rw":{"max_time":0.82,"sim_time":18.662596,"passed":20,"total":20,"percent":100.0},"edn_csr_aliasing":{"max_time":1.05,"sim_time":27.040663000000002,"passed":5,"total":5,"percent":100.0},"edn_same_csr_outstanding":{"max_time":1.12,"sim_time":41.662871,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":963,"total":970,"percent":99.27835051546391},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"edn_tl_intg_err":{"max_time":2.05,"sim_time":1385.121281,"passed":20,"total":20,"percent":100.0},"edn_sec_cm":{"max_time":5.36,"sim_time":395.880216,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_config_regwen":{"tests":{"edn_regwen":{"max_time":1.23,"sim_time":29.224097,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sec_cm_config_mubi":{"tests":{"edn_alert":{"max_time":1.53,"sim_time":44.797684999999994,"passed":200,"total":200,"percent":100.0}},"passed":200,"total":200,"percent":100.0},"sec_cm_main_sm_fsm_sparse":{"tests":{"edn_sec_cm":{"max_time":5.36,"sim_time":395.880216,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ack_sm_fsm_sparse":{"tests":{"edn_sec_cm":{"max_time":5.36,"sim_time":395.880216,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_fifo_ctr_redun":{"tests":{"edn_sec_cm":{"max_time":5.36,"sim_time":395.880216,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ctr_redun":{"tests":{"edn_sec_cm":{"max_time":5.36,"sim_time":395.880216,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_main_sm_ctr_local_esc":{"tests":{"edn_alert":{"max_time":1.53,"sim_time":44.797684999999994,"passed":200,"total":200,"percent":100.0},"edn_sec_cm":{"max_time":5.36,"sim_time":395.880216,"passed":5,"total":5,"percent":100.0}},"passed":205,"total":205,"percent":100.0},"sec_cm_cs_rdata_bus_consistency":{"tests":{"edn_alert":{"max_time":1.53,"sim_time":44.797684999999994,"passed":200,"total":200,"percent":100.0}},"passed":200,"total":200,"percent":100.0},"sec_cm_tile_link_bus_integrity":{"tests":{"edn_tl_intg_err":{"max_time":2.05,"sim_time":1385.121281,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0}},"passed":235,"total":235,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"edn_stress_all_with_rand_reset":{"max_time":88.56,"sim_time":49299.679511,"passed":46,"total":50,"percent":92.0}},"passed":46,"total":50,"percent":92.0}},"passed":46,"total":50,"percent":92.0}},"coverage":{"code":{"block":null,"line_statement":98.48,"branch":94.59,"condition_expression":95.0,"toggle":96.15,"fsm":94.32},"assertion":97.14,"functional":92.44},"cov_report_page":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"edn_stress_all_with_rand_reset","qual_name":"2.edn_stress_all_with_rand_reset.93294439877521694046583416823618731401475355039947047861281025241353395171505","seed":93294439877521694046583416823618731401475355039947047861281025241353395171505,"line":222,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2061960259 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2061960259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"9.edn_stress_all_with_rand_reset.3626027525328950465798392795269826992033360726211584851228745359417975716236","seed":3626027525328950465798392795269826992033360726211584851228745359417975716236,"line":151,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 547941335 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 547941335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"15.edn_stress_all_with_rand_reset.114564877822749079493470096195931358171823294018951184185988898598650609851375","seed":114564877822749079493470096195931358171823294018951184185988898598650609851375,"line":201,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2348347460 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2348347460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"31.edn_stress_all_with_rand_reset.46847529570674450606574639183923116632991202213920350517584315686820950955658","seed":46847529570674450606574639183923116632991202213920350517584315686820950955658,"line":209,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/31.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1703434335 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1703434335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"edn_disable_auto_req_mode","qual_name":"7.edn_disable_auto_req_mode.75766288584646985083534550169445767925403723580063712540171466328358311410791","seed":75766288584646985083534550169445767925403723580063712540171466328358311410791,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/7.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"12.edn_disable_auto_req_mode.34784878740832639976100362227335782695651303065103052592548985211187711822294","seed":34784878740832639976100362227335782695651303065103052592548985211187711822294,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/12.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"15.edn_disable_auto_req_mode.105571386844917377828180734000039467720246070677188993489156568810168161659101","seed":105571386844917377828180734000039467720246070677188993489156568810168161659101,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"20.edn_disable_auto_req_mode.102054328338666870973111131047697064055359328484022321758323813628818778018703","seed":102054328338666870973111131047697064055359328484022321758323813628818778018703,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.":[{"name":"edn_disable_auto_req_mode","qual_name":"29.edn_disable_auto_req_mode.67141496134702730713232660353399869630539509926186469158241769382173104469226","seed":67141496134702730713232660353399869630539509926186469158241769382173104469226,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/29.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  10522762 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00935902 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  10522762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"47.edn_disable_auto_req_mode.107137857988846827597525898981523795828006055679349027604592903898599152093581","seed":107137857988846827597525898981523795828006055679349027604592903898599152093581,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/47.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  12618956 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00f389a2 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  12618956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Error-[FCIBH] Illegal bin hit":[{"name":"edn_disable_auto_req_mode","qual_name":"44.edn_disable_auto_req_mode.88316089735987803067347254921435368641281149829717064631466850781487552553802","seed":88316089735987803067347254921435368641281149829717064631466850781487552553802,"line":90,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/44.edn_disable_auto_req_mode/latest/run.log","log_context":["Error-[FCIBH] Illegal bin hit\n","/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25\n","csrng_agent_pkg, \"csrng_agent_pkg::device_cmd_cg\"\n","  VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 180791516 ps, Illegal \n","  state bin il of coverpoint csrng_cmd_cp in covergroup \n"]}]}},"passed":1119,"total":1130,"percent":99.02654867256638}