{"block":{"name":"lc_ctrl","variant":"volatile_unlock_enabled","commit":"8007f614bd52d7ac557e5e3253489f0bf7b820c5","commit_short":"8007f61","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/8007f614bd52d7ac557e5e3253489f0bf7b820c5","revision_info":"GitHub Revision: [`8007f61`](https://github.com/lowrisc/opentitan/tree/8007f614bd52d7ac557e5e3253489f0bf7b820c5)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-24T16:00:28Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/lc_ctrl_volatile_unlock_enabled/data/lc_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"lc_ctrl_smoke":{"max_time":6.72,"sim_time":154.12924299999997,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"lc_ctrl_csr_hw_reset":{"max_time":1.34,"sim_time":20.409326,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"lc_ctrl_csr_rw":{"max_time":1.4,"sim_time":17.046508999999997,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"lc_ctrl_csr_bit_bash":{"max_time":2.33,"sim_time":812.217413,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"lc_ctrl_csr_aliasing":{"max_time":1.59,"sim_time":64.95516,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"lc_ctrl_csr_mem_rw_with_rand_reset":{"max_time":1.82,"sim_time":107.992003,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"lc_ctrl_csr_rw":{"max_time":1.4,"sim_time":17.046508999999997,"passed":20,"total":20,"percent":100.0},"lc_ctrl_csr_aliasing":{"max_time":1.59,"sim_time":64.95516,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":105,"total":105,"percent":100.0},"V2":{"testpoints":{"state_post_trans":{"tests":{"lc_ctrl_state_post_trans":{"max_time":9.15,"sim_time":245.041894,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"regwen_during_op":{"tests":{"lc_ctrl_regwen_during_op":{"max_time":17.35,"sim_time":792.93129,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rand_wr_claim_transition_if":{"tests":{"lc_ctrl_claim_transition_if":{"max_time":1.24,"sim_time":17.018104,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"lc_prog_failure":{"tests":{"lc_ctrl_prog_failure":{"max_time":5.03,"sim_time":115.588912,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"lc_state_failure":{"tests":{"lc_ctrl_state_failure":{"max_time":12.75,"sim_time":267.41457299999996,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"lc_errors":{"tests":{"lc_ctrl_errors":{"max_time":13.67,"sim_time":492.425844,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"security_escalation":{"tests":{"lc_ctrl_state_failure":{"max_time":12.75,"sim_time":267.41457299999996,"passed":50,"total":50,"percent":100.0},"lc_ctrl_prog_failure":{"max_time":5.03,"sim_time":115.588912,"passed":50,"total":50,"percent":100.0},"lc_ctrl_errors":{"max_time":13.67,"sim_time":492.425844,"passed":50,"total":50,"percent":100.0},"lc_ctrl_security_escalation":{"max_time":10.86,"sim_time":764.473324,"passed":50,"total":50,"percent":100.0},"lc_ctrl_jtag_state_failure":{"max_time":87.94,"sim_time":15467.707658,"passed":20,"total":20,"percent":100.0},"lc_ctrl_jtag_prog_failure":{"max_time":15.12,"sim_time":5699.115335,"passed":20,"total":20,"percent":100.0},"lc_ctrl_jtag_errors":{"max_time":51.43,"sim_time":32884.266929000005,"passed":20,"total":20,"percent":100.0}},"passed":260,"total":260,"percent":100.0},"jtag_access":{"tests":{"lc_ctrl_jtag_smoke":{"max_time":9.58,"sim_time":1859.940351,"passed":20,"total":20,"percent":100.0},"lc_ctrl_jtag_state_post_trans":{"max_time":24.12,"sim_time":5583.243013,"passed":20,"total":20,"percent":100.0},"lc_ctrl_jtag_prog_failure":{"max_time":15.12,"sim_time":5699.115335,"passed":20,"total":20,"percent":100.0},"lc_ctrl_jtag_errors":{"max_time":51.43,"sim_time":32884.266929000005,"passed":20,"total":20,"percent":100.0},"lc_ctrl_jtag_access":{"max_time":17.02,"sim_time":3352.8773429999997,"passed":50,"total":50,"percent":100.0},"lc_ctrl_jtag_regwen_during_op":{"max_time":30.01,"sim_time":5154.397967,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_csr_hw_reset":{"max_time":5.34,"sim_time":599.5127269999999,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_csr_rw":{"max_time":2.68,"sim_time":444.047952,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_csr_bit_bash":{"max_time":46.8,"sim_time":3432.565181,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_csr_aliasing":{"max_time":12.6,"sim_time":788.129361,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_same_csr_outstanding":{"max_time":1.58,"sim_time":139.899135,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_csr_mem_rw_with_rand_reset":{"max_time":5.18,"sim_time":1201.470026,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_alert_test":{"max_time":2.38,"sim_time":166.35607000000002,"passed":10,"total":10,"percent":100.0}},"passed":210,"total":210,"percent":100.0},"jtag_priority":{"tests":{"lc_ctrl_jtag_priority":{"max_time":96.99,"sim_time":12045.774758,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"lc_ctrl_volatile_unlock":{"tests":{"lc_ctrl_volatile_unlock_smoke":{"max_time":1.58,"sim_time":17.475642,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all":{"tests":{"lc_ctrl_stress_all":{"max_time":362.79,"sim_time":66331.815251,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0},"alert_test":{"tests":{"lc_ctrl_alert_test":{"max_time":2.09,"sim_time":113.603685,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"lc_ctrl_tl_errors":{"max_time":3.57,"sim_time":707.8068440000001,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"lc_ctrl_tl_errors":{"max_time":3.57,"sim_time":707.8068440000001,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"lc_ctrl_csr_hw_reset":{"max_time":1.34,"sim_time":20.409326,"passed":5,"total":5,"percent":100.0},"lc_ctrl_csr_rw":{"max_time":1.4,"sim_time":17.046508999999997,"passed":20,"total":20,"percent":100.0},"lc_ctrl_csr_aliasing":{"max_time":1.59,"sim_time":64.95516,"passed":5,"total":5,"percent":100.0},"lc_ctrl_same_csr_outstanding":{"max_time":1.81,"sim_time":40.670754,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"lc_ctrl_csr_hw_reset":{"max_time":1.34,"sim_time":20.409326,"passed":5,"total":5,"percent":100.0},"lc_ctrl_csr_rw":{"max_time":1.4,"sim_time":17.046508999999997,"passed":20,"total":20,"percent":100.0},"lc_ctrl_csr_aliasing":{"max_time":1.59,"sim_time":64.95516,"passed":5,"total":5,"percent":100.0},"lc_ctrl_same_csr_outstanding":{"max_time":1.81,"sim_time":40.670754,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":729,"total":730,"percent":99.86301369863014},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"lc_ctrl_sec_cm":{"max_time":9.38,"sim_time":1766.012833,"passed":5,"total":5,"percent":100.0},"lc_ctrl_tl_intg_err":{"max_time":4.28,"sim_time":3049.034826,"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"lc_ctrl_tl_intg_err":{"max_time":4.28,"sim_time":3049.034826,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_transition_config_regwen":{"tests":{"lc_ctrl_regwen_during_op":{"max_time":17.35,"sim_time":792.93129,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sec_cm_manuf_state_sparse":{"tests":{"lc_ctrl_state_failure":{"max_time":12.75,"sim_time":267.41457299999996,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.38,"sim_time":1766.012833,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_transition_ctr_sparse":{"tests":{"lc_ctrl_state_failure":{"max_time":12.75,"sim_time":267.41457299999996,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.38,"sim_time":1766.012833,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_manuf_state_bkgn_chk":{"tests":{"lc_ctrl_state_failure":{"max_time":12.75,"sim_time":267.41457299999996,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.38,"sim_time":1766.012833,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_transition_ctr_bkgn_chk":{"tests":{"lc_ctrl_state_failure":{"max_time":12.75,"sim_time":267.41457299999996,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.38,"sim_time":1766.012833,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_state_config_sparse":{"tests":{"lc_ctrl_state_failure":{"max_time":12.75,"sim_time":267.41457299999996,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.38,"sim_time":1766.012833,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_main_fsm_sparse":{"tests":{"lc_ctrl_state_failure":{"max_time":12.75,"sim_time":267.41457299999996,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.38,"sim_time":1766.012833,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_kmac_fsm_sparse":{"tests":{"lc_ctrl_state_failure":{"max_time":12.75,"sim_time":267.41457299999996,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.38,"sim_time":1766.012833,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_main_fsm_local_esc":{"tests":{"lc_ctrl_state_failure":{"max_time":12.75,"sim_time":267.41457299999996,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.38,"sim_time":1766.012833,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_main_fsm_global_esc":{"tests":{"lc_ctrl_security_escalation":{"max_time":10.86,"sim_time":764.473324,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_main_ctrl_flow_consistency":{"tests":{"lc_ctrl_state_post_trans":{"max_time":9.15,"sim_time":245.041894,"passed":50,"total":50,"percent":100.0},"lc_ctrl_jtag_state_post_trans":{"max_time":24.12,"sim_time":5583.243013,"passed":20,"total":20,"percent":100.0}},"passed":70,"total":70,"percent":100.0},"sec_cm_intersig_mubi":{"tests":{"lc_ctrl_sec_mubi":{"max_time":16.73,"sim_time":2788.2990290000002,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_token_valid_ctrl_mubi":{"tests":{"lc_ctrl_sec_mubi":{"max_time":16.73,"sim_time":2788.2990290000002,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_token_digest":{"tests":{"lc_ctrl_sec_token_digest":{"max_time":14.29,"sim_time":894.841417,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_token_mux_ctrl_redun":{"tests":{"lc_ctrl_sec_token_mux":{"max_time":15.26,"sim_time":731.2184599999999,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_token_valid_mux_redun":{"tests":{"lc_ctrl_sec_token_mux":{"max_time":15.26,"sim_time":731.2184599999999,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":355,"total":355,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"lc_ctrl_stress_all_with_rand_reset":{"max_time":116.1,"sim_time":5294.163487,"passed":17,"total":50,"percent":34.0}},"passed":17,"total":50,"percent":34.0}},"passed":17,"total":50,"percent":34.0}},"coverage":{"code":{"block":null,"line_statement":97.87,"branch":97.06,"condition_expression":82.59,"toggle":91.35,"fsm":76.36},"assertion":96.13,"functional":96.22},"cov_report_page":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"0.lc_ctrl_stress_all_with_rand_reset.87150689919386868825137428974427549116692949674212806424832646245364357881379","seed":87150689919386868825137428974427549116692949674212806424832646245364357881379,"line":2037,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6797016288 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 6797016288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"2.lc_ctrl_stress_all_with_rand_reset.96947793177328825567691051760451073301541211936331648907843289869650762319739","seed":96947793177328825567691051760451073301541211936331648907843289869650762319739,"line":3469,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5066146555 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5066146555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"3.lc_ctrl_stress_all_with_rand_reset.9253354916141288832875591896385914333949477567816856359005855942976015337732","seed":9253354916141288832875591896385914333949477567816856359005855942976015337732,"line":1388,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2084745545 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2084745545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"4.lc_ctrl_stress_all_with_rand_reset.32061783906340089690700220563326852248416688362226458120752588586608080741857","seed":32061783906340089690700220563326852248416688362226458120752588586608080741857,"line":1633,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1645319168 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1645319168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"6.lc_ctrl_stress_all_with_rand_reset.76683625927476496303267020333590829160347226262753135465643696130930382861967","seed":76683625927476496303267020333590829160347226262753135465643696130930382861967,"line":5078,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3503456166 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3503456166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"7.lc_ctrl_stress_all_with_rand_reset.3507944399535784218740388638341068460969431466606328122017434450923346310811","seed":3507944399535784218740388638341068460969431466606328122017434450923346310811,"line":3558,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1856794094 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1856794094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"9.lc_ctrl_stress_all_with_rand_reset.1136547840815077492361712738577585071749021670036646000630218260776481049509","seed":1136547840815077492361712738577585071749021670036646000630218260776481049509,"line":3804,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5726701728 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5726701728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"11.lc_ctrl_stress_all_with_rand_reset.34119046675474830546957846902342566545773095242356231841409222559428978631639","seed":34119046675474830546957846902342566545773095242356231841409222559428978631639,"line":9518,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2731589988 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2731589988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"12.lc_ctrl_stress_all_with_rand_reset.69508678506797275494671727072631725580559748546037816728422901603629402210746","seed":69508678506797275494671727072631725580559748546037816728422901603629402210746,"line":7114,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 9364708816 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 9364708816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"14.lc_ctrl_stress_all_with_rand_reset.65079934619985207276379296023208497689176299463007596433105949373845132350726","seed":65079934619985207276379296023208497689176299463007596433105949373845132350726,"line":249,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 640905709 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 640905709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"16.lc_ctrl_stress_all_with_rand_reset.109806902757669346051619530379332901059711064267255905644218765476846245205694","seed":109806902757669346051619530379332901059711064267255905644218765476846245205694,"line":1277,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2909610073 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2909610073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"17.lc_ctrl_stress_all_with_rand_reset.80212085156673412374830488293288222716576813915997107255740778169501877962822","seed":80212085156673412374830488293288222716576813915997107255740778169501877962822,"line":6141,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2193235522 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2193235522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"18.lc_ctrl_stress_all_with_rand_reset.30005207629512364507001630950534510758714285704674080248097965717320395193166","seed":30005207629512364507001630950534510758714285704674080248097965717320395193166,"line":6643,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5294163487 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5294163487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"19.lc_ctrl_stress_all_with_rand_reset.14496107635887490412528213297713449758804236877207954561136713122167998209855","seed":14496107635887490412528213297713449758804236877207954561136713122167998209855,"line":6667,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2833156957 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2833156957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"20.lc_ctrl_stress_all_with_rand_reset.84475992044853559285404652076312315175985005089537687755465017629448338763309","seed":84475992044853559285404652076312315175985005089537687755465017629448338763309,"line":163,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1982114445 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1982114445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"22.lc_ctrl_stress_all_with_rand_reset.93115480969675512635567997184684143870592899825285272258811122139998096582318","seed":93115480969675512635567997184684143870592899825285272258811122139998096582318,"line":4045,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3334422362 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3334422362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"23.lc_ctrl_stress_all_with_rand_reset.63798757397352086207096120036937844646984936366413433928529389108136220514838","seed":63798757397352086207096120036937844646984936366413433928529389108136220514838,"line":633,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 11039668169 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 11039668169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"25.lc_ctrl_stress_all_with_rand_reset.24979769637277582754089610934668804118928128151172879223382749203979431365103","seed":24979769637277582754089610934668804118928128151172879223382749203979431365103,"line":3532,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7390310792 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 7390310792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"26.lc_ctrl_stress_all_with_rand_reset.40299417306587513965720256991156616240473210029515593527347886490918686838246","seed":40299417306587513965720256991156616240473210029515593527347886490918686838246,"line":4030,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2953082078 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2953082078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"27.lc_ctrl_stress_all_with_rand_reset.112780147869843049022566957706532790885791076410698205594407669257115741297312","seed":112780147869843049022566957706532790885791076410698205594407669257115741297312,"line":433,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2287854353 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2287854353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"28.lc_ctrl_stress_all_with_rand_reset.7037363631976278099096228149308200770417511586227581669771293072410951210793","seed":7037363631976278099096228149308200770417511586227581669771293072410951210793,"line":699,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1307990860 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1307990860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"30.lc_ctrl_stress_all_with_rand_reset.69426686345956124209305324152366581050936216253920350215183438885970907554876","seed":69426686345956124209305324152366581050936216253920350215183438885970907554876,"line":5160,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5283777406 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5283777406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"31.lc_ctrl_stress_all_with_rand_reset.26689730448423124763015435557720142910272815616393151683572386969146590457983","seed":26689730448423124763015435557720142910272815616393151683572386969146590457983,"line":4246,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2955446423 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2955446423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"34.lc_ctrl_stress_all_with_rand_reset.50314038054300704256032248809932250635510909682201734181346916752099564534296","seed":50314038054300704256032248809932250635510909682201734181346916752099564534296,"line":591,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1167383183 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1167383183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"37.lc_ctrl_stress_all_with_rand_reset.76728804296589124727643367838932615776599721783665240811083595978232541950521","seed":76728804296589124727643367838932615776599721783665240811083595978232541950521,"line":803,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2072769121 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2072769121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"38.lc_ctrl_stress_all_with_rand_reset.88265557541194015432804238193006571372192004184569719423709389053819230047400","seed":88265557541194015432804238193006571372192004184569719423709389053819230047400,"line":1064,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1773807885 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1773807885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"40.lc_ctrl_stress_all_with_rand_reset.103875813674018377556704890430635132097498139515275348361596784404828150372395","seed":103875813674018377556704890430635132097498139515275348361596784404828150372395,"line":209,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3066236502 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3066236502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"42.lc_ctrl_stress_all_with_rand_reset.112252216252527993189306344326928820955907534361755390851499141036177742702061","seed":112252216252527993189306344326928820955907534361755390851499141036177742702061,"line":705,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 21313448408 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 21313448408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"44.lc_ctrl_stress_all_with_rand_reset.98384639644772068388486262693912119546901659942128520556758071516688633402283","seed":98384639644772068388486262693912119546901659942128520556758071516688633402283,"line":11799,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6705349799 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 6705349799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"46.lc_ctrl_stress_all_with_rand_reset.56676942940320252940225540224418847100368697217497387701693103190938963995325","seed":56676942940320252940225540224418847100368697217497387701693103190938963995325,"line":3233,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1373607657 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1373607657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"47.lc_ctrl_stress_all_with_rand_reset.101799758836386130377003341945670429116103561594840048902016906940142728576807","seed":101799758836386130377003341945670429116103561594840048902016906940142728576807,"line":150,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 117281168 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 117281168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"48.lc_ctrl_stress_all_with_rand_reset.36682188118951224507995199673237527115320657702153066101533024460625456051461","seed":36682188118951224507995199673237527115320657702153066101533024460625456051461,"line":2144,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5768911848 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5768911848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:*":[{"name":"lc_ctrl_stress_all","qual_name":"16.lc_ctrl_stress_all.15574453893204892490309366081475616190210809962004572972869309396058006503986","seed":15574453893204892490309366081475616190210809962004572972869309396058006503986,"line":3196,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 6503729437 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000\n","UVM_INFO @ 6503729437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"45.lc_ctrl_stress_all_with_rand_reset.38727388786155841726478078199403906117267185701433299975391237651276766164093","seed":38727388786155841726478078199403906117267185701433299975391237651276766164093,"line":5778,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 10331169513 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error\n","UVM_INFO @ 10331169513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":996,"total":1030,"percent":96.69902912621359}