{"block":{"name":"uart","variant":null,"commit":"8007f614bd52d7ac557e5e3253489f0bf7b820c5","commit_short":"8007f61","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/8007f614bd52d7ac557e5e3253489f0bf7b820c5","revision_info":"GitHub Revision: [`8007f61`](https://github.com/lowrisc/opentitan/tree/8007f614bd52d7ac557e5e3253489f0bf7b820c5)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-24T16:00:28Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/uart/data/uart_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"uart_smoke":{"max_time":32.21,"sim_time":5888.476847,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"uart_csr_hw_reset":{"max_time":2.14,"sim_time":1031.876838,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"uart_csr_rw":{"max_time":0.92,"sim_time":15.271716,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"uart_csr_bit_bash":{"max_time":2.83,"sim_time":194.135882,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"uart_csr_aliasing":{"max_time":1.02,"sim_time":46.747651,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"uart_csr_mem_rw_with_rand_reset":{"max_time":1.51,"sim_time":30.845214,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"uart_csr_rw":{"max_time":0.92,"sim_time":15.271716,"passed":20,"total":20,"percent":100.0},"uart_csr_aliasing":{"max_time":1.02,"sim_time":46.747651,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":105,"total":105,"percent":100.0},"V2":{"testpoints":{"base_random_seq":{"tests":{"uart_tx_rx":{"max_time":236.54,"sim_time":73480.920982,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"parity":{"tests":{"uart_smoke":{"max_time":32.21,"sim_time":5888.476847,"passed":50,"total":50,"percent":100.0},"uart_tx_rx":{"max_time":236.54,"sim_time":73480.920982,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"parity_error":{"tests":{"uart_intr":{"max_time":558.72,"sim_time":407941.731468,"passed":50,"total":50,"percent":100.0},"uart_rx_parity_err":{"max_time":451.43,"sim_time":237663.085158,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"watermark":{"tests":{"uart_tx_rx":{"max_time":236.54,"sim_time":73480.920982,"passed":50,"total":50,"percent":100.0},"uart_intr":{"max_time":558.72,"sim_time":407941.731468,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"fifo_full":{"tests":{"uart_fifo_full":{"max_time":447.14,"sim_time":221378.90866699998,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"fifo_overflow":{"tests":{"uart_fifo_overflow":{"max_time":517.54,"sim_time":228994.37305599998,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"fifo_reset":{"tests":{"uart_fifo_reset":{"max_time":546.88,"sim_time":297378.549456,"passed":299,"total":300,"percent":99.66666666666667}},"passed":299,"total":300,"percent":99.66666666666667},"rx_frame_err":{"tests":{"uart_intr":{"max_time":558.72,"sim_time":407941.731468,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"rx_break_err":{"tests":{"uart_intr":{"max_time":558.72,"sim_time":407941.731468,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"rx_timeout":{"tests":{"uart_intr":{"max_time":558.72,"sim_time":407941.731468,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"perf":{"tests":{"uart_perf":{"max_time":1206.47,"sim_time":26671.160468,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sys_loopback":{"tests":{"uart_loopback":{"max_time":22.84,"sim_time":9576.466687,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"line_loopback":{"tests":{"uart_loopback":{"max_time":22.84,"sim_time":9576.466687,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"rx_noise_filter":{"tests":{"uart_noise_filter":{"max_time":171.26,"sim_time":82453.022428,"passed":5,"total":50,"percent":10.0}},"passed":5,"total":50,"percent":10.0},"rx_start_bit_filter":{"tests":{"uart_rx_start_bit_filter":{"max_time":76.21,"sim_time":46093.524004,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tx_overide":{"tests":{"uart_tx_ovrd":{"max_time":31.06,"sim_time":12981.465046,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"rx_oversample":{"tests":{"uart_rx_oversample":{"max_time":61.43,"sim_time":7021.725724999999,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"long_b2b_transfer":{"tests":{"uart_long_xfer_wo_dly":{"max_time":854.75,"sim_time":184935.08739700002,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all":{"tests":{"uart_stress_all":{"max_time":658.35,"sim_time":404157.75895499997,"passed":38,"total":50,"percent":76.0}},"passed":38,"total":50,"percent":76.0},"alert_test":{"tests":{"uart_alert_test":{"max_time":0.92,"sim_time":41.374106,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"uart_intr_test":{"max_time":0.89,"sim_time":29.321794,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"uart_tl_errors":{"max_time":1.9,"sim_time":535.342932,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"uart_tl_errors":{"max_time":1.9,"sim_time":535.342932,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"uart_csr_hw_reset":{"max_time":2.14,"sim_time":1031.876838,"passed":5,"total":5,"percent":100.0},"uart_csr_rw":{"max_time":0.92,"sim_time":15.271716,"passed":20,"total":20,"percent":100.0},"uart_csr_aliasing":{"max_time":1.02,"sim_time":46.747651,"passed":5,"total":5,"percent":100.0},"uart_same_csr_outstanding":{"max_time":1.04,"sim_time":63.159523,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"uart_csr_hw_reset":{"max_time":2.14,"sim_time":1031.876838,"passed":5,"total":5,"percent":100.0},"uart_csr_rw":{"max_time":0.92,"sim_time":15.271716,"passed":20,"total":20,"percent":100.0},"uart_csr_aliasing":{"max_time":1.02,"sim_time":46.747651,"passed":5,"total":5,"percent":100.0},"uart_same_csr_outstanding":{"max_time":1.04,"sim_time":63.159523,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":1112,"total":1170,"percent":95.04273504273505},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"uart_sec_cm":{"max_time":1.1,"sim_time":178.611742,"passed":5,"total":5,"percent":100.0},"uart_tl_intg_err":{"max_time":1.41,"sim_time":89.60442900000001,"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"uart_tl_intg_err":{"max_time":1.41,"sim_time":89.60442900000001,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"uart_stress_all_with_rand_reset":{"max_time":111.21,"sim_time":5078.312102,"passed":83,"total":100,"percent":83.0}},"passed":83,"total":100,"percent":83.0}},"passed":83,"total":100,"percent":83.0}},"coverage":{"code":{"block":null,"line_statement":99.48,"branch":98.14,"condition_expression":98.25,"toggle":91.55,"fsm":null},"assertion":97.12,"functional":99.59},"cov_report_page":"/nightly/current_run/scratch/master/uart-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *":[{"name":"uart_noise_filter","qual_name":"0.uart_noise_filter.70966186498289882581948459706990372512418326690163524438427002052519947818921","seed":70966186498289882581948459706990372512418326690163524438427002052519947818921,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 39269732357 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 39463479257 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 39463479257 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 39463479257 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 39519520027 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"0.uart_stress_all_with_rand_reset.70463236513787666917396977065181211833762538776609710248423423589994809437526","seed":70463236513787666917396977065181211833762538776609710248423423589994809437526,"line":108,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 642387350 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 648450044 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 649012562 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 649533412 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 650054262 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"2.uart_noise_filter.18060404471395137452899570009483229923900456583617265207454521441402938584514","seed":18060404471395137452899570009483229923900456583617265207454521441402938584514,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/2.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 10074867102 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 10074867102 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 10164094841 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 10164094841 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 10238739480 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n"]},{"name":"uart_stress_all","qual_name":"2.uart_stress_all.56775170016701698237916207498152129590084111850132458575266435234257211931450","seed":56775170016701698237916207498152129590084111850132458575266435234257211931450,"line":118,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/2.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 212032121497 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 212039911033 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 212043753169 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 212050700593 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 212055542737 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"4.uart_noise_filter.51748923902162618249022687401057606108738429603352868076465867962823968854046","seed":51748923902162618249022687401057606108738429603352868076465867962823968854046,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/4.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 2087945325 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2095875621 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2095875621 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 2192527557 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 2195260137 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"9.uart_noise_filter.105223787290957141040721834624122331747242894726750458670923434675675562749959","seed":105223787290957141040721834624122331747242894726750458670923434675675562749959,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/9.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 3971056031 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 3979117669 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 3983715483 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 4052713620 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 4053332160 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"11.uart_noise_filter.89442292291125060003161494778606222414592140999930880431130589228522313990884","seed":89442292291125060003161494778606222414592140999930880431130589228522313990884,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/11.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 5445883050 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 5445883050 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 5618363050 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr\n","UVM_ERROR @ 5693103050 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2,                                 clk_pulses: 0\n","UVM_ERROR @ 5693133050 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"13.uart_noise_filter.106405736722197294817776907202713702022916449797811868622180662227464427030081","seed":106405736722197294817776907202713702022916449797811868622180662227464427030081,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/13.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  11823634 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 304200973 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 304200973 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 977039689 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 1066582072 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"14.uart_noise_filter.72563115795003184429680961472299784353108615653534152275273607804028222345202","seed":72563115795003184429680961472299784353108615653534152275273607804028222345202,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/14.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  22639409 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 278824338 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4,                                 clk_pulses: 0\n","UVM_ERROR @ 278861375 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 278898412 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 63 [0x3f]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 412046427 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_noise_filter","qual_name":"15.uart_noise_filter.100499755957163042158416530651653704318606314401404011137397473926784205948665","seed":100499755957163042158416530651653704318606314401404011137397473926784205948665,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/15.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 22920609087 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 22921186017 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 22922609111 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 23080611007 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 23080611007 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"16.uart_noise_filter.26744102548480371276792605403437645057618685859222318632296528233065120463394","seed":26744102548480371276792605403437645057618685859222318632296528233065120463394,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/16.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 53941483080 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 53941483080 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 55092188160 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 55145289776 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n","UVM_ERROR @ 55270390816 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"19.uart_noise_filter.7375902135665506139536733232457299920082371111773166393442543808897155848357","seed":7375902135665506139536733232457299920082371111773166393442543808897155848357,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/19.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 3578379012 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 3619703251 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0\n","UVM_ERROR @ 3619713668 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 3619724085 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 247 [0xf7]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 3619734502 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_stress_all","qual_name":"22.uart_stress_all.82772791229365142803467780299315264302644987909984679215936473670665654139958","seed":82772791229365142803467780299315264302644987909984679215936473670665654139958,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/22.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 2515173666 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2523869266 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2529782274 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2879214960 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 17,                                 clk_pulses: 0\n","UVM_ERROR @ 2879258438 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"23.uart_noise_filter.93283244024736466935865452326151361137486123200672060396498487552662541918702","seed":93283244024736466935865452326151361137486123200672060396498487552662541918702,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/23.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 169515831 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 169515831 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 258095831 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 258425831 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 372585831 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"24.uart_noise_filter.72101664086927893290260225125728976818717379940081278112278089244753884801323","seed":72101664086927893290260225125728976818717379940081278112278089244753884801323,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/24.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  19198563 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  21998591 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  23198603 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  24162249 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  25125895 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"25.uart_noise_filter.26927262093822054869325393487147279687066207285104009546973588905302464340071","seed":26927262093822054869325393487147279687066207285104009546973588905302464340071,"line":81,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/25.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 71178636471 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 71178636471 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 72328886471 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 72563386471 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n","UVM_ERROR @ 73647823971 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"25.uart_stress_all_with_rand_reset.45967261535556539579618020850888239274719786103339227333445037948281595478693","seed":45967261535556539579618020850888239274719786103339227333445037948281595478693,"line":233,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/25.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 19480881541 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 19485173242 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 19489339942 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 19497215005 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 19503340054 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all","qual_name":"28.uart_stress_all.75559077117994810888091077535413854251153728696711807339784499390066376891761","seed":75559077117994810888091077535413854251153728696711807339784499390066376891761,"line":84,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/28.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 2327658212 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2327658212 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 2659961676 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr\n","UVM_ERROR @ 2659961676 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr\n","UVM_ERROR @ 2662369820 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr\n"]},{"name":"uart_noise_filter","qual_name":"29.uart_noise_filter.20186705652258290146759218929351859005116383107881331183960765138407936433515","seed":20186705652258290146759218929351859005116383107881331183960765138407936433515,"line":85,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/29.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 74534302457 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 74544844208 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 74655345092 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 74655345092 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 74655345092 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n"]},{"name":"uart_noise_filter","qual_name":"30.uart_noise_filter.88466764648166267992885448857556921940633099083044862884675905925801123308807","seed":88466764648166267992885448857556921940633099083044862884675905925801123308807,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/30.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 4161189171 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 4161189171 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 4207139171 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (216 [0xd8] vs 11 [0xb]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 4208109171 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 4365949171 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"32.uart_noise_filter.87011239218317512485162117685259915445080753953177550782404969732455915322339","seed":87011239218317512485162117685259915445080753953177550782404969732455915322339,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/32.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  72007503 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  72007503 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 169047810 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (113 [0x71] vs 197 [0xc5]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 179340729 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 216512409 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_noise_filter","qual_name":"33.uart_noise_filter.110224798035517958027625642638512817939761381720632683072058088226856938525495","seed":110224798035517958027625642638512817939761381720632683072058088226856938525495,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/33.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  15455401 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 104145739 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 104145739 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 110958457 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 110958457 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"38.uart_noise_filter.4079384402132710044101823624460245506167335466210787454234955081774828062584","seed":4079384402132710044101823624460245506167335466210787454234955081774828062584,"line":81,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/38.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 56580284621 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 56588100885 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 56596580409 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 56604559937 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 56604559937 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n"]},{"name":"uart_stress_all","qual_name":"39.uart_stress_all.19320879600561052179036675391736943930626483751204926919359201731477152983189","seed":19320879600561052179036675391736943930626483751204926919359201731477152983189,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/39.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 2016051224 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2016051224 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_INFO @ 3171979361 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 3/5\n","UVM_INFO @ 3388898336 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 4/5\n","UVM_INFO @ 4496058845 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 5/5\n"]},{"name":"uart_noise_filter","qual_name":"40.uart_noise_filter.109736403242792104437129089242840153805993440622719677430446774444169640952188","seed":109736403242792104437129089242840153805993440622719677430446774444169640952188,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/40.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 6846656717 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 6851495417 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 6858688951 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 6869592155 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 6882205033 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"40.uart_stress_all_with_rand_reset.107844876564133764002126952586637044549005876022326042215959824771850863414136","seed":107844876564133764002126952586637044549005876022326042215959824771850863414136,"line":227,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/40.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 17424051207 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 17426691207 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_INFO @ 17556491207 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/830\n","UVM_ERROR @ 17649851207 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_INFO @ 17941411207 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/830\n"]},{"name":"uart_noise_filter","qual_name":"43.uart_noise_filter.48236653010726235461069154770280070080617941826650239106753813949349719851886","seed":48236653010726235461069154770280070080617941826650239106753813949349719851886,"line":78,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/43.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 34768890770 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 34775390770 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 34782190770 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 34782890770 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 34797840770 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"45.uart_noise_filter.91123329397140985428844237002065671157497267716063668137497969990218129075739","seed":91123329397140985428844237002065671157497267716063668137497969990218129075739,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/45.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  10816387 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 121549097 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 149820835 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 10,                                 clk_pulses: 0\n","UVM_ERROR @ 149831252 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 149841669 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"47.uart_noise_filter.43150540683851401414314408343075310035853738844395720692122087312173924550061","seed":43150540683851401414314408343075310035853738844395720692122087312173924550061,"line":78,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/47.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 21238870927 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 21238870927 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 21861803236 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 8,                                 clk_pulses: 0\n","UVM_ERROR @ 21861946094 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (13 [0xd] vs 195 [0xc3]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 21862017523 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"49.uart_noise_filter.92907154677132567932951249251731679129800897793676588061748623365619530608570","seed":92907154677132567932951249251731679129800897793676588061748623365619530608570,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/49.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 4777881841 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 4777965173 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 4786548369 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 4786548369 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 4958524784 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"55.uart_stress_all_with_rand_reset.61764647217769015403273512273279863492805948194511282941630142395212761804614","seed":61764647217769015403273512273279863492805948194511282941630142395212761804614,"line":182,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/55.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3031323978 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 3031323978 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_INFO @ 3113847452 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/952\n","UVM_INFO @ 3228142776 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/952\n","UVM_ERROR @ 3245091235 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"77.uart_stress_all_with_rand_reset.64985818181550754462038840546066750686726512496375244402092895338832576888545","seed":64985818181550754462038840546066750686726512496375244402092895338832576888545,"line":181,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/77.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 27329455499 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 27329455499 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_INFO @ 27741071263 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Issuing reset for run 7/10\n","UVM_INFO @ 27741763570 ps: (cip_base_vseq.sv:1173) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"80.uart_stress_all_with_rand_reset.20408696859621919487431271777288442820817612803222495154105683526801930028374","seed":20408696859621919487431271777288442820817612803222495154105683526801930028374,"line":109,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/80.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4081998320 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_INFO @ 4091931754 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Issuing reset for run 4/5\n","UVM_INFO @ 4092051754 ps: (cip_base_vseq.sv:1173) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Stress w/ reset is done for run 4/5\n"]}],"UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = *":[{"name":"uart_stress_all","qual_name":"0.uart_stress_all.13957115208275236828104258462209094483354122659399682447088728408348201640719","seed":13957115208275236828104258462209094483354122659399682447088728408348201640719,"line":84,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 91369650474 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 91369650474 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 91369650474 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 91537126961 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2,                                 clk_pulses: 0\n","UVM_ERROR @ 91537168627 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (78 [0x4e] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"1.uart_noise_filter.65154248442341963411501483244642597395108062388473448812776028694079805973788","seed":65154248442341963411501483244642597395108062388473448812776028694079805973788,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/1.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 63302117750 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 63315717750 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 63315717750 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 63340517750 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 63364317750 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_noise_filter","qual_name":"5.uart_noise_filter.95009159199197535858303321095599495484151471342975124487118774670748170959373","seed":95009159199197535858303321095599495484151471342975124487118774670748170959373,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/5.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 354516998 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 354516998 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 354744273 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 354744273 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 360471603 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_stress_all","qual_name":"9.uart_stress_all.25435442901198504251785952054039668360300948385302142061880530884331240064162","seed":25435442901198504251785952054039668360300948385302142061880530884331240064162,"line":80,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/9.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 24075747431 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 24189188561 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 24192334495 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 24193074102 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 24196855473 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"10.uart_noise_filter.67122984937799292621061531048864044376275866155200213788133971240528607076411","seed":67122984937799292621061531048864044376275866155200213788133971240528607076411,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/10.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 2562052607 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 2562052607 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2562052607 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 3140172607 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 19,                                 clk_pulses: 0\n","UVM_ERROR @ 3140252607 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (81 [0x51] vs 223 [0xdf]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all","qual_name":"10.uart_stress_all.80820007286664060313491662059548908001593586327579665772994850087500026123777","seed":80820007286664060313491662059548908001593586327579665772994850087500026123777,"line":90,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/10.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 37120689441 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 37120689441 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 37120689441 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 37201769441 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4,                                 clk_pulses: 1\n","UVM_ERROR @ 37207519441 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (243 [0xf3] vs 253 [0xfd]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"28.uart_noise_filter.33520462825738928123346014604638753342899705923319120296790292734683267326783","seed":33520462825738928123346014604638753342899705923319120296790292734683267326783,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/28.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 48550902168 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 48550902168 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 48550902168 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 48559044960 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 48559840872 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"31.uart_noise_filter.10876042117121340898954091596149595161691111235800317301818622697377487176105","seed":10876042117121340898954091596149595161691111235800317301818622697377487176105,"line":81,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/31.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 44948270882 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 44948270882 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 44948270882 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 45538390882 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 5\n","UVM_ERROR @ 45538430882 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_stress_all","qual_name":"31.uart_stress_all.46378894337125029213808188979054409637004747975634046859236437012824476870145","seed":46378894337125029213808188979054409637004747975634046859236437012824476870145,"line":108,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/31.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 196061173876 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 196061173876 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 196061173876 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 196267024749 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 4,                                 clk_pulses: 0\n","UVM_ERROR @ 196267066415 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (198 [0xc6] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"35.uart_noise_filter.60827947140422172422875735370697621865894169950399748064127120859369804138880","seed":60827947140422172422875735370697621865894169950399748064127120859369804138880,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/35.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 1950072543 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 2334632543 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 36,                                 clk_pulses: 0\n","UVM_ERROR @ 2334672543 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (252 [0xfc] vs 251 [0xfb]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 2334692543 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 2334712543 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (252 [0xfc] vs 237 [0xed]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"36.uart_noise_filter.71567974028452173043012452936114085944289454956963402546240872190583761711740","seed":71567974028452173043012452936114085944289454956963402546240872190583761711740,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/36.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 71273032981 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 71273032981 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 71273032981 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 74118872006 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 3,                                 clk_pulses: 0\n","UVM_ERROR @ 74119872008 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (71 [0x47] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"37.uart_noise_filter.96218887793968521782515927297105444381931081322926814926145385099308246201963","seed":96218887793968521782515927297105444381931081322926814926145385099308246201963,"line":79,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/37.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 25873387590 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 25873387590 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 25873387590 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 25956187590 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 2\n","UVM_ERROR @ 25956227590 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"41.uart_noise_filter.15352559287707414769609792656912435026604311814195069627833411103340388324010","seed":15352559287707414769609792656912435026604311814195069627833411103340388324010,"line":78,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/41.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 18625086704 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 18625086704 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 18625086704 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 19222546210 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 26,                                 clk_pulses: 0\n","UVM_ERROR @ 19222617638 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (24 [0x18] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"42.uart_noise_filter.51836717643974942052103887597787793086497983567990651855434062507676766029938","seed":51836717643974942052103887597787793086497983567990651855434062507676766029938,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/42.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 307898550 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 307898550 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 307898550 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 312129370 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr\n","UVM_ERROR @ 312129370 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark\n"]},{"name":"uart_noise_filter","qual_name":"44.uart_noise_filter.33919287223396616727591591987160516876936694169088122851199982475075879606405","seed":33919287223396616727591591987160516876936694169088122851199982475075879606405,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/44.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 12047550494 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 12047550494 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 12114009359 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 12114009359 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 12114009359 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"47.uart_stress_all_with_rand_reset.1245414844437558049427878288685257355459333359185340951355860270735660364916","seed":1245414844437558049427878288685257355459333359185340951355860270735660364916,"line":78,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 147962269 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 147962269 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 158129017 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 158129017 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 163545727 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]}],"UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *":[{"name":"uart_noise_filter","qual_name":"3.uart_noise_filter.9959214427015359126912791535274735563828819851631461822839020561055592929614","seed":9959214427015359126912791535274735563828819851631461822839020561055592929614,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/3.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 129233411403 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0\n","UVM_ERROR @ 129233554260 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 129233697117 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 239 [0xef]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 129840982224 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 129840982224 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"6.uart_noise_filter.81627408351759710621794626781052373906692196752022873202723724098152126769150","seed":81627408351759710621794626781052373906692196752022873202723724098152126769150,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/6.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 131017935404 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0\n","UVM_ERROR @ 131017997904 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 131018060404 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (64 [0x40] vs 215 [0xd7]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 131018122904 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 131018185404 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (64 [0x40] vs 247 [0xf7]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"8.uart_noise_filter.20677998309094184871324029856053082191120727987080270669905694586334502658114","seed":20677998309094184871324029856053082191120727987080270669905694586334502658114,"line":84,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/8.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 23224765378 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0\n","UVM_ERROR @ 23224775378 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 23224785378 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (179 [0xb3] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 23225055378 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 23225065378 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"12.uart_noise_filter.53614524816006565647323605947172893944911392595070263191038562226401632601168","seed":53614524816006565647323605947172893944911392595070263191038562226401632601168,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/12.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  66183618 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @  66194729 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @  66205840 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 220804294 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0\n","UVM_ERROR @ 220815405 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"17.uart_noise_filter.73497118807123201953621438980284200238907529204751441482361675324784705632364","seed":73497118807123201953621438980284200238907529204751441482361675324784705632364,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/17.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 400497304 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4,                                 clk_pulses: 0\n","UVM_ERROR @ 400538971 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 400913974 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 254 [0xfe]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 400955641 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 401372311 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"17.uart_stress_all_with_rand_reset.11597415289949794527451875894375317394738724762919231345334537990633910803773","seed":11597415289949794527451875894375317394738724762919231345334537990633910803773,"line":107,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2260933037 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 10,                                 clk_pulses: 0\n","UVM_ERROR @ 2261036486 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 2261070969 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 111 [0x6f]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 2261174418 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 2261415799 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 63 [0x3f]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"20.uart_noise_filter.28075347576213380690391847397763108896107955502962682482229309985433860345609","seed":28075347576213380690391847397763108896107955502962682482229309985433860345609,"line":78,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/20.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 25069501414 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0\n","UVM_ERROR @ 25069527055 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 25069552696 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (209 [0xd1] vs 223 [0xdf]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 25069603978 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 25169142340 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 3,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"21.uart_noise_filter.53162149342915725884956812006452649757474902116713289140253218238034410290946","seed":53162149342915725884956812006452649757474902116713289140253218238034410290946,"line":82,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/21.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 21535598277 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 21535608586 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 21535618895 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 237 [0xed]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 21611668388 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0\n","UVM_ERROR @ 21611678697 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"22.uart_noise_filter.78423065743230852182636213694036466187655589737229857471569622035260499279725","seed":78423065743230852182636213694036466187655589737229857471569622035260499279725,"line":80,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/22.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 15088574544 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0\n","UVM_ERROR @ 15088594952 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 15088615360 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 15383959936 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 5,                                 clk_pulses: 0\n","UVM_ERROR @ 15383980344 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_stress_all","qual_name":"24.uart_stress_all.111782764365257736538723675454247427851199434710551273825837266162027408210053","seed":111782764365257736538723675454247427851199434710551273825837266162027408210053,"line":90,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/24.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 90144141903 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 6,                                 clk_pulses: 0\n","UVM_ERROR @ 90144162311 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 90144182719 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (104 [0x68] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 90229079999 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 11,                                 clk_pulses: 0\n","UVM_ERROR @ 90229100407 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"26.uart_noise_filter.21931770145603917773691721619404120550032639610412817150885465358786762161531","seed":21931770145603917773691721619404120550032639610412817150885465358786762161531,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/26.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 1327347868 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 9,                                 clk_pulses: 0\n","UVM_ERROR @ 1327386330 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 1327424792 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 250 [0xfa]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 1327463254 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 1327501716 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 247 [0xf7]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"36.uart_stress_all_with_rand_reset.96340233759322584178548651721677265193597886995698168748626416574206524873925","seed":96340233759322584178548651721677265193597886995698168748626416574206524873925,"line":171,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 9424783670 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 9424823670 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 9425023670 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 251 [0xfb]) reg name: uart_reg_block.rdata\n","UVM_INFO @ 9676863670 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/401\n","UVM_ERROR @ 9824423670 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 7,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"48.uart_noise_filter.105636529677214938042093275489819894304155683691779790749511577215683851440515","seed":105636529677214938042093275489819894304155683691779790749511577215683851440515,"line":81,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/48.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 19428715379 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 6,                                 clk_pulses: 0\n","UVM_ERROR @ 19428735787 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 19428756195 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (151 [0x97] vs 127 [0x7f]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 19428776603 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 19428837827 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (151 [0x97] vs 246 [0xf6]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"70.uart_stress_all_with_rand_reset.39921819082431828214927033814930247714648312317699541716755125367654881660726","seed":39921819082431828214927033814930247714648312317699541716755125367654881660726,"line":122,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5833331887 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4,                                 clk_pulses: 0\n","UVM_ERROR @ 5833373554 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 5833415221 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 5833456888 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 5833540222 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 191 [0xbf]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"79.uart_stress_all_with_rand_reset.18814947707314166543708343631514525349193108435739959029024739346742350789906","seed":18814947707314166543708343631514525349193108435739959029024739346742350789906,"line":78,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/79.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 259717346 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 259737754 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 259901018 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 127 [0x7f]) reg name: uart_reg_block.rdata\n","UVM_INFO @ 401287642 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/650\n","UVM_ERROR @ 447226050 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"88.uart_stress_all_with_rand_reset.6404354211596878753308400446323639810326740436917936269370418084861082469244","seed":6404354211596878753308400446323639810326740436917936269370418084861082469244,"line":85,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/88.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 652048263 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 652058680 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 652069097 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 254 [0xfe]) reg name: uart_reg_block.rdata\n","UVM_INFO @ 657090091 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/590\n","UVM_INFO @ 668959820 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"95.uart_stress_all_with_rand_reset.91956565179023885915440898665765838455164927847623132295235244608780171227734","seed":91956565179023885915440898665765838455164927847623132295235244608780171227734,"line":126,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/95.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2065514843 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0\n","UVM_ERROR @ 2065525260 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 2065535677 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_INFO @ 2073275508 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/430\n","UVM_ERROR @ 2073567184 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0\n"]}],"UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty":[{"name":"uart_stress_all","qual_name":"3.uart_stress_all.1666325199550732664126060177145567706206815788708605944435769440187781488428","seed":1666325199550732664126060177145567706206815788708605944435769440187781488428,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/3.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @   3191093 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty\n","UVM_INFO @ 18337921965 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 1/9\n","UVM_INFO @ 19062018213 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 2/9\n","UVM_INFO @ 19254016677 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 3/9\n","UVM_INFO @ 19256241149 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 4/9\n"]},{"name":"uart_stress_all","qual_name":"34.uart_stress_all.73428203913913366326936249565684251413810609468855149037213511190904883106487","seed":73428203913913366326936249565684251413810609468855149037213511190904883106487,"line":85,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/34.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 133348748060 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty\n","UVM_INFO @ 206532121992 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 1/19\n","UVM_INFO @ 208493197481 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 2/19\n","UVM_INFO @ 228261285075 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 3/19\n","UVM_INFO @ 228964115597 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 4/19\n"]},{"name":"uart_stress_all","qual_name":"44.uart_stress_all.17350349322110795132344915506246600107265097659171282015418734448747217942234","seed":17350349322110795132344915506246600107265097659171282015418734448747217942234,"line":87,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/44.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 5887172781 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty\n","UVM_INFO @ 8147819083 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/7\n","UVM_INFO @ 10748583171 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/7\n","UVM_INFO @ 12484989937 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/7\n","UVM_INFO @ 59125772306 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 5/7\n"]},{"name":"uart_fifo_reset","qual_name":"262.uart_fifo_reset.59317777799719252844990048331557455181219068970953012272932991506632596644148","seed":59317777799719252844990048331557455181219068970953012272932991506632596644148,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/262.uart_fifo_reset/latest/run.log","log_context":["UVM_ERROR @   1334124 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty\n","UVM_INFO @ 3082571995 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/9\n","UVM_INFO @ 3353733064 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/9\n","UVM_INFO @ 5470561217 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/9\n","UVM_INFO @ 5691964382 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/9\n"]}],"UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr":[{"name":"uart_stress_all_with_rand_reset","qual_name":"5.uart_stress_all_with_rand_reset.48459483669425634044792026169723422037897701392165243345474984534557013778871","seed":48459483669425634044792026169723422037897701392165243345474984534557013778871,"line":128,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/5.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6448284987 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr\n","UVM_ERROR @ 6448284987 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr\n","UVM_ERROR @ 6448284987 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark\n","UVM_INFO @ 6487841860 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Issuing reset for run 4/5\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"13.uart_stress_all_with_rand_reset.88081662353131442465763942369910974519913199957242347178012251687596331919761","seed":88081662353131442465763942369910974519913199957242347178012251687596331919761,"line":90,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 126855278 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr\n","UVM_ERROR @ 126855278 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr\n","UVM_ERROR @ 126855278 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark\n","UVM_ERROR @ 128355326 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark\n","UVM_INFO @ 161460552 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/443\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"99.uart_stress_all_with_rand_reset.65351980380620862677363672281241441369300943539659163277656030928204775943828","seed":65351980380620862677363672281241441369300943539659163277656030928204775943828,"line":172,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/99.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 11171280934 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr\n","UVM_ERROR @ 11171280934 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr\n","UVM_INFO @ 11229906403 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/254\n","UVM_ERROR @ 11496700204 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_INFO @ 11528325457 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/254\n"]}],"UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxFrameErr":[{"name":"uart_noise_filter","qual_name":"39.uart_noise_filter.5291400549288872061910365720460885124132988640219024370682068916571717511074","seed":5291400549288872061910365720460885124132988640219024370682068916571717511074,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/39.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 789723948 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr\n","UVM_ERROR @ 789723948 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr\n","UVM_ERROR @ 1294471929 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 16,                                 clk_pulses: 0\n","UVM_ERROR @ 1294555262 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 1294638595 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 207 [0xcf]) reg name: uart_reg_block.rdata\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"uart_stress_all_with_rand_reset","qual_name":"82.uart_stress_all_with_rand_reset.10290111674473512303297228865409328628470436134367706909854160616917842544124","seed":10290111674473512303297228865409328628470436134367706909854160616917842544124,"line":79,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/82.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 156802034 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 156811410 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 156811410 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 156812135 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2\n"]}]}},"passed":1245,"total":1320,"percent":94.31818181818181}