{"block":{"name":"alert_handler","variant":null,"commit":"1521b5f2d5d90c126b1cbab588514f5ecff12f40","commit_short":"1521b5f","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/1521b5f2d5d90c126b1cbab588514f5ecff12f40","revision_info":"GitHub Revision: [`1521b5f`](https://github.com/lowrisc/opentitan/tree/1521b5f2d5d90c126b1cbab588514f5ecff12f40)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-01T16:00:28Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_darjeeling/ip_autogen/alert_handler/data/alert_handler_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"alert_handler_smoke":{"max_time":63.03,"sim_time":3292.4957769999996,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"alert_handler_csr_hw_reset":{"max_time":12.91,"sim_time":118.287313,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"alert_handler_csr_rw":{"max_time":13.27,"sim_time":579.567366,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"alert_handler_csr_bit_bash":{"max_time":541.47,"sim_time":9778.201978000001,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"alert_handler_csr_aliasing":{"max_time":338.95,"sim_time":30270.709763,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"alert_handler_csr_mem_rw_with_rand_reset":{"max_time":18.67,"sim_time":807.785041,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"alert_handler_csr_rw":{"max_time":13.27,"sim_time":579.567366,"passed":20,"total":20,"percent":100.0},"alert_handler_csr_aliasing":{"max_time":338.95,"sim_time":30270.709763,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":105,"total":105,"percent":100.0},"V2":{"testpoints":{"esc_accum":{"tests":{"alert_handler_esc_alert_accum":{"max_time":387.85,"sim_time":30812.332558,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"esc_timeout":{"tests":{"alert_handler_esc_intr_timeout":{"max_time":74.47,"sim_time":4297.403586,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"entropy":{"tests":{"alert_handler_entropy":{"max_time":3269.28,"sim_time":59129.443659000004,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0},"sig_int_fail":{"tests":{"alert_handler_sig_int_fail":{"max_time":67.34,"sim_time":1907.444598,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"clk_skew":{"tests":{"alert_handler_smoke":{"max_time":63.03,"sim_time":3292.4957769999996,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"random_alerts":{"tests":{"alert_handler_random_alerts":{"max_time":92.39,"sim_time":5962.162404,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"random_classes":{"tests":{"alert_handler_random_classes":{"max_time":108.46,"sim_time":1437.526466,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"ping_timeout":{"tests":{"alert_handler_ping_timeout":{"max_time":642.92,"sim_time":91279.34821899999,"passed":19,"total":50,"percent":38.0}},"passed":19,"total":50,"percent":38.0},"lpg":{"tests":{"alert_handler_lpg":{"max_time":3505.23,"sim_time":259416.69191099997,"passed":48,"total":50,"percent":96.0},"alert_handler_lpg_stub_clk":{"max_time":2722.09,"sim_time":203051.980274,"passed":50,"total":50,"percent":100.0}},"passed":98,"total":100,"percent":98.0},"stress_all":{"tests":{"alert_handler_stress_all":{"max_time":3113.87,"sim_time":67019.886343,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0},"alert_handler_entropy_stress_test":{"tests":{"alert_handler_entropy_stress":{"max_time":89.66,"sim_time":4022.061946,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"alert_handler_alert_accum_saturation":{"tests":{"alert_handler_alert_accum_saturation":{"max_time":5.55,"sim_time":53.164069000000005,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"intr_test":{"tests":{"alert_handler_intr_test":{"max_time":2.48,"sim_time":15.951606,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"alert_handler_tl_errors":{"max_time":32.7,"sim_time":1315.341093,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"alert_handler_tl_errors":{"max_time":32.7,"sim_time":1315.341093,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"alert_handler_csr_hw_reset":{"max_time":12.91,"sim_time":118.287313,"passed":5,"total":5,"percent":100.0},"alert_handler_csr_rw":{"max_time":13.27,"sim_time":579.567366,"passed":20,"total":20,"percent":100.0},"alert_handler_csr_aliasing":{"max_time":338.95,"sim_time":30270.709763,"passed":5,"total":5,"percent":100.0},"alert_handler_same_csr_outstanding":{"max_time":59.16,"sim_time":2994.180753,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"alert_handler_csr_hw_reset":{"max_time":12.91,"sim_time":118.287313,"passed":5,"total":5,"percent":100.0},"alert_handler_csr_rw":{"max_time":13.27,"sim_time":579.567366,"passed":20,"total":20,"percent":100.0},"alert_handler_csr_aliasing":{"max_time":338.95,"sim_time":30270.709763,"passed":5,"total":5,"percent":100.0},"alert_handler_same_csr_outstanding":{"max_time":59.16,"sim_time":2994.180753,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":675,"total":710,"percent":95.07042253521126},"V2S":{"testpoints":{"shadow_reg_update_error":{"tests":{"alert_handler_shadow_reg_errors":{"max_time":326.74,"sim_time":23172.209477,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_read_clear_staged_value":{"tests":{"alert_handler_shadow_reg_errors":{"max_time":326.74,"sim_time":23172.209477,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_storage_error":{"tests":{"alert_handler_shadow_reg_errors":{"max_time":326.74,"sim_time":23172.209477,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadowed_reset_glitch":{"tests":{"alert_handler_shadow_reg_errors":{"max_time":326.74,"sim_time":23172.209477,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_update_error_with_csr_rw":{"tests":{"alert_handler_shadow_reg_errors_with_csr_rw":{"max_time":1246.02,"sim_time":71876.026647,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_intg_err":{"tests":{"alert_handler_sec_cm":{"max_time":43.25,"sim_time":1261.0956529999999,"passed":5,"total":5,"percent":100.0},"alert_handler_tl_intg_err":{"max_time":101.09,"sim_time":7699.418417999999,"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"alert_handler_tl_intg_err":{"max_time":101.09,"sim_time":7699.418417999999,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_config_shadow":{"tests":{"alert_handler_shadow_reg_errors":{"max_time":326.74,"sim_time":23172.209477,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_ping_timer_config_regwen":{"tests":{"alert_handler_smoke":{"max_time":63.03,"sim_time":3292.4957769999996,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_alert_config_regwen":{"tests":{"alert_handler_smoke":{"max_time":63.03,"sim_time":3292.4957769999996,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_alert_loc_config_regwen":{"tests":{"alert_handler_smoke":{"max_time":63.03,"sim_time":3292.4957769999996,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_class_config_regwen":{"tests":{"alert_handler_smoke":{"max_time":63.03,"sim_time":3292.4957769999996,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_alert_intersig_diff":{"tests":{"alert_handler_sig_int_fail":{"max_time":67.34,"sim_time":1907.444598,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_lpg_intersig_mubi":{"tests":{"alert_handler_lpg":{"max_time":3505.23,"sim_time":259416.69191099997,"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0},"sec_cm_esc_intersig_diff":{"tests":{"alert_handler_sig_int_fail":{"max_time":67.34,"sim_time":1907.444598,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_alert_rx_intersig_bkgn_chk":{"tests":{"alert_handler_entropy":{"max_time":3269.28,"sim_time":59129.443659000004,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0},"sec_cm_esc_tx_intersig_bkgn_chk":{"tests":{"alert_handler_entropy":{"max_time":3269.28,"sim_time":59129.443659000004,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0},"sec_cm_esc_timer_fsm_sparse":{"tests":{"alert_handler_sec_cm":{"max_time":43.25,"sim_time":1261.0956529999999,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ping_timer_fsm_sparse":{"tests":{"alert_handler_sec_cm":{"max_time":43.25,"sim_time":1261.0956529999999,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_esc_timer_fsm_local_esc":{"tests":{"alert_handler_sec_cm":{"max_time":43.25,"sim_time":1261.0956529999999,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ping_timer_fsm_local_esc":{"tests":{"alert_handler_sec_cm":{"max_time":43.25,"sim_time":1261.0956529999999,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_esc_timer_fsm_global_esc":{"tests":{"alert_handler_sec_cm":{"max_time":43.25,"sim_time":1261.0956529999999,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_accu_ctr_redun":{"tests":{"alert_handler_sec_cm":{"max_time":43.25,"sim_time":1261.0956529999999,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_esc_timer_ctr_redun":{"tests":{"alert_handler_sec_cm":{"max_time":43.25,"sim_time":1261.0956529999999,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ping_timer_ctr_redun":{"tests":{"alert_handler_sec_cm":{"max_time":43.25,"sim_time":1261.0956529999999,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ping_timer_lfsr_redun":{"tests":{"alert_handler_sec_cm":{"max_time":43.25,"sim_time":1261.0956529999999,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0}},"passed":262,"total":265,"percent":98.86792452830188},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"alert_handler_stress_all_with_rand_reset":{"max_time":614.74,"sim_time":10428.687059,"passed":26,"total":50,"percent":52.0}},"passed":26,"total":50,"percent":52.0}},"passed":26,"total":50,"percent":52.0}},"coverage":{"code":{"block":null,"line_statement":99.99,"branch":99.99,"condition_expression":97.54,"toggle":96.69,"fsm":100.0},"assertion":98.92,"functional":99.36},"cov_report_page":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"0.alert_handler_stress_all_with_rand_reset.66275175223572598873390088621206284570873106724858053050451329517148146590714","seed":66275175223572598873390088621206284570873106724858053050451329517148146590714,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 134489391 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 134489391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"5.alert_handler_stress_all_with_rand_reset.103833274917497106756240662261314360128548093673581625362793193332107837733115","seed":103833274917497106756240662261314360128548093673581625362793193332107837733115,"line":368,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 90407921300 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 90407921300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"7.alert_handler_stress_all_with_rand_reset.65597904417738324545444099819774902695185497298844775899057573814402434896818","seed":65597904417738324545444099819774902695185497298844775899057573814402434896818,"line":122,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2295061741 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2295061741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"8.alert_handler_stress_all_with_rand_reset.113478931084941321996351771796235759340190133251823687569292074380198284535513","seed":113478931084941321996351771796235759340190133251823687569292074380198284535513,"line":219,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7298260057 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 7298260057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"10.alert_handler_stress_all_with_rand_reset.41536585530798295989280207825983059873876640453352158749576555307713335301744","seed":41536585530798295989280207825983059873876640453352158749576555307713335301744,"line":164,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2860146331 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2860146331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"12.alert_handler_stress_all_with_rand_reset.4109130482330134072511818126062280494016744101145556897413804040091580772460","seed":4109130482330134072511818126062280494016744101145556897413804040091580772460,"line":160,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2477761149 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2477761149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"13.alert_handler_stress_all_with_rand_reset.72028826638383378886854892047124044605855948906052437991027281417797353931512","seed":72028826638383378886854892047124044605855948906052437991027281417797353931512,"line":212,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 9310686129 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 9310686129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"15.alert_handler_stress_all_with_rand_reset.12078965599243004496818600195254492959834702269070223620430072119492336260810","seed":12078965599243004496818600195254492959834702269070223620430072119492336260810,"line":123,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 9819394350 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 9819394350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"17.alert_handler_stress_all_with_rand_reset.107569895783847817512723315630941594026544034746511724233381264305671382886249","seed":107569895783847817512723315630941594026544034746511724233381264305671382886249,"line":150,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 49380518972 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 49380518972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"19.alert_handler_stress_all_with_rand_reset.31483479706723376065309443427561947928660930119389985373457759478621519310538","seed":31483479706723376065309443427561947928660930119389985373457759478621519310538,"line":101,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1783194768 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1783194768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"20.alert_handler_stress_all_with_rand_reset.85509728842237850919264199212637375639837703821349671713112200944879520773130","seed":85509728842237850919264199212637375639837703821349671713112200944879520773130,"line":148,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8670105908 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 8670105908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"21.alert_handler_stress_all_with_rand_reset.106104415591032025287829564957497893773352345015130521538428773381674940230357","seed":106104415591032025287829564957497893773352345015130521538428773381674940230357,"line":83,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 127968559 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 127968559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"24.alert_handler_stress_all_with_rand_reset.87028754111388550772114819272385618904070955031929507822856203771073239517801","seed":87028754111388550772114819272385618904070955031929507822856203771073239517801,"line":121,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 898114026 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 898114026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"26.alert_handler_stress_all_with_rand_reset.27231507973280097776745005380541613441365186098290898248658485267510593770052","seed":27231507973280097776745005380541613441365186098290898248658485267510593770052,"line":94,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/26.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 364893011 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 364893011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"28.alert_handler_stress_all_with_rand_reset.70770237134466704470471115588382335669128165474502024928972116666353205099487","seed":70770237134466704470471115588382335669128165474502024928972116666353205099487,"line":85,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/28.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 110384513 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 110384513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"30.alert_handler_stress_all_with_rand_reset.87347993709076110906966735264650643939622721856623191713960499996753394321002","seed":87347993709076110906966735264650643939622721856623191713960499996753394321002,"line":91,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/30.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 933066107 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 933066107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"33.alert_handler_stress_all_with_rand_reset.81603479509195919275435668685661776839301907342674334093935670152405785929627","seed":81603479509195919275435668685661776839301907342674334093935670152405785929627,"line":88,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/33.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 355835879 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 355835879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"35.alert_handler_stress_all_with_rand_reset.98695475045541306776068508131633306646434437586448261842062103906409365667412","seed":98695475045541306776068508131633306646434437586448261842062103906409365667412,"line":111,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/35.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4619611089 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4619611089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"38.alert_handler_stress_all_with_rand_reset.23449679932848286862044004954991989293218085750372565129692021826164822650033","seed":23449679932848286862044004954991989293218085750372565129692021826164822650033,"line":125,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/38.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1784304743 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1784304743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"39.alert_handler_stress_all_with_rand_reset.22437197880321121811471536194441062847033817042002376287550315558159272940931","seed":22437197880321121811471536194441062847033817042002376287550315558159272940931,"line":162,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/39.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6097151832 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 6097151832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"43.alert_handler_stress_all_with_rand_reset.80192057006643466301773114744522027863513045387501674463856984539457722985254","seed":80192057006643466301773114744522027863513045387501674463856984539457722985254,"line":138,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/43.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3328518546 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3328518546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"45.alert_handler_stress_all_with_rand_reset.55146730647651511605189196829182477795736513043220712339660170170246524041672","seed":55146730647651511605189196829182477795736513043220712339660170170246524041672,"line":96,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/45.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 683469114 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 683469114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"46.alert_handler_stress_all_with_rand_reset.35063510995774931588314371133535551964938287787214048311865281779285117104904","seed":35063510995774931588314371133535551964938287787214048311865281779285117104904,"line":90,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 503590098 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 503590098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state":[{"name":"alert_handler_lpg","qual_name":"2.alert_handler_lpg.22093192815164153172514903242537194373020127465775937362682575621943545681450","seed":22093192815164153172514903242537194373020127465775937362682575621943545681450,"line":85,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_lpg/latest/run.log","log_context":["UVM_ERROR @ 218836062048 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 218836062048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"4.alert_handler_ping_timeout.99531836100246981154044105992401197391498879207005494532578815772240664486931","seed":99531836100246981154044105992401197391498879207005494532578815772240664486931,"line":87,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 1297421971 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 1297421971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"5.alert_handler_ping_timeout.4569381032672788644251069736444349236733969419363663877008927407205480141723","seed":4569381032672788644251069736444349236733969419363663877008927407205480141723,"line":108,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 13023098646 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 13023098646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"8.alert_handler_ping_timeout.83298972824006101469817973147506674747979771460699412362680399309073045045943","seed":83298972824006101469817973147506674747979771460699412362680399309073045045943,"line":105,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 14224328755 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 14224328755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"11.alert_handler_ping_timeout.57830426782373846362629432912426319698041228516552180637999743065189690316361","seed":57830426782373846362629432912426319698041228516552180637999743065189690316361,"line":96,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 25000486365 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 25000486365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"14.alert_handler_ping_timeout.86211191010267476335710225884604789960400480196853717549580483400276335118645","seed":86211191010267476335710225884604789960400480196853717549580483400276335118645,"line":86,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 4116219028 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 4116219028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all","qual_name":"14.alert_handler_stress_all.39748110553407402411096613280776470815107554583066601215476732202892347112353","seed":39748110553407402411096613280776470815107554583066601215476732202892347112353,"line":236,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_stress_all/latest/run.log","log_context":["UVM_ERROR @ 26139334802 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (11 [0xb] vs 15 [0xf]) reg name: intr_state\n","UVM_INFO @ 26139334802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"17.alert_handler_ping_timeout.10141857483219051352149943920936486371750924055093816848810279294495069341983","seed":10141857483219051352149943920936486371750924055093816848810279294495069341983,"line":97,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 4517913424 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 4517913424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"19.alert_handler_ping_timeout.111484484517067997829636231775477626709594847454632093356492751793678949746832","seed":111484484517067997829636231775477626709594847454632093356492751793678949746832,"line":90,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 2444055766 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 2444055766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"20.alert_handler_ping_timeout.13476410911706502445944013606633803325804035109558375699476086251542053117287","seed":13476410911706502445944013606633803325804035109558375699476086251542053117287,"line":102,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 4445533611 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 4445533611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"21.alert_handler_ping_timeout.14101156437080460248532943042278840880608108247903915591503127235011968288257","seed":14101156437080460248532943042278840880608108247903915591503127235011968288257,"line":117,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 7897716974 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 7897716974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"22.alert_handler_ping_timeout.44603757608785503539166434008484060065375504276006032178232839773914667519178","seed":44603757608785503539166434008484060065375504276006032178232839773914667519178,"line":114,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 6138413963 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 6138413963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"23.alert_handler_ping_timeout.60895334141036173446809306288357143880054982204283781400337411498115362922763","seed":60895334141036173446809306288357143880054982204283781400337411498115362922763,"line":102,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 28896662241 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 28896662241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"24.alert_handler_ping_timeout.14034870002765885831031648548884920754795179444375841300299556696000118538839","seed":14034870002765885831031648548884920754795179444375841300299556696000118538839,"line":108,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 12390344448 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 12390344448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"25.alert_handler_ping_timeout.109472494950493572710891483417702043854140960095116235751659514525561815817681","seed":109472494950493572710891483417702043854140960095116235751659514525561815817681,"line":142,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/25.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 26731722837 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 26731722837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"27.alert_handler_ping_timeout.108561859602886811597608371692828105133871761742663004801638261079276193405132","seed":108561859602886811597608371692828105133871761742663004801638261079276193405132,"line":87,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 1535801335 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 1535801335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"29.alert_handler_ping_timeout.34673664313663773540891015086566051391487410433207051357674668915149406730411","seed":34673664313663773540891015086566051391487410433207051357674668915149406730411,"line":93,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/29.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 2556718506 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 2556718506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"30.alert_handler_ping_timeout.112071961322579205862000803804827918457875554339578586878876780946281287657805","seed":112071961322579205862000803804827918457875554339578586878876780946281287657805,"line":96,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/30.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 10354176599 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 10354176599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"32.alert_handler_ping_timeout.111230952280509919381311700450099924824669387790424416088029309050323477697069","seed":111230952280509919381311700450099924824669387790424416088029309050323477697069,"line":123,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 10841423938 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 10841423938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"35.alert_handler_ping_timeout.39102815066309634475615632579465209104334656412509906752851342926690107833146","seed":39102815066309634475615632579465209104334656412509906752851342926690107833146,"line":129,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 28502800515 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 28502800515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"37.alert_handler_ping_timeout.70352516888334317399945151968468355514585916957567534784163557861851079255607","seed":70352516888334317399945151968468355514585916957567534784163557861851079255607,"line":126,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 16046224979 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 16046224979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"38.alert_handler_ping_timeout.39981655956799400670074654323577772299936265705180080836508277884355442107717","seed":39981655956799400670074654323577772299936265705180080836508277884355442107717,"line":90,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 34650567464 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 34650567464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"41.alert_handler_ping_timeout.66655952860104522736657192393053076343389744891862717081666904825480297111699","seed":66655952860104522736657192393053076343389744891862717081666904825480297111699,"line":102,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 4809884675 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 4809884675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"42.alert_handler_ping_timeout.64902738464227667584700777559042145246667177399131744434383240894758394143329","seed":64902738464227667584700777559042145246667177399131744434383240894758394143329,"line":153,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/42.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 18359613372 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 18359613372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"44.alert_handler_ping_timeout.23402390597622841513392137845388499544175054786578295996368597927106876707759","seed":23402390597622841513392137845388499544175054786578295996368597927106876707759,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/44.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 3809712381 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 3809712381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"45.alert_handler_ping_timeout.111736919009627965210761913248411018988639968275768948782831429188931557585330","seed":111736919009627965210761913248411018988639968275768948782831429188931557585330,"line":133,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 27147293786 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 27147293786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"46.alert_handler_ping_timeout.59797186443009201805426979157801352386963424047887212478502509808931312154205","seed":59797186443009201805426979157801352386963424047887212478502509808931312154205,"line":90,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 2384179794 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 2384179794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"47.alert_handler_ping_timeout.92173339733687700937360894214870076814068589371148304264287525763950230030161","seed":92173339733687700937360894214870076814068589371148304264287525763950230030161,"line":128,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 38814152958 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 38814152958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"49.alert_handler_ping_timeout.44468097562657360047683764307597794141313018266248589495172611603623409926567","seed":44468097562657360047683764307597794141313018266248589495172611603623409926567,"line":93,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 2025604354 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 2025604354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"alert_handler_entropy","qual_name":"6.alert_handler_entropy.29254795067844622692569139589973291933008457416231908589805213248242092015133","seed":29254795067844622692569139589973291933008457416231908589805213248242092015133,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_entropy/latest/run.log","log_context":["UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model.":[{"name":"alert_handler_ping_timeout","qual_name":"9.alert_handler_ping_timeout.69379071772056236672991683656486913412483535155993188394852283579322860949356","seed":69379071772056236672991683656486913412483535155993188394852283579322860949356,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 1123146960 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 1123146960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"13.alert_handler_ping_timeout.76864862320403143283259494785952249674287745453785079316485567835675025697748","seed":76864862320403143283259494785952249674287745453785079316485567835675025697748,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 200659127 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 200659127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"15.alert_handler_ping_timeout.4080999532444827256929357888529783167117495546422778574628353585533410059270","seed":4080999532444827256929357888529783167117495546422778574628353585533410059270,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 331858486 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 331858486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"16.alert_handler_ping_timeout.114023534694623158284855795342816598014370781695936430874917892479389753046553","seed":114023534694623158284855795342816598014370781695936430874917892479389753046553,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 1008813676 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 1008813676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_lpg","qual_name":"27.alert_handler_lpg.96339575957222342002073152111940396785615640477510144287183842425161264395313","seed":96339575957222342002073152111940396785615640477510144287183842425161264395313,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_lpg/latest/run.log","log_context":["UVM_ERROR @ 5146332101 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 5146332101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_state":[{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"18.alert_handler_stress_all_with_rand_reset.81211654662443751055559325678042532773108284548519962745592078180392705922401","seed":81211654662443751055559325678042532773108284548519962745592078180392705922401,"line":111,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5104085051 ps: (alert_handler_scoreboard.sv:490) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (7 [0x7] vs 3 [0x3]) reg name: alert_handler_reg_block.classb_state\n","UVM_INFO @ 5104085051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":791,"total":850,"percent":93.05882352941177}