{"block":{"name":"clkmgr","variant":null,"commit":"1521b5f2d5d90c126b1cbab588514f5ecff12f40","commit_short":"1521b5f","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/1521b5f2d5d90c126b1cbab588514f5ecff12f40","revision_info":"GitHub Revision: [`1521b5f`](https://github.com/lowrisc/opentitan/tree/1521b5f2d5d90c126b1cbab588514f5ecff12f40)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-01T16:00:28Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"clkmgr_smoke":{"max_time":2.44,"sim_time":188.31348300000002,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.71,"sim_time":106.491098,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"clkmgr_csr_rw":{"max_time":1.25,"sim_time":48.358278,"passed":11,"total":20,"percent":55.0}},"passed":11,"total":20,"percent":55.0},"csr_bit_bash":{"tests":{"clkmgr_csr_bit_bash":{"max_time":4.87,"sim_time":399.641817,"passed":0,"total":5,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"csr_aliasing":{"tests":{"clkmgr_csr_aliasing":{"max_time":4.15,"sim_time":397.639392,"passed":2,"total":5,"percent":40.0}},"passed":2,"total":5,"percent":40.0},"csr_mem_rw_with_rand_reset":{"tests":{"clkmgr_csr_mem_rw_with_rand_reset":{"max_time":2.28,"sim_time":116.865864,"passed":8,"total":20,"percent":40.0}},"passed":8,"total":20,"percent":40.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"clkmgr_csr_rw":{"max_time":1.25,"sim_time":48.358278,"passed":11,"total":20,"percent":55.0},"clkmgr_csr_aliasing":{"max_time":4.15,"sim_time":397.639392,"passed":2,"total":5,"percent":40.0}},"passed":13,"total":25,"percent":52.0}},"passed":76,"total":105,"percent":72.38095238095238},"V2":{"testpoints":{"peri_enables":{"tests":{"clkmgr_peri":{"max_time":1.98,"sim_time":144.687705,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"trans_enables":{"tests":{"clkmgr_trans":{"max_time":5.38,"sim_time":535.165891,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"clk_status":{"tests":{"clkmgr_clk_status":{"max_time":2.17,"sim_time":173.91031700000002,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"jitter":{"tests":{"clkmgr_smoke":{"max_time":2.44,"sim_time":188.31348300000002,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"frequency":{"tests":{"clkmgr_frequency":{"max_time":1.22,"sim_time":57.329889,"passed":1,"total":50,"percent":2.0}},"passed":1,"total":50,"percent":2.0},"frequency_timeout":{"tests":{"clkmgr_frequency_timeout":{"max_time":0.84,"sim_time":12.638492,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":50,"percent":0.0},"frequency_overflow":{"tests":{"clkmgr_frequency":{"max_time":1.22,"sim_time":57.329889,"passed":1,"total":50,"percent":2.0}},"passed":1,"total":50,"percent":2.0},"stress_all":{"tests":{"clkmgr_stress_all":{"max_time":4.91,"sim_time":425.758842,"passed":3,"total":50,"percent":6.0}},"passed":3,"total":50,"percent":6.0},"alert_test":{"tests":{"clkmgr_alert_test":{"max_time":1.99,"sim_time":134.26310500000002,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"clkmgr_tl_errors":{"max_time":5.12,"sim_time":369.181296,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"clkmgr_tl_errors":{"max_time":5.12,"sim_time":369.181296,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.71,"sim_time":106.491098,"passed":5,"total":5,"percent":100.0},"clkmgr_csr_rw":{"max_time":1.25,"sim_time":48.358278,"passed":11,"total":20,"percent":55.0},"clkmgr_csr_aliasing":{"max_time":4.15,"sim_time":397.639392,"passed":2,"total":5,"percent":40.0},"clkmgr_same_csr_outstanding":{"max_time":1.07,"sim_time":39.135227,"passed":1,"total":20,"percent":5.0}},"passed":19,"total":50,"percent":38.0},"tl_d_partial_access":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.71,"sim_time":106.491098,"passed":5,"total":5,"percent":100.0},"clkmgr_csr_rw":{"max_time":1.25,"sim_time":48.358278,"passed":11,"total":20,"percent":55.0},"clkmgr_csr_aliasing":{"max_time":4.15,"sim_time":397.639392,"passed":2,"total":5,"percent":40.0},"clkmgr_same_csr_outstanding":{"max_time":1.07,"sim_time":39.135227,"passed":1,"total":20,"percent":5.0}},"passed":19,"total":50,"percent":38.0}},"passed":293,"total":470,"percent":62.340425531914896},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"clkmgr_sec_cm":{"max_time":8.9,"sim_time":857.634274,"passed":2,"total":5,"percent":40.0},"clkmgr_tl_intg_err":{"max_time":1.66,"sim_time":91.657577,"passed":0,"total":20,"percent":0.0}},"passed":2,"total":25,"percent":8.0},"shadow_reg_update_error":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":3.11,"sim_time":298.995817,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_read_clear_staged_value":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":3.11,"sim_time":298.995817,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_storage_error":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":3.11,"sim_time":298.995817,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadowed_reset_glitch":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":3.11,"sim_time":298.995817,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_update_error_with_csr_rw":{"tests":{"clkmgr_shadow_reg_errors_with_csr_rw":{"max_time":1.29,"sim_time":54.941964,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"sec_cm_bus_integrity":{"tests":{"clkmgr_tl_intg_err":{"max_time":1.66,"sim_time":91.657577,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"sec_cm_meas_clk_bkgn_chk":{"tests":{"clkmgr_frequency":{"max_time":1.22,"sim_time":57.329889,"passed":1,"total":50,"percent":2.0}},"passed":1,"total":50,"percent":2.0},"sec_cm_timeout_clk_bkgn_chk":{"tests":{"clkmgr_frequency_timeout":{"max_time":0.84,"sim_time":12.638492,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":50,"percent":0.0},"sec_cm_meas_config_shadow":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":3.11,"sim_time":298.995817,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_idle_intersig_mubi":{"tests":{"clkmgr_idle_intersig_mubi":{"max_time":4.23,"sim_time":406.478811,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_jitter_config_mubi":{"tests":{"clkmgr_csr_rw":{"max_time":1.25,"sim_time":48.358278,"passed":11,"total":20,"percent":55.0}},"passed":11,"total":20,"percent":55.0},"sec_cm_idle_ctr_redun":{"tests":{"clkmgr_sec_cm":{"max_time":8.9,"sim_time":857.634274,"passed":2,"total":5,"percent":40.0}},"passed":2,"total":5,"percent":40.0},"sec_cm_meas_config_regwen":{"tests":{"clkmgr_csr_rw":{"max_time":1.25,"sim_time":48.358278,"passed":11,"total":20,"percent":55.0}},"passed":11,"total":20,"percent":55.0},"sec_cm_clk_ctrl_config_regwen":{"tests":{"clkmgr_csr_rw":{"max_time":1.25,"sim_time":48.358278,"passed":11,"total":20,"percent":55.0}},"passed":11,"total":20,"percent":55.0},"prim_count_check":{"tests":{"clkmgr_sec_cm":{"max_time":8.9,"sim_time":857.634274,"passed":2,"total":5,"percent":40.0}},"passed":2,"total":5,"percent":40.0}},"passed":84,"total":235,"percent":35.744680851063826},"V3":{"testpoints":{"regwen":{"tests":{"clkmgr_regwen":{"max_time":0.99,"sim_time":23.480586,"passed":1,"total":50,"percent":2.0}},"passed":1,"total":50,"percent":2.0},"stress_all_with_rand_reset":{"tests":{"clkmgr_stress_all_with_rand_reset":{"max_time":29.7,"sim_time":2346.358158,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":50,"percent":0.0}},"passed":1,"total":100,"percent":1.0}},"coverage":{"code":{"block":null,"line_statement":91.54,"branch":94.16,"condition_expression":88.56,"toggle":100.0,"fsm":25.0},"assertion":94.01,"functional":76.69},"cov_report_page":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*":[{"name":"clkmgr_frequency","qual_name":"0.clkmgr_frequency.82750386369262189098965177182869407174824797594249147289323548279597008521086","seed":82750386369262189098965177182869407174824797594249147289323548279597008521086,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5070680 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5070680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"0.clkmgr_stress_all.79468327012035492505153904148085986544292336078535719462873137177159137151333","seed":79468327012035492505153904148085986544292336078535719462873137177159137151333,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  56397755 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  56397755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"1.clkmgr_frequency.108631365011135262464703658597417634149840206770769374839859160589891681706019","seed":108631365011135262464703658597417634149840206770769374839859160589891681706019,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  13560783 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  13560783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"1.clkmgr_stress_all_with_rand_reset.93958931646986462037445632999453086539238918800102817932555634987556449964818","seed":93958931646986462037445632999453086539238918800102817932555634987556449964818,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  15075629 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  15075629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"1.clkmgr_stress_all.66810816715924476597074799411072739225353855575378135499536487147102084764279","seed":66810816715924476597074799411072739225353855575378135499536487147102084764279,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   7685898 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7685898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"2.clkmgr_frequency.97962571957050079183977554244018852133196417966309680693186254190856064382519","seed":97962571957050079183977554244018852133196417966309680693186254190856064382519,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  24468198 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  24468198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"2.clkmgr_stress_all_with_rand_reset.88001312601240429392481631233808429502757969198807667579561811225374827992741","seed":88001312601240429392481631233808429502757969198807667579561811225374827992741,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   5520897 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5520897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"3.clkmgr_frequency.81611124901426938694766463961716191871793853152679195232900244479522996175040","seed":81611124901426938694766463961716191871793853152679195232900244479522996175040,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6638521 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6638521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"3.clkmgr_stress_all.15825545768049139943600362684982165426536177019690231717380453693008829538018","seed":15825545768049139943600362684982165426536177019690231717380453693008829538018,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  11490091 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  11490091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"4.clkmgr_frequency.17845406035952302330508358354006652945401993094260207445775625639380314606504","seed":17845406035952302330508358354006652945401993094260207445775625639380314606504,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5362689 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5362689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"4.clkmgr_stress_all_with_rand_reset.26906612030364062093952471196658353808809521138435977042954880537395365219410","seed":26906612030364062093952471196658353808809521138435977042954880537395365219410,"line":109,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  56952200 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  56952200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"4.clkmgr_stress_all.82863892581719221217810412510215511758044921293090174761401654872542218292196","seed":82863892581719221217810412510215511758044921293090174761401654872542218292196,"line":92,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 175050291 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 175050291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"5.clkmgr_frequency.30106086392777029568233488920460144170058003826763722562395752897751377328445","seed":30106086392777029568233488920460144170058003826763722562395752897751377328445,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5079582 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5079582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"5.clkmgr_stress_all_with_rand_reset.1828045175238442337303843737952844269502643967845220862901850611490179867638","seed":1828045175238442337303843737952844269502643967845220862901850611490179867638,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  47571133 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  47571133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"5.clkmgr_stress_all.497815214246510030981649593554560765759741164232476122361108494004935156029","seed":497815214246510030981649593554560765759741164232476122361108494004935156029,"line":84,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  18761710 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  18761710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"6.clkmgr_stress_all_with_rand_reset.30163917421588837137937631531435816862881309228966120756027761791570206893340","seed":30163917421588837137937631531435816862881309228966120756027761791570206893340,"line":153,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  69809086 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  69809086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"7.clkmgr_frequency.101800037545461287397756671217900797892863787189249380601454394816169829668526","seed":101800037545461287397756671217900797892863787189249380601454394816169829668526,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  10231736 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  10231736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"7.clkmgr_stress_all.91774966044537127892730005578735149193312708933339328233673391719840016845292","seed":91774966044537127892730005578735149193312708933339328233673391719840016845292,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  12710662 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  12710662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"8.clkmgr_frequency.89000913228462771874276112594714487306763361500835161601892418476058763124551","seed":89000913228462771874276112594714487306763361500835161601892418476058763124551,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  10287727 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  10287727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"8.clkmgr_stress_all.45459625930263041691113879685187992084383494210763833232226665056942795123315","seed":45459625930263041691113879685187992084383494210763833232226665056942795123315,"line":96,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  30178748 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  30178748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"9.clkmgr_frequency.102962257772076042293873431169481884909441316370459235661337172000553192309962","seed":102962257772076042293873431169481884909441316370459235661337172000553192309962,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  14802025 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  14802025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"9.clkmgr_stress_all_with_rand_reset.37000813115430952483707102344024665920801561788769125340708749279210817536285","seed":37000813115430952483707102344024665920801561788769125340708749279210817536285,"line":130,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 167859418 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 167859418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"9.clkmgr_stress_all.10062481731724058608427946426860251738512843448308927667528829388408015622561","seed":10062481731724058608427946426860251738512843448308927667528829388408015622561,"line":133,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  70825402 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  70825402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"10.clkmgr_frequency.57320498489799203011630445888225122311887210451571879555712533907354868807032","seed":57320498489799203011630445888225122311887210451571879555712533907354868807032,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4550117 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4550117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"10.clkmgr_stress_all_with_rand_reset.100243539870887043756447207341987945894985568018642506276923418256975367133937","seed":100243539870887043756447207341987945894985568018642506276923418256975367133937,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  36963483 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  36963483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"10.clkmgr_stress_all.43482918569629140193611583356391973100999318486900971845493716374949771966961","seed":43482918569629140193611583356391973100999318486900971845493716374949771966961,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   7948735 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7948735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"11.clkmgr_frequency.30826365474471529506123945089995786154696284328601144008455577929213709850526","seed":30826365474471529506123945089995786154696284328601144008455577929213709850526,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  12453266 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  12453266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"12.clkmgr_frequency.30528713063987599965575906188851641449551868516298961387354801944555497216964","seed":30528713063987599965575906188851641449551868516298961387354801944555497216964,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  13130030 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  13130030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"12.clkmgr_stress_all_with_rand_reset.32885562726213136482587631744935439012978046209048464097185214427331931980016","seed":32885562726213136482587631744935439012978046209048464097185214427331931980016,"line":146,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 175379244 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 175379244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"12.clkmgr_stress_all.16033567295680553994381268597090719913783726840867760919433127365192992682060","seed":16033567295680553994381268597090719913783726840867760919433127365192992682060,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  31981595 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  31981595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"13.clkmgr_frequency.59354450557535958972221154713554591682165014919851350488481738563429929240762","seed":59354450557535958972221154713554591682165014919851350488481738563429929240762,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5001848 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5001848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"13.clkmgr_stress_all_with_rand_reset.113775739823072699848593385429741941846068850235028514797895302777858401865107","seed":113775739823072699848593385429741941846068850235028514797895302777858401865107,"line":87,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  31108697 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  31108697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"14.clkmgr_frequency.91177581254718559263086670333870402553737945656986303669896384167566540643924","seed":91177581254718559263086670333870402553737945656986303669896384167566540643924,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  15033716 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  15033716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"15.clkmgr_frequency.88972002213454554845992995333007077959124783163709867804454479725205335823923","seed":88972002213454554845992995333007077959124783163709867804454479725205335823923,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  14108701 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  14108701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"15.clkmgr_stress_all_with_rand_reset.107993433952337533175992567161739677322270341774569661137500207471783582386987","seed":107993433952337533175992567161739677322270341774569661137500207471783582386987,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  32995204 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  32995204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"16.clkmgr_frequency.43266332559841716539185197692476047515008564278893054879125232981803548334615","seed":43266332559841716539185197692476047515008564278893054879125232981803548334615,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   8135986 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8135986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"16.clkmgr_stress_all.102729636483896553715395665120571460931287488533373825823382558275264947059403","seed":102729636483896553715395665120571460931287488533373825823382558275264947059403,"line":156,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 425758842 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 425758842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"17.clkmgr_frequency.13732468264188660174554604060395085890795959975902590831961937276939082778361","seed":13732468264188660174554604060395085890795959975902590831961937276939082778361,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5718644 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5718644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"18.clkmgr_frequency.63448382404215210861189522555963969661930907881077796248495969914220677978673","seed":63448382404215210861189522555963969661930907881077796248495969914220677978673,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  23109696 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  23109696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"18.clkmgr_stress_all_with_rand_reset.68921241814472991562189207441368623336061380674354575408467298732870708381399","seed":68921241814472991562189207441368623336061380674354575408467298732870708381399,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  39884666 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  39884666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"19.clkmgr_frequency.104237827844072024034859808486052410384857471572221067899402764826561075313910","seed":104237827844072024034859808486052410384857471572221067899402764826561075313910,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  22308235 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  22308235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"19.clkmgr_stress_all_with_rand_reset.80993966584903666058461173418435063015233724513086511647647540210889418294262","seed":80993966584903666058461173418435063015233724513086511647647540210889418294262,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  19326418 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  19326418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"20.clkmgr_frequency.50879754458099606702120192754504319191280034671474587089361062392802843544367","seed":50879754458099606702120192754504319191280034671474587089361062392802843544367,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  10625738 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  10625738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"20.clkmgr_stress_all_with_rand_reset.43524432111625949346847586561656657582543544904724467906240881126329411444774","seed":43524432111625949346847586561656657582543544904724467906240881126329411444774,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  24056264 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  24056264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"20.clkmgr_stress_all.33813891278113752046060085783408844627412293828751849644450101431287975997522","seed":33813891278113752046060085783408844627412293828751849644450101431287975997522,"line":196,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 285524431 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 285524431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"21.clkmgr_frequency.33118089926979360413800478711906478969226340973877497908833989621924644082743","seed":33118089926979360413800478711906478969226340973877497908833989621924644082743,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7480985 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7480985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"22.clkmgr_frequency.48842743018785706050580625230417385964812324947208968235112319940550025142727","seed":48842743018785706050580625230417385964812324947208968235112319940550025142727,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5233825 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5233825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"23.clkmgr_frequency.39947792919460706707005982050436185549567565630201761174060014688490746915732","seed":39947792919460706707005982050436185549567565630201761174060014688490746915732,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6912239 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6912239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"24.clkmgr_frequency.26357165562912840997781773471028520897245742575278005919545386632820600418360","seed":26357165562912840997781773471028520897245742575278005919545386632820600418360,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4794116 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4794116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"24.clkmgr_stress_all_with_rand_reset.22478568068985452878632456808999498180071715604614872974615722804210227831714","seed":22478568068985452878632456808999498180071715604614872974615722804210227831714,"line":80,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 149417098 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 149417098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"24.clkmgr_stress_all.50953979960320634467224107889191015447662704594328852098946146901867914928964","seed":50953979960320634467224107889191015447662704594328852098946146901867914928964,"line":141,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 190922731 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 190922731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"25.clkmgr_frequency.100969832373739252086922836186710689974723051079611721946722349051387846968896","seed":100969832373739252086922836186710689974723051079611721946722349051387846968896,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  19755335 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  19755335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"26.clkmgr_frequency.75009917137095441820907932739300741877830283948426475418454594403601297279084","seed":75009917137095441820907932739300741877830283948426475418454594403601297279084,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5734308 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5734308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"27.clkmgr_frequency.36133231894079119466172543354573297958689620138835722994599193303304805060836","seed":36133231894079119466172543354573297958689620138835722994599193303304805060836,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5546509 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5546509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"28.clkmgr_frequency.63517659709483852564385620203300764146105579394636300658914029265129913950056","seed":63517659709483852564385620203300764146105579394636300658914029265129913950056,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/28.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  24487801 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  24487801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"28.clkmgr_stress_all_with_rand_reset.21426003158239624790735137249597852877978280311407839866526601886028385005261","seed":21426003158239624790735137249597852877978280311407839866526601886028385005261,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/28.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  26254860 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  26254860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"29.clkmgr_frequency.91582905182478191181202057973071733121551576109127808202600241939217067230246","seed":91582905182478191181202057973071733121551576109127808202600241939217067230246,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5056938 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5056938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"29.clkmgr_stress_all.91050153128944674193251517358155966970542534461528983656992219300655842823474","seed":91050153128944674193251517358155966970542534461528983656992219300655842823474,"line":280,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 202894893 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 202894893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"30.clkmgr_frequency.88035390761983699114649455113561182018928536932820120084825876621968658549744","seed":88035390761983699114649455113561182018928536932820120084825876621968658549744,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  26867092 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  26867092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"30.clkmgr_stress_all.52126162932770701785631292493997434028661727168132243994672307325966784256050","seed":52126162932770701785631292493997434028661727168132243994672307325966784256050,"line":263,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 113514023 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 113514023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"31.clkmgr_frequency.65321689993436664638353985859187531717627378831663255784877127491702566194532","seed":65321689993436664638353985859187531717627378831663255784877127491702566194532,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   9214436 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   9214436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"31.clkmgr_stress_all.88458124956531132403173311466707838423988435954938357080664864088646289686842","seed":88458124956531132403173311466707838423988435954938357080664864088646289686842,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   8288867 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8288867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"32.clkmgr_frequency.1729924045572533732055193195176548369728819459523537145885051465762147924021","seed":1729924045572533732055193195176548369728819459523537145885051465762147924021,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  21992558 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  21992558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"32.clkmgr_stress_all_with_rand_reset.20480977610315586120111374565784611900520057576186471079450970650986167979692","seed":20480977610315586120111374565784611900520057576186471079450970650986167979692,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  38827645 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  38827645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"33.clkmgr_frequency.100246870327092745056083746464832079635994761781121213834819316115634549502475","seed":100246870327092745056083746464832079635994761781121213834819316115634549502475,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  16975637 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  16975637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"33.clkmgr_stress_all_with_rand_reset.2786190291013794674092881072919528205163108709041530353432515868218997892710","seed":2786190291013794674092881072919528205163108709041530353432515868218997892710,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   7707032 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7707032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"34.clkmgr_frequency.27198256225464589718294049127420848067678193762001078976693946144388754083230","seed":27198256225464589718294049127420848067678193762001078976693946144388754083230,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  18666052 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  18666052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"34.clkmgr_stress_all_with_rand_reset.21234140682693604368237650369282372691614535793938106214670367834176947120780","seed":21234140682693604368237650369282372691614535793938106214670367834176947120780,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   4640344 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4640344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"35.clkmgr_frequency.68494702011761976900808266442556771108278375577110858806978693259500003872505","seed":68494702011761976900808266442556771108278375577110858806978693259500003872505,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   9692901 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   9692901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"36.clkmgr_frequency.99527757730805167592113047880613790671079083138855704272729235961939337779668","seed":99527757730805167592113047880613790671079083138855704272729235961939337779668,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6694551 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6694551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"36.clkmgr_stress_all_with_rand_reset.59018026598525575878165369828636131455039325106343146095675228551208822478560","seed":59018026598525575878165369828636131455039325106343146095675228551208822478560,"line":205,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 178249372 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 178249372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"37.clkmgr_frequency.87165109446464680275012570966979443442470628227135337414745709369705732966397","seed":87165109446464680275012570966979443442470628227135337414745709369705732966397,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  10667673 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  10667673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"37.clkmgr_stress_all_with_rand_reset.20251767389658360895103261213037350883822875177852923660716803214523244730370","seed":20251767389658360895103261213037350883822875177852923660716803214523244730370,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 409848235 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 409848235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"37.clkmgr_stress_all.9076054344467421675450941776890316986091782324373179155550752007261625838841","seed":9076054344467421675450941776890316986091782324373179155550752007261625838841,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   6986752 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6986752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"38.clkmgr_frequency.26153246640139653173829732878172781208281331711555682790948871595292434826436","seed":26153246640139653173829732878172781208281331711555682790948871595292434826436,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5770318 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5770318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"38.clkmgr_stress_all_with_rand_reset.85631812601709937807717381907079479834988424966432385003780941128548906410079","seed":85631812601709937807717381907079479834988424966432385003780941128548906410079,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  13105866 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  13105866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"39.clkmgr_frequency.16732135856262190466655916317240539906556805116083800562734614030696350487425","seed":16732135856262190466655916317240539906556805116083800562734614030696350487425,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6274444 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6274444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"40.clkmgr_frequency.113056088556023648619111692619315356984400522383220412708280442761274831980757","seed":113056088556023648619111692619315356984400522383220412708280442761274831980757,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   7029261 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7029261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"41.clkmgr_frequency.91914069558093276143339088243010267579010268145391375465454486338826288250442","seed":91914069558093276143339088243010267579010268145391375465454486338826288250442,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  18499972 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  18499972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"41.clkmgr_stress_all_with_rand_reset.29167155851518983609232188501803843888511563478350634194131274770359711582219","seed":29167155851518983609232188501803843888511563478350634194131274770359711582219,"line":106,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  78038722 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  78038722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"41.clkmgr_stress_all.102583491182345427113682775851336052327698166364119417923494467708519122303921","seed":102583491182345427113682775851336052327698166364119417923494467708519122303921,"line":104,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 282626011 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 282626011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"42.clkmgr_frequency.41481023460925397592927982042185087904190831529834107412894060168081069082564","seed":41481023460925397592927982042185087904190831529834107412894060168081069082564,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5112270 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5112270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"42.clkmgr_stress_all_with_rand_reset.27831233747833431608878895393718387753781368888649329134799801406832146660267","seed":27831233747833431608878895393718387753781368888649329134799801406832146660267,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   8715115 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8715115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"42.clkmgr_stress_all.96156346403745775108272608723313103958707725724549924679334251647234074906314","seed":96156346403745775108272608723313103958707725724549924679334251647234074906314,"line":125,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 237737393 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 237737393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"43.clkmgr_frequency.11971997233199149297567994213282818663133990391741915712179305060672745084661","seed":11971997233199149297567994213282818663133990391741915712179305060672745084661,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  57329889 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  57329889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"43.clkmgr_stress_all_with_rand_reset.100122728493428035811631982952687100840309215601264786456286298067247437102615","seed":100122728493428035811631982952687100840309215601264786456286298067247437102615,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   9006778 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   9006778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"44.clkmgr_frequency.70673003634246290076422915568655516300016318098547300769064554769866344932031","seed":70673003634246290076422915568655516300016318098547300769064554769866344932031,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   4443140 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4443140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"44.clkmgr_stress_all_with_rand_reset.70198630777806250463138368016609252347164396276928829150600653665904069762154","seed":70198630777806250463138368016609252347164396276928829150600653665904069762154,"line":134,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  53751747 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  53751747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"45.clkmgr_frequency.56928274598167213385703716604826766440881535429177241549804935519924846850380","seed":56928274598167213385703716604826766440881535429177241549804935519924846850380,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  29781794 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  29781794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"46.clkmgr_frequency.106069014690069228980517804141574978913282969826465825277924311784952850466429","seed":106069014690069228980517804141574978913282969826465825277924311784952850466429,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @  12243661 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  12243661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"47.clkmgr_frequency.46025571622045302879170201437228004377077364992332862113522849885310460493974","seed":46025571622045302879170201437228004377077364992332862113522849885310460493974,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   8626804 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8626804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"47.clkmgr_stress_all.17787414667126068869332685695993856673936121091352490497291556154862577129462","seed":17787414667126068869332685695993856673936121091352490497291556154862577129462,"line":132,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  34875879 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  34875879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"48.clkmgr_frequency.82885120066918326695104930289193094299263649653509627959636830621532175485556","seed":82885120066918326695104930289193094299263649653509627959636830621532175485556,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5715059 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5715059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"48.clkmgr_stress_all_with_rand_reset.8095373835386187368676739261765730083462610910461792210051322831192537573108","seed":8095373835386187368676739261765730083462610910461792210051322831192537573108,"line":130,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 449134462 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 449134462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"48.clkmgr_stress_all.3884171335607081614399346411322117223969633827123088106229984458027469811277","seed":3884171335607081614399346411322117223969633827123088106229984458027469811277,"line":124,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  23865122 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  23865122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency","qual_name":"49.clkmgr_frequency.98556832835881253129673067989474688340869100903555849686385188684220968274936","seed":98556832835881253129673067989474688340869100903555849686385188684220968274936,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   6793861 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6793861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"49.clkmgr_stress_all_with_rand_reset.48795804548333133182922243343379243802645815595892945056420408888764002490643","seed":48795804548333133182922243343379243802645815595892945056420408888764002490643,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  83756810 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  83756810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"49.clkmgr_stress_all.38622232179017643422792145065091254290686539147649828335501018054715711738145","seed":38622232179017643422792145065091254290686539147649828335501018054715711738145,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  86993237 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  86993237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*":[{"name":"clkmgr_frequency_timeout","qual_name":"0.clkmgr_frequency_timeout.57623319450116424960727838175628300433696618285263390658666502680360440333042","seed":57623319450116424960727838175628300433696618285263390658666502680360440333042,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5052120 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5052120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"0.clkmgr_stress_all_with_rand_reset.18728023751172739466156401349008628439274412809351750914875613424938010070231","seed":18728023751172739466156401349008628439274412809351750914875613424938010070231,"line":95,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  81997075 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  81997075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"1.clkmgr_frequency_timeout.25382035108028105258352875600015183824418178082517308672065164143000097002111","seed":25382035108028105258352875600015183824418178082517308672065164143000097002111,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2837366 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2837366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"2.clkmgr_frequency_timeout.3736143879957267158069637788758238018154257270025842909996137996762436288982","seed":3736143879957267158069637788758238018154257270025842909996137996762436288982,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5335481 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5335481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"2.clkmgr_stress_all.12587969909160352419799009828132004950225686390145284531292128778367880150467","seed":12587969909160352419799009828132004950225686390145284531292128778367880150467,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   7844252 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   7844252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"3.clkmgr_frequency_timeout.75864581896549311359851768722090532755347284188568334277336375137357013566167","seed":75864581896549311359851768722090532755347284188568334277336375137357013566167,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4227512 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4227512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"3.clkmgr_stress_all_with_rand_reset.54464635605845957574558221569015452597627223429743969878192511909514495898696","seed":54464635605845957574558221569015452597627223429743969878192511909514495898696,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   6337000 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6337000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"4.clkmgr_frequency_timeout.60684222723354448242869217148301598317688550414159867384009334273474846486998","seed":60684222723354448242869217148301598317688550414159867384009334273474846486998,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6570000 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6570000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"5.clkmgr_frequency_timeout.41456834449807178786542142883952310939976148301652468265347019292293246261283","seed":41456834449807178786542142883952310939976148301652468265347019292293246261283,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2568949 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2568949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"6.clkmgr_frequency_timeout.31305838737303088454019023572211998661721592404905476975058543521861955166901","seed":31305838737303088454019023572211998661721592404905476975058543521861955166901,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @  11295217 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  11295217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"6.clkmgr_stress_all.17184704019569178401449863167107175970060172797415369417481450847433738287985","seed":17184704019569178401449863167107175970060172797415369417481450847433738287985,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   5173039 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5173039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"7.clkmgr_frequency_timeout.105177271556951345851975850302139258051168485019172350848174391057793399765331","seed":105177271556951345851975850302139258051168485019172350848174391057793399765331,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2391178 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2391178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"7.clkmgr_stress_all_with_rand_reset.94152979278328134134521109246130934091545463254586627690064545833780719501518","seed":94152979278328134134521109246130934091545463254586627690064545833780719501518,"line":107,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 118168889 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 118168889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"8.clkmgr_frequency_timeout.97747954657788293195869829676170945482514193620698392720466808062450970847084","seed":97747954657788293195869829676170945482514193620698392720466808062450970847084,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3786067 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3786067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"8.clkmgr_stress_all_with_rand_reset.21014809479424250378084500826183569869518630854262927604331710912712550373074","seed":21014809479424250378084500826183569869518630854262927604331710912712550373074,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   5717366 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5717366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"9.clkmgr_frequency_timeout.54491087565963538742008474861117979964640029836771350660711671116337824976335","seed":54491087565963538742008474861117979964640029836771350660711671116337824976335,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2969358 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2969358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"10.clkmgr_frequency_timeout.15528862502249642237602812672931871031286199350133566798178670277515271596395","seed":15528862502249642237602812672931871031286199350133566798178670277515271596395,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4049272 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4049272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"11.clkmgr_frequency_timeout.8362447243402574677348583410216342161141936305828486465363447936044749525261","seed":8362447243402574677348583410216342161141936305828486465363447936044749525261,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5970133 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5970133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"11.clkmgr_stress_all_with_rand_reset.19260648337273322105541544262824233995415704299549123220782064358508416044124","seed":19260648337273322105541544262824233995415704299549123220782064358508416044124,"line":153,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 178766135 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 178766135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"11.clkmgr_stress_all.81404910618637558460507572597406394343535871457643286666216245283978091720122","seed":81404910618637558460507572597406394343535871457643286666216245283978091720122,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  37828343 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  37828343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"12.clkmgr_frequency_timeout.76919077439615736166618375365231180741917751792112477309952473331499796127472","seed":76919077439615736166618375365231180741917751792112477309952473331499796127472,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2624182 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2624182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"13.clkmgr_frequency_timeout.101378776402257365328826113608016164971402557181142190102673986497300884106189","seed":101378776402257365328826113608016164971402557181142190102673986497300884106189,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2116855 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2116855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"13.clkmgr_stress_all.53568903688102394595039291674085452312323280873981627282884654269614693942535","seed":53568903688102394595039291674085452312323280873981627282884654269614693942535,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   3809301 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3809301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"14.clkmgr_frequency_timeout.3033418595630830439802166074743895340842572246671450339566659564151488082006","seed":3033418595630830439802166074743895340842572246671450339566659564151488082006,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @  13861847 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  13861847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"14.clkmgr_stress_all_with_rand_reset.59188295777820678458584863588298769319028910457980067533303338067594552007201","seed":59188295777820678458584863588298769319028910457980067533303338067594552007201,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  20154935 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  20154935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"15.clkmgr_frequency_timeout.19705991560872553386295015878391665545230343269159731298603431347142236825540","seed":19705991560872553386295015878391665545230343269159731298603431347142236825540,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3388098 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3388098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"15.clkmgr_stress_all.77959796190073517197995737034055881437076321214907304906700201302942823349877","seed":77959796190073517197995737034055881437076321214907304906700201302942823349877,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   4410408 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4410408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"16.clkmgr_frequency_timeout.51130412929782460609653308260029328519928816165110149012209345154585931661759","seed":51130412929782460609653308260029328519928816165110149012209345154585931661759,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6457995 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6457995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"16.clkmgr_stress_all_with_rand_reset.114347993345157862773835324752814730372603807216716773251887476428228122582948","seed":114347993345157862773835324752814730372603807216716773251887476428228122582948,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  16605885 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  16605885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"17.clkmgr_frequency_timeout.104592132260756090781830048491607752556879035524326444654496168370139615138026","seed":104592132260756090781830048491607752556879035524326444654496168370139615138026,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3307770 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3307770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"17.clkmgr_stress_all_with_rand_reset.73908870443277538281327722708475733195406184749401680914527045744533198414471","seed":73908870443277538281327722708475733195406184749401680914527045744533198414471,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  36133198 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  36133198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"17.clkmgr_stress_all.47797915195241812195936354969423987302110136561665117156804151178284479367440","seed":47797915195241812195936354969423987302110136561665117156804151178284479367440,"line":117,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 177537234 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 177537234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"18.clkmgr_frequency_timeout.30800040753791989960100076011679416053023776058983438311779331384971903270859","seed":30800040753791989960100076011679416053023776058983438311779331384971903270859,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   7877804 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7877804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"18.clkmgr_stress_all.3655574597337517526831917119838394397834075720033952342623842428226174825331","seed":3655574597337517526831917119838394397834075720033952342623842428226174825331,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   4557306 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4557306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"19.clkmgr_frequency_timeout.1818355735240832596977724381199300160959130673910403182711590510170774682401","seed":1818355735240832596977724381199300160959130673910403182711590510170774682401,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3200277 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3200277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"19.clkmgr_stress_all.82678480022085477142825162935905362600499307559893882677242875681097247095393","seed":82678480022085477142825162935905362600499307559893882677242875681097247095393,"line":89,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  24433797 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  24433797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"20.clkmgr_frequency_timeout.97020844758050035695290098472910249477044165069965601507136139036518402291314","seed":97020844758050035695290098472910249477044165069965601507136139036518402291314,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5139277 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5139277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"21.clkmgr_frequency_timeout.49590025207548798746028188983111691767131653259012174269404293752211110827449","seed":49590025207548798746028188983111691767131653259012174269404293752211110827449,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2674382 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2674382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"21.clkmgr_stress_all_with_rand_reset.15856915807160406095789306609034287781769364050585775221936047889801117923241","seed":15856915807160406095789306609034287781769364050585775221936047889801117923241,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   3682526 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3682526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"21.clkmgr_stress_all.85822986986564114417185282103593784398116062845345506190710785037269427056070","seed":85822986986564114417185282103593784398116062845345506190710785037269427056070,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   9996269 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   9996269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"22.clkmgr_frequency_timeout.94807491743434532880862324192729253217208286753671419464452950583290781640213","seed":94807491743434532880862324192729253217208286753671419464452950583290781640213,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   1774310 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   1774310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"22.clkmgr_stress_all_with_rand_reset.88031201404597479743085486220882176530937165323347306445982709990659749750567","seed":88031201404597479743085486220882176530937165323347306445982709990659749750567,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   9226314 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   9226314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"22.clkmgr_stress_all.99112668815999084934209349259043073586890584233441649227391851137493539416768","seed":99112668815999084934209349259043073586890584233441649227391851137493539416768,"line":125,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @ 182130948 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 182130948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"23.clkmgr_frequency_timeout.98357053844543724452062202372055862109007402587763991293116215492198863271361","seed":98357053844543724452062202372055862109007402587763991293116215492198863271361,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4336472 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4336472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"23.clkmgr_stress_all_with_rand_reset.68665967545250127866723696625247203980240540731249149570573387975919756363335","seed":68665967545250127866723696625247203980240540731249149570573387975919756363335,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   3147554 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3147554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"23.clkmgr_stress_all.85569552895161085819349384594778447206813442014595847059003239371392770393302","seed":85569552895161085819349384594778447206813442014595847059003239371392770393302,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  15756034 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  15756034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"24.clkmgr_frequency_timeout.100062030793477829599841884037121463577255524361157792844117943666770354392429","seed":100062030793477829599841884037121463577255524361157792844117943666770354392429,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5179984 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5179984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"25.clkmgr_frequency_timeout.91405282520977076129311997366850931072749532325096451411371293630848937684482","seed":91405282520977076129311997366850931072749532325096451411371293630848937684482,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4646635 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   4646635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"25.clkmgr_stress_all_with_rand_reset.43382578823568266523804993161177426845362001102102282633340960147588267133792","seed":43382578823568266523804993161177426845362001102102282633340960147588267133792,"line":85,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  89518651 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  89518651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"25.clkmgr_stress_all.65260169632254027340780116689696788156938737584318852757825535755264637387453","seed":65260169632254027340780116689696788156938737584318852757825535755264637387453,"line":250,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  76955029 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  76955029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"26.clkmgr_frequency_timeout.72953202570092819133718246912101384120319663015410786956120372565494497340655","seed":72953202570092819133718246912101384120319663015410786956120372565494497340655,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @  12638492 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  12638492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"26.clkmgr_stress_all_with_rand_reset.61296081213285930652427521254967420232995807573839476650644180703450188260030","seed":61296081213285930652427521254967420232995807573839476650644180703450188260030,"line":152,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2346358158 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 2346358158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"27.clkmgr_frequency_timeout.5401059971299901036270416814168332931865326457075100924423299271185471561672","seed":5401059971299901036270416814168332931865326457075100924423299271185471561672,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6938893 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6938893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"27.clkmgr_stress_all_with_rand_reset.54192565297686320818128896042934804608707541922106485098671114245503589073260","seed":54192565297686320818128896042934804608707541922106485098671114245503589073260,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  25293975 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  25293975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"27.clkmgr_stress_all.27226693099947316621618353198121061344881671795987864066438166317788250257584","seed":27226693099947316621618353198121061344881671795987864066438166317788250257584,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   9190286 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   9190286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"28.clkmgr_frequency_timeout.100385952805872610405130170586546966014033146316844631818264526915599072356718","seed":100385952805872610405130170586546966014033146316844631818264526915599072356718,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/28.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3519320 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3519320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"28.clkmgr_stress_all.43449314375443006840741434640129699235274421828377146680943272444386242733257","seed":43449314375443006840741434640129699235274421828377146680943272444386242733257,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/28.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  21590256 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  21590256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"29.clkmgr_frequency_timeout.98956810497635042999918050836100944997222002614483581522606333592918766286420","seed":98956810497635042999918050836100944997222002614483581522606333592918766286420,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2775967 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2775967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"29.clkmgr_stress_all_with_rand_reset.1340036534782550893166501288691227029874705634752510331806884392295241465112","seed":1340036534782550893166501288691227029874705634752510331806884392295241465112,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 128024186 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 128024186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"30.clkmgr_frequency_timeout.93786967091546062802425980538368080138543231960255580929511707578121999865312","seed":93786967091546062802425980538368080138543231960255580929511707578121999865312,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @  13046745 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  13046745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"30.clkmgr_stress_all_with_rand_reset.32278186618272012433796661556093855024649721071905293431123916804410294511690","seed":32278186618272012433796661556093855024649721071905293431123916804410294511690,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   3439462 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3439462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"31.clkmgr_frequency_timeout.69886926396993447649245108564274399986756875620211746388005870967490944444699","seed":69886926396993447649245108564274399986756875620211746388005870967490944444699,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6542584 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6542584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"31.clkmgr_stress_all_with_rand_reset.31285526401279521707096475201523837629967602448606705289120233364403710214708","seed":31285526401279521707096475201523837629967602448606705289120233364403710214708,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  11845440 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  11845440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"32.clkmgr_frequency_timeout.79745646111110457443431820957998163807152268270639783103880888076546992751600","seed":79745646111110457443431820957998163807152268270639783103880888076546992751600,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2102483 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2102483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"32.clkmgr_stress_all.40526148421756477174414935599419350656887029218270536305251490460643163676655","seed":40526148421756477174414935599419350656887029218270536305251490460643163676655,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   5688695 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5688695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"33.clkmgr_frequency_timeout.16785451701704794367652843330186255894202613172980883523742490324946852867245","seed":16785451701704794367652843330186255894202613172980883523742490324946852867245,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5057223 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   5057223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"33.clkmgr_stress_all.78507239209032719604101101674626320347820951052352742232040339200037330156908","seed":78507239209032719604101101674626320347820951052352742232040339200037330156908,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  50550299 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  50550299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"34.clkmgr_frequency_timeout.59976798704942422252907861358124822324620020383806217421660073162456774716164","seed":59976798704942422252907861358124822324620020383806217421660073162456774716164,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3278118 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3278118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"34.clkmgr_stress_all.52212929626983470172445457471346126567092448074557196525878320833619474064583","seed":52212929626983470172445457471346126567092448074557196525878320833619474064583,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   6074718 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   6074718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"35.clkmgr_frequency_timeout.108964576944597631345306118041458735381723644825247628321471431552331647463087","seed":108964576944597631345306118041458735381723644825247628321471431552331647463087,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   7786353 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7786353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"35.clkmgr_stress_all_with_rand_reset.40982836510971959542157850377500794711758611710397782728718749445536240354299","seed":40982836510971959542157850377500794711758611710397782728718749445536240354299,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   8659854 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   8659854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"35.clkmgr_stress_all.6396011067683506145931970884017931435963047877284728902943516072427415814311","seed":6396011067683506145931970884017931435963047877284728902943516072427415814311,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  32136720 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  32136720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"36.clkmgr_frequency_timeout.27133416366044433924002581626582081875222465605947093963574412021104678769750","seed":27133416366044433924002581626582081875222465605947093963574412021104678769750,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2544899 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2544899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"36.clkmgr_stress_all.37543998920989421270878747437947687924012985204803021018944124846648138512633","seed":37543998920989421270878747437947687924012985204803021018944124846648138512633,"line":86,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  23685562 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  23685562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"37.clkmgr_frequency_timeout.99463210103502137859163979511924246869178167461982448302893473158231618308768","seed":99463210103502137859163979511924246869178167461982448302893473158231618308768,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   6998827 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   6998827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"38.clkmgr_frequency_timeout.83378670211533898505727546894247498920808739607732765473453844925079468963898","seed":83378670211533898505727546894247498920808739607732765473453844925079468963898,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   5116443 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5116443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"38.clkmgr_stress_all.81041943711596287272255221781253455317009634927858690957529471095829961522581","seed":81041943711596287272255221781253455317009634927858690957529471095829961522581,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  65550212 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  65550212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"39.clkmgr_frequency_timeout.38104476894082970264614681894258949066885415500354830496861503120486821811561","seed":38104476894082970264614681894258949066885415500354830496861503120486821811561,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3047765 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3047765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"39.clkmgr_stress_all_with_rand_reset.95345071238549151979392041522676219922316663698150675801675913680524036094123","seed":95345071238549151979392041522676219922316663698150675801675913680524036094123,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  56909898 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @  56909898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"40.clkmgr_frequency_timeout.80407226772119647152746346155067115691024600800690738864874906781641914295008","seed":80407226772119647152746346155067115691024600800690738864874906781641914295008,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2357448 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2357448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"40.clkmgr_stress_all_with_rand_reset.102836229790748555036433426716622322553940564415108444328255166092560678861059","seed":102836229790748555036433426716622322553940564415108444328255166092560678861059,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 214636446 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @ 214636446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"40.clkmgr_stress_all.98618157977035777271070381580660099962061619487077374240355656282857268822924","seed":98618157977035777271070381580660099962061619487077374240355656282857268822924,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   2831853 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   2831853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"41.clkmgr_frequency_timeout.48329141141772728312355851392842025338270822368880477198063658798517619481444","seed":48329141141772728312355851392842025338270822368880477198063658798517619481444,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3307952 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3307952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"42.clkmgr_frequency_timeout.69775307270125947669927156470572933249788628320480988014511053391464588184694","seed":69775307270125947669927156470572933249788628320480988014511053391464588184694,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3120735 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3120735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"43.clkmgr_frequency_timeout.103354309195476552507857402047297424760688231360985881386420535515363460324327","seed":103354309195476552507857402047297424760688231360985881386420535515363460324327,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   2695493 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2695493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"43.clkmgr_stress_all.66191207112666931185041647165051613115539631466382480168480047505587229418013","seed":66191207112666931185041647165051613115539631466382480168480047505587229418013,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   9820325 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   9820325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"44.clkmgr_frequency_timeout.32242414855145353390218117339843927545934841520703280575639610069372879152301","seed":32242414855145353390218117339843927545934841520703280575639610069372879152301,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3620058 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3620058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"44.clkmgr_stress_all.82403712278968117387307477360596138379043091950413112057571553280703146769830","seed":82403712278968117387307477360596138379043091950413112057571553280703146769830,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @  43150664 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  43150664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"45.clkmgr_frequency_timeout.71578312798899177084553551445172227311226626324751967347531484627833569250239","seed":71578312798899177084553551445172227311226626324751967347531484627833569250239,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3116354 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3116354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"45.clkmgr_stress_all_with_rand_reset.107419240989199497395744061686054602157894973161324592556586570467951267764703","seed":107419240989199497395744061686054602157894973161324592556586570467951267764703,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  16101296 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  16101296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"45.clkmgr_stress_all.9991562085559742893793180238630590097401327891846058168804375744258277033669","seed":9991562085559742893793180238630590097401327891846058168804375744258277033669,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   2195685 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   2195685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"46.clkmgr_frequency_timeout.42187851151977549437637931103830376403818818250825371539333397701891428327497","seed":42187851151977549437637931103830376403818818250825371539333397701891428327497,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3611811 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3611811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"46.clkmgr_stress_all_with_rand_reset.1105587589580271412259150837493772991230746906749509255469326364507010705644","seed":1105587589580271412259150837493772991230746906749509255469326364507010705644,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  32172631 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @  32172631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"46.clkmgr_stress_all.36735360118404137315597743430645613344024434159390132706102718989509506452447","seed":36735360118404137315597743430645613344024434159390132706102718989509506452447,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   3784927 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3784927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"47.clkmgr_frequency_timeout.78100271689727122957941700996699695014196182379368953164403558085565474477708","seed":78100271689727122957941700996699695014196182379368953164403558085565474477708,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   4364557 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   4364557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"47.clkmgr_stress_all_with_rand_reset.90068023758803187019875086225662176727709533050073939503776746971831321137287","seed":90068023758803187019875086225662176727709533050073939503776746971831321137287,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   3782341 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3782341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"48.clkmgr_frequency_timeout.18914234751915218649656842640900866690158760428443854880095684765794824583835","seed":18914234751915218649656842640900866690158760428443854880095684765794824583835,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3303166 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3303166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_frequency_timeout","qual_name":"49.clkmgr_frequency_timeout.28261107146505995378905507432328103919544555288700774011316833852376364293726","seed":28261107146505995378905507432328103919544555288700774011316833852376364293726,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3547084 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   3547084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.main_meas_ctrl_en":[{"name":"clkmgr_regwen","qual_name":"0.clkmgr_regwen.113558127491715514812374894486234597880046469557443134360492541035763181526619","seed":113558127491715514812374894486234597880046469557443134360492541035763181526619,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3856732 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @   3856732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"2.clkmgr_regwen.114102317518142872879895363882156222044795054343057188418420270077386972019390","seed":114102317518142872879895363882156222044795054343057188418420270077386972019390,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3191827 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (8 [0x8] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @   3191827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"18.clkmgr_regwen.110472064375907263107091236109598790711397691125272123319227534072009169273221","seed":110472064375907263107091236109598790711397691125272123319227534072009169273221,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   9696121 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @   9696121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"38.clkmgr_regwen.96837111940157501731335958755720916228610337446060865937829868146915797031177","seed":96837111940157501731335958755720916228610337446060865937829868146915797031177,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/38.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   7272173 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @   7272173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"46.clkmgr_regwen.69192556220627846510257876540681789756488229600551095912338745620060324361644","seed":69192556220627846510257876540681789756488229600551095912338745620060324361644,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/46.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3012436 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en\n","UVM_INFO @   3012436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed":[{"name":"clkmgr_regwen","qual_name":"1.clkmgr_regwen.99216195734913165385478061769610800907323849131893409724226842911409782353145","seed":99216195734913165385478061769610800907323849131893409724226842911409782353145,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5415133 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   5415133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"4.clkmgr_regwen.101365793333403423449765654470477604730211997968194121145618994279083532014477","seed":101365793333403423449765654470477604730211997968194121145618994279083532014477,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5235289 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   5235289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"6.clkmgr_regwen.100682835092360453687953363374760759192632845931050458879214834915485827611576","seed":100682835092360453687953363374760759192632845931050458879214834915485827611576,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   7653484 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   7653484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"13.clkmgr_regwen.65655910164677299718716195465256154642594542028175683524513545896436327948546","seed":65655910164677299718716195465256154642594542028175683524513545896436327948546,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3137933 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   3137933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"14.clkmgr_regwen.90501591979030561168300929635060274758414726581212594296295568871600232860839","seed":90501591979030561168300929635060274758414726581212594296295568871600232860839,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3114698 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   3114698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"17.clkmgr_regwen.34717123323259560087645529453603947269201065399282578070978197492008163988273","seed":34717123323259560087645529453603947269201065399282578070978197492008163988273,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6081099 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   6081099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"22.clkmgr_regwen.113110906125381564453996943330128216632896067336361139927258809354682527623421","seed":113110906125381564453996943330128216632896067336361139927258809354682527623421,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  23686872 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @  23686872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"24.clkmgr_regwen.60416881444313306334720048792407381114354245088804711533790120383611661126010","seed":60416881444313306334720048792407381114354245088804711533790120383611661126010,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  23480586 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @  23480586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"29.clkmgr_regwen.66811568367217437285654298924847381013570386869871719613893965438232000195718","seed":66811568367217437285654298924847381013570386869871719613893965438232000195718,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/29.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   7864619 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   7864619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"31.clkmgr_regwen.74868883811197350183373435872745653083097392110761744432104900061784256068936","seed":74868883811197350183373435872745653083097392110761744432104900061784256068936,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/31.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3591374 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   3591374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"35.clkmgr_regwen.62703051023278122872191543385143767158855887228706118119688514480708801504591","seed":62703051023278122872191543385143767158855887228706118119688514480708801504591,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/35.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  21683511 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @  21683511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"37.clkmgr_regwen.52661004730549857977917940434280331512576355174051183965837257098305413200904","seed":52661004730549857977917940434280331512576355174051183965837257098305413200904,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/37.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2741590 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   2741590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"40.clkmgr_regwen.5290571584486743641281094619960172102202248417896940209864319975273729991769","seed":5290571584486743641281094619960172102202248417896940209864319975273729991769,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/40.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4114665 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   4114665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"43.clkmgr_regwen.45453076793653420473401585820033191463015231447403696900902906712550670578545","seed":45453076793653420473401585820033191463015231447403696900902906712550670578545,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/43.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4369228 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   4369228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"45.clkmgr_regwen.102514124129031444004040380659990439110520908831275262432320420794876232455816","seed":102514124129031444004040380659990439110520908831275262432320420794876232455816,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/45.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   7021369 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   7021369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"48.clkmgr_regwen.80686429206616981753138331300831111880024291049818001127838389836156493790421","seed":80686429206616981753138331300831111880024291049818001127838389836156493790421,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/48.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2359115 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed\n","UVM_INFO @   2359115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire":[{"name":"clkmgr_sec_cm","qual_name":"1.clkmgr_sec_cm.47856957361825876515207772894224689753427089259993110320873493583920484296848","seed":47856957361825876515207772894224689753427089259993110320873493583920484296848,"line":255,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_sec_cm/latest/run.log","log_context":["UVM_ERROR @ 202970852 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire\n","UVM_INFO @ 202970852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_sec_cm","qual_name":"3.clkmgr_sec_cm.39148450995546573208887142115513188695754976645359977747016476552429332327008","seed":39148450995546573208887142115513188695754976645359977747016476552429332327008,"line":91,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_sec_cm/latest/run.log","log_context":["UVM_ERROR @  35709981 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire\n","UVM_INFO @  35709981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (alert_receiver_driver.sv:218) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q":[{"name":"clkmgr_sec_cm","qual_name":"2.clkmgr_sec_cm.115169677303459794717034680219789484049707477765842629300574926356078494526432","seed":115169677303459794717034680219789484049707477765842629300574926356078494526432,"line":109,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_sec_cm/latest/run.log","log_context":["UVM_FATAL @ 746835498 ps: (alert_receiver_driver.sv:218) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q \n","UVM_INFO @ 746835498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en":[{"name":"clkmgr_regwen","qual_name":"3.clkmgr_regwen.14945509649591084275733755618765927844066456828130683122861602472796838458215","seed":14945509649591084275733755618765927844066456828130683122861602472796838458215,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6838859 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   6838859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"5.clkmgr_regwen.104660260762671597005865987649883113224791893561026424096144613074841752990631","seed":104660260762671597005865987649883113224791893561026424096144613074841752990631,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2793794 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2793794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"7.clkmgr_regwen.51954727608930448514707264623076318190420844845870505694909426878410358285171","seed":51954727608930448514707264623076318190420844845870505694909426878410358285171,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   1947059 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 8 [0x8]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   1947059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"8.clkmgr_regwen.89532800971246214248592635164788623354496754457513424163364706150149754781332","seed":89532800971246214248592635164788623354496754457513424163364706150149754781332,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2571017 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2571017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"9.clkmgr_regwen.53827025901108792764380148199698019386627343636334629355620878317175368579638","seed":53827025901108792764380148199698019386627343636334629355620878317175368579638,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2327124 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2327124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"10.clkmgr_regwen.97857323304694630679521764581420263184106211401013628599401807883703033988030","seed":97857323304694630679521764581420263184106211401013628599401807883703033988030,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3326941 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3326941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"11.clkmgr_regwen.56951910537234510879955511564373682689970134613705648419733882872291496932605","seed":56951910537234510879955511564373682689970134613705648419733882872291496932605,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   1090461 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 11 [0xb]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   1090461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"12.clkmgr_regwen.61004166603757511864512601356684011442802253177299214734323798026272522333213","seed":61004166603757511864512601356684011442802253177299214734323798026272522333213,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4127564 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 5 [0x5]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   4127564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"15.clkmgr_regwen.49339210221716530980270399930952019574906211060992875263312395621763324456827","seed":49339210221716530980270399930952019574906211060992875263312395621763324456827,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6605044 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (15 [0xf] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   6605044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"16.clkmgr_regwen.12463637357544049236698662304629773947437310535992994127720986844327485283637","seed":12463637357544049236698662304629773947437310535992994127720986844327485283637,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3960630 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3960630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"19.clkmgr_regwen.25912603865349669482919398193878535919141796305257413153678194307240738918558","seed":25912603865349669482919398193878535919141796305257413153678194307240738918558,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3881047 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 7 [0x7]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3881047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"20.clkmgr_regwen.98573078521487139021553928857862491748668298392305694106344546116117006948805","seed":98573078521487139021553928857862491748668298392305694106344546116117006948805,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2892523 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 14 [0xe]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2892523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"21.clkmgr_regwen.77011538244894178742154716879083139174804003704476503791587914361068787991093","seed":77011538244894178742154716879083139174804003704476503791587914361068787991093,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4241996 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   4241996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"23.clkmgr_regwen.96234259037142394667192068232441449517914711150704947471335909059175309469117","seed":96234259037142394667192068232441449517914711150704947471335909059175309469117,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2472967 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2472967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"25.clkmgr_regwen.6859254081667271219293275959999670621316977268682741417517779514995305373724","seed":6859254081667271219293275959999670621316977268682741417517779514995305373724,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/25.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6310223 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (14 [0xe] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   6310223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"26.clkmgr_regwen.49504112660955139385137169151858474537112596543135265494793305545877793566069","seed":49504112660955139385137169151858474537112596543135265494793305545877793566069,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/26.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  11196844 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @  11196844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"27.clkmgr_regwen.112511330922837272241363201612993871216040482521070058405871360912789873585281","seed":112511330922837272241363201612993871216040482521070058405871360912789873585281,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/27.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3838336 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 7 [0x7]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3838336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"30.clkmgr_regwen.71912563242695108516133301536399355549833465279806497075348133623300191038411","seed":71912563242695108516133301536399355549833465279806497075348133623300191038411,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/30.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3278637 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 1 [0x1]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3278637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"32.clkmgr_regwen.87298862913347011843730511327495168055960017696476141820472620186784876117092","seed":87298862913347011843730511327495168055960017696476141820472620186784876117092,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/32.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4057933 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   4057933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"33.clkmgr_regwen.13277441347778939591243335715698509663077388176507186042798756464346155009763","seed":13277441347778939591243335715698509663077388176507186042798756464346155009763,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/33.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   6838728 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   6838728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"34.clkmgr_regwen.33914731723680375140117214461405350554439352413465226383233824569190774695639","seed":33914731723680375140117214461405350554439352413465226383233824569190774695639,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/34.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   3060156 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 0 [0x0]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   3060156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"36.clkmgr_regwen.82276447617216379813782963744106282293439985663771421967852567133669773833746","seed":82276447617216379813782963744106282293439985663771421967852567133669773833746,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/36.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  20597012 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 11 [0xb]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @  20597012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"39.clkmgr_regwen.79655757651103236348458786880073961894027778752304998120442879283327815635753","seed":79655757651103236348458786880073961894027778752304998120442879283327815635753,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/39.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   8886118 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   8886118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"41.clkmgr_regwen.86694226685566521893322131493537662195096132794775582628780498090486809353209","seed":86694226685566521893322131493537662195096132794775582628780498090486809353209,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/41.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @  12690481 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @  12690481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"42.clkmgr_regwen.35747875521701987765603394230542978301962846704747864497812054928024308646962","seed":35747875521701987765603394230542978301962846704747864497812054928024308646962,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/42.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   5014958 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   5014958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"44.clkmgr_regwen.10336031059043601481056357491448866447012326909508312840392511087637285080199","seed":10336031059043601481056357491448866447012326909508312840392511087637285080199,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/44.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   2134073 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   2134073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"47.clkmgr_regwen.5140496647130331405949919785823491090896435452411980043014051463901509662263","seed":5140496647130331405949919785823491090896435452411980043014051463901509662263,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/47.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   7026603 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   7026603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_regwen","qual_name":"49.clkmgr_regwen.30213327979339684366993006236145532728459384383006261699191517933559820445125","seed":30213327979339684366993006236145532728459384383006261699191517933559820445125,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/49.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4237152 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (7 [0x7] vs 9 [0x9]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   4237152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *":[{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"0.clkmgr_shadow_reg_errors_with_csr_rw.8996045505586072006610262071016019512698393831298354149825663109092072442642","seed":8996045505586072006610262071016019512698393831298354149825663109092072442642,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3239366 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   3239366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"0.clkmgr_tl_intg_err.95192344952906614711287634209926040083737239905624568293386933054501807805934","seed":95192344952906614711287634209926040083737239905624568293386933054501807805934,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   6466627 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   6466627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"1.clkmgr_shadow_reg_errors_with_csr_rw.15905462245957955697513383931494186494414640208983799977243116554819543656331","seed":15905462245957955697513383931494186494414640208983799977243116554819543656331,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  54941964 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  54941964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_aliasing","qual_name":"1.clkmgr_csr_aliasing.52153254097864236472138689740365143253334437335372564484652001740981013649739","seed":52153254097864236472138689740365143253334437335372564484652001740981013649739,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_csr_aliasing/latest/run.log","log_context":["UVM_ERROR @  34738834 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  34738834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"2.clkmgr_tl_intg_err.18225723809883965711390975715703459935623900223140811676888923266951181675309","seed":18225723809883965711390975715703459935623900223140811676888923266951181675309,"line":97,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  15449258 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  15449258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_aliasing","qual_name":"2.clkmgr_csr_aliasing.45557739985644543433017863942712825883513024169278876478409822842456934023530","seed":45557739985644543433017863942712825883513024169278876478409822842456934023530,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_csr_aliasing/latest/run.log","log_context":["UVM_ERROR @  11130847 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  11130847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"3.clkmgr_csr_rw.66130680600146330130444808353780801195347759129650898875576954643952270208819","seed":66130680600146330130444808353780801195347759129650898875576954643952270208819,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   4649606 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   4649606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_aliasing","qual_name":"3.clkmgr_csr_aliasing.76392387609166855710792611537704421456246486337071750287721118894230747110272","seed":76392387609166855710792611537704421456246486337071750287721118894230747110272,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_csr_aliasing/latest/run.log","log_context":["UVM_ERROR @  35263508 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  35263508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"3.clkmgr_csr_mem_rw_with_rand_reset.64935331146188998236609152467215765185977334677761940206968531120195395035780","seed":64935331146188998236609152467215765185977334677761940206968531120195395035780,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   1748732 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   1748732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"5.clkmgr_shadow_reg_errors_with_csr_rw.114608227421603702891129501688096160379209293379932515104612593200119850233686","seed":114608227421603702891129501688096160379209293379932515104612593200119850233686,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3733860 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   3733860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"6.clkmgr_shadow_reg_errors_with_csr_rw.9452209930380783626201174172680631789539746979458472912933101495085164004525","seed":9452209930380783626201174172680631789539746979458472912933101495085164004525,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2093121 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   2093121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"6.clkmgr_tl_intg_err.80485580986797673663004345584857140823822206007500725821214027219796814835352","seed":80485580986797673663004345584857140823822206007500725821214027219796814835352,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   4739551 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   4739551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"6.clkmgr_csr_rw.28230647919153460146484674800192795613655014453714787181996442411703181823785","seed":28230647919153460146484674800192795613655014453714787181996442411703181823785,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3627993 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   3627993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"7.clkmgr_tl_intg_err.76139128024870509309412826678901531628680014064356873168386800771202961866529","seed":76139128024870509309412826678901531628680014064356873168386800771202961866529,"line":113,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  29341725 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  29341725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"7.clkmgr_csr_mem_rw_with_rand_reset.54862046552684726838184179999859157091024615895244079388811738776795209080331","seed":54862046552684726838184179999859157091024615895244079388811738776795209080331,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  36436789 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  36436789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"9.clkmgr_tl_intg_err.71993957051345999657829220857419328394698649319400627937077513532481912688762","seed":71993957051345999657829220857419328394698649319400627937077513532481912688762,"line":109,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  29991378 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  29991378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"9.clkmgr_csr_mem_rw_with_rand_reset.76199028673284353798821319650346351509417985248677165037932173275397506738973","seed":76199028673284353798821319650346351509417985248677165037932173275397506738973,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 131965726 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @ 131965726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"10.clkmgr_shadow_reg_errors_with_csr_rw.91218089730557382203896723772720781240009419288081034212196691829967686723436","seed":91218089730557382203896723772720781240009419288081034212196691829967686723436,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2074559 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   2074559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"10.clkmgr_tl_intg_err.45049845705360844874342112837761922680454460894714249413861167926076012449452","seed":45049845705360844874342112837761922680454460894714249413861167926076012449452,"line":86,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   5648345 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   5648345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"11.clkmgr_shadow_reg_errors_with_csr_rw.51840665484720390779858497383898896249406877478781065249458157779890047545494","seed":51840665484720390779858497383898896249406877478781065249458157779890047545494,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  27220167 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  27220167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"12.clkmgr_shadow_reg_errors_with_csr_rw.37454461434244277414779225658769170259403744776177581853949365956903839605365","seed":37454461434244277414779225658769170259403744776177581853949365956903839605365,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  27846587 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  27846587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"12.clkmgr_tl_intg_err.13320236546114906926233639948419387458678644617192052524350984780139558330471","seed":13320236546114906926233639948419387458678644617192052524350984780139558330471,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   2571176 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   2571176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"13.clkmgr_tl_intg_err.20661245793271852797170432244854169673662420493943579743790453303362835889809","seed":20661245793271852797170432244854169673662420493943579743790453303362835889809,"line":90,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  21115481 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  21115481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"13.clkmgr_csr_rw.90273004558553448517333746949022504839495972439309568144555427205585245962704","seed":90273004558553448517333746949022504839495972439309568144555427205585245962704,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2012629 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   2012629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"13.clkmgr_csr_mem_rw_with_rand_reset.56916062761422577800811301977378872656535772838414222378147179477600605692976","seed":56916062761422577800811301977378872656535772838414222378147179477600605692976,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  10669295 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  10669295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"15.clkmgr_tl_intg_err.85793652972315085112532537180117811823501717451243558802775255408338346646358","seed":85793652972315085112532537180117811823501717451243558802775255408338346646358,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   2014472 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   2014472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"15.clkmgr_csr_rw.36900821849783005461389995115865743589102345301134718431999002593663192666501","seed":36900821849783005461389995115865743589102345301134718431999002593663192666501,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @  19547875 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  19547875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"16.clkmgr_shadow_reg_errors_with_csr_rw.75672044505027812041062666529026387193835820261441643824355216728853074152640","seed":75672044505027812041062666529026387193835820261441643824355216728853074152640,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   9906721 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   9906721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"18.clkmgr_tl_intg_err.60101439206970724217869649452661480561288726036845450988430374135540726811345","seed":60101439206970724217869649452661480561288726036845450988430374135540726811345,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   3280587 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   3280587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"18.clkmgr_csr_mem_rw_with_rand_reset.73946931192045480866528657719454813838513582039953769566252394834098096015129","seed":73946931192045480866528657719454813838513582039953769566252394834098096015129,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  22145880 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @  22145880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"19.clkmgr_shadow_reg_errors_with_csr_rw.44801505108316546059852609486231193488891913872315350698666163572190481841259","seed":44801505108316546059852609486231193488891913872315350698666163572190481841259,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3313612 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 \n","UVM_INFO @   3313612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *":[{"name":"clkmgr_csr_bit_bash","qual_name":"0.clkmgr_csr_bit_bash.71337616148988025648536376435548233327090960123781612731830375796648132602007","seed":71337616148988025648536376435548233327090960123781612731830375796648132602007,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @ 157923530 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @ 157923530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_bit_bash","qual_name":"1.clkmgr_csr_bit_bash.9627958862446869736125088285960278095428529150299699917575258111850091266191","seed":9627958862446869736125088285960278095428529150299699917575258111850091266191,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @ 399641817 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @ 399641817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_bit_bash","qual_name":"2.clkmgr_csr_bit_bash.51242001072912571188814868913803246287322084750450451273044758283897610217256","seed":51242001072912571188814868913803246287322084750450451273044758283897610217256,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @  18824084 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @  18824084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_bit_bash","qual_name":"3.clkmgr_csr_bit_bash.23574313219727032233534009742036028655373583171828809116265247497380595674500","seed":23574313219727032233534009742036028655373583171828809116265247497380595674500,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @ 199466085 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @ 199466085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_bit_bash","qual_name":"4.clkmgr_csr_bit_bash.24509325638560152914802371027372499378535362871193808934203019145572647807718","seed":24509325638560152914802371027372499378535362871193808934203019145572647807718,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @  50662571 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @  50662571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch":[{"name":"clkmgr_same_csr_outstanding","qual_name":"0.clkmgr_same_csr_outstanding.5185003942714228592210254309320990323087528241739047189982175756721499163814","seed":5185003942714228592210254309320990323087528241739047189982175756721499163814,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   7584087 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x96213ee4 read out mismatch\n","UVM_INFO @   7584087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"1.clkmgr_same_csr_outstanding.61292924793127322741852632413689468239211978792522829933931844823185015591038","seed":61292924793127322741852632413689468239211978792522829933931844823185015591038,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   4506357 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x35284a24 read out mismatch\n","UVM_INFO @   4506357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"2.clkmgr_same_csr_outstanding.114046900798786412391229947074534208674192090004793582608570455439146293741337","seed":114046900798786412391229947074534208674192090004793582608570455439146293741337,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  17623841 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x225b0de4 read out mismatch\n","UVM_INFO @  17623841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"3.clkmgr_same_csr_outstanding.4447636389478037533678626067800535950567667202975472955556522410302106074218","seed":4447636389478037533678626067800535950567667202975472955556522410302106074218,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   1551566 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xe4119164 read out mismatch\n","UVM_INFO @   1551566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"5.clkmgr_same_csr_outstanding.19874972150333828034067521271106983774017329701093532657938460272623658852897","seed":19874972150333828034067521271106983774017329701093532657938460272623658852897,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  30837040 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xe3637e64 read out mismatch\n","UVM_INFO @  30837040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"6.clkmgr_same_csr_outstanding.31861156969846369839977497658164063392152604183552337129314068396190463669703","seed":31861156969846369839977497658164063392152604183552337129314068396190463669703,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   9908479 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xa461a364 read out mismatch\n","UVM_INFO @   9908479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"7.clkmgr_same_csr_outstanding.103368384740200292273533307147985833117392491174214962260476388505748006034543","seed":103368384740200292273533307147985833117392491174214962260476388505748006034543,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  10222588 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x40fbe8e4 read out mismatch\n","UVM_INFO @  10222588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"8.clkmgr_same_csr_outstanding.4476598339552852430736868762787355175743514051209971237679142830031296684375","seed":4476598339552852430736868762787355175743514051209971237679142830031296684375,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   4635401 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xe23cd2a4 read out mismatch\n","UVM_INFO @   4635401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"9.clkmgr_same_csr_outstanding.69313136227676716464425306186577684323157716087792237160327071794320230436076","seed":69313136227676716464425306186577684323157716087792237160327071794320230436076,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   3086930 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xf3a00364 read out mismatch\n","UVM_INFO @   3086930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"10.clkmgr_same_csr_outstanding.67992385326846761103068056707938768729829360090828072420987594885457632170905","seed":67992385326846761103068056707938768729829360090828072420987594885457632170905,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  17667411 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xcf8a90a4 read out mismatch\n","UVM_INFO @  17667411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"11.clkmgr_same_csr_outstanding.840418038010407912772591295101392581463451513572711429018095140695319931548","seed":840418038010407912772591295101392581463451513572711429018095140695319931548,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   3796705 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x46aab4a4 read out mismatch\n","UVM_INFO @   3796705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"12.clkmgr_same_csr_outstanding.100816204540791637027173085541881507116321332380393665310692434788758098526","seed":100816204540791637027173085541881507116321332380393665310692434788758098526,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  13756257 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x88e50964 read out mismatch\n","UVM_INFO @  13756257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"13.clkmgr_same_csr_outstanding.68657443926006135124473115508401695866841518158560020616976788442672256064758","seed":68657443926006135124473115508401695866841518158560020616976788442672256064758,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   3978282 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x6c00f364 read out mismatch\n","UVM_INFO @   3978282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"14.clkmgr_same_csr_outstanding.43332304150178855675972088038161691756004167692740815374320020807311978821223","seed":43332304150178855675972088038161691756004167692740815374320020807311978821223,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   3638525 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x150f9da4 read out mismatch\n","UVM_INFO @   3638525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"15.clkmgr_same_csr_outstanding.44487364632248361615879425672306481675888167996520995401512064051604456851967","seed":44487364632248361615879425672306481675888167996520995401512064051604456851967,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  39135227 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x35746ea4 read out mismatch\n","UVM_INFO @  39135227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"16.clkmgr_same_csr_outstanding.67687901836379350789251517277520409639377631287019482248969574834042180606023","seed":67687901836379350789251517277520409639377631287019482248969574834042180606023,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   4507753 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xa99cace4 read out mismatch\n","UVM_INFO @   4507753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"17.clkmgr_same_csr_outstanding.110585993600360547450866935588655282816225399263024424302210403654653278565542","seed":110585993600360547450866935588655282816225399263024424302210403654653278565542,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  23562787 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xd6a176e4 read out mismatch\n","UVM_INFO @  23562787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"18.clkmgr_same_csr_outstanding.80084200455427559720530680772621530432310445094179204078764095815213107496431","seed":80084200455427559720530680772621530432310445094179204078764095815213107496431,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  27741416 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x159f5824 read out mismatch\n","UVM_INFO @  27741416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_same_csr_outstanding","qual_name":"19.clkmgr_same_csr_outstanding.102830634450650731228991263793126300866726826224039951223024903404419237612930","seed":102830634450650731228991263793126300866726826224039951223024903404419237612930,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @  13295351 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xd44a2de4 read out mismatch\n","UVM_INFO @  13295351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: *":[{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"0.clkmgr_csr_mem_rw_with_rand_reset.73648786502102299432827920708222066520839066841711149239747368820992956786941","seed":73648786502102299432827920708222066520839066841711149239747368820992956786941,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   7963668 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   7963668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"1.clkmgr_tl_intg_err.28649140429769422643560157610159868353508636225541420907794213521891141010979","seed":28649140429769422643560157610159868353508636225541420907794213521891141010979,"line":86,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  10418766 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  10418766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"2.clkmgr_shadow_reg_errors_with_csr_rw.115044609364881110917522993021449374533830015843414508795829096496806014793477","seed":115044609364881110917522993021449374533830015843414508795829096496806014793477,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2343952 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2343952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"3.clkmgr_shadow_reg_errors_with_csr_rw.106958148003079215312328460049338687612223203504071703633604018300816144044032","seed":106958148003079215312328460049338687612223203504071703633604018300816144044032,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  29351114 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  29351114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"3.clkmgr_tl_intg_err.84118108401837065296063123768267014456693042349159452278795084677321501548305","seed":84118108401837065296063123768267014456693042349159452278795084677321501548305,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   2381407 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2381407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"4.clkmgr_shadow_reg_errors_with_csr_rw.104303135828624753898251266886498367775018174414705723654012824296606313824750","seed":104303135828624753898251266886498367775018174414705723654012824296606313824750,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  22389075 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  22389075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"4.clkmgr_tl_intg_err.16529130461304954352269600614727075128775300045075627094919991250341623848289","seed":16529130461304954352269600614727075128775300045075627094919991250341623848289,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   3109192 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   3109192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"4.clkmgr_csr_mem_rw_with_rand_reset.16638661692596363729154944738524416438792955075678827741932108905985320991478","seed":16638661692596363729154944738524416438792955075678827741932108905985320991478,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   4381619 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   4381619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"5.clkmgr_tl_intg_err.9672047069760538253720220506130447185166375468576296841212869068664117669528","seed":9672047069760538253720220506130447185166375468576296841212869068664117669528,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  10231258 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  10231258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"5.clkmgr_csr_rw.51957986156761078309210316257214459790021173870060877477891304134434642540820","seed":51957986156761078309210316257214459790021173870060877477891304134434642540820,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3722506 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   3722506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"7.clkmgr_shadow_reg_errors_with_csr_rw.47195674968980756211086557625449385902204465438497511835189289722421737926900","seed":47195674968980756211086557625449385902204465438497511835189289722421737926900,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   6174307 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   6174307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"8.clkmgr_shadow_reg_errors_with_csr_rw.89255262248840224901312419065154750954658078470645869998046127703781292336094","seed":89255262248840224901312419065154750954658078470645869998046127703781292336094,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  12480085 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  12480085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"8.clkmgr_tl_intg_err.44276109913300299318195504162272357818282430071514317726174953570994356636089","seed":44276109913300299318195504162272357818282430071514317726174953570994356636089,"line":132,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  91657577 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  91657577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"9.clkmgr_shadow_reg_errors_with_csr_rw.91394152533358544903778294723375207906279394529521376097893461750925894444789","seed":91394152533358544903778294723375207906279394529521376097893461750925894444789,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   9970773 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   9970773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"9.clkmgr_csr_rw.91254464714471247813460883981248043890451802811636081041675661738573036698738","seed":91254464714471247813460883981248043890451802811636081041675661738573036698738,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2931462 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2931462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"10.clkmgr_csr_rw.32549406941431704962416361445654699081319278442807617412647003036255063268217","seed":32549406941431704962416361445654699081319278442807617412647003036255063268217,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   9440215 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   9440215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"11.clkmgr_tl_intg_err.77147692539244870571622049977762094912723379707819966603036678835449209599663","seed":77147692539244870571622049977762094912723379707819966603036678835449209599663,"line":96,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  16559517 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  16559517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"11.clkmgr_csr_mem_rw_with_rand_reset.79862341548209741884483749343506211517770040767878911441310911784572705439653","seed":79862341548209741884483749343506211517770040767878911441310911784572705439653,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  43987499 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  43987499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"12.clkmgr_csr_rw.110194385502557075465487486806890465901290181200256713558222607012752951740381","seed":110194385502557075465487486806890465901290181200256713558222607012752951740381,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   5391444 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   5391444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"13.clkmgr_shadow_reg_errors_with_csr_rw.113580665077886666213586796416702192548034107197765279559473020168859083649810","seed":113580665077886666213586796416702192548034107197765279559473020168859083649810,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  12626404 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  12626404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"14.clkmgr_shadow_reg_errors_with_csr_rw.100360915910143643854304242854452875485977026242964044180634702546493610357283","seed":100360915910143643854304242854452875485977026242964044180634702546493610357283,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   3499806 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   3499806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"14.clkmgr_tl_intg_err.69593973115550477280377957336079237690711923320350969355989867604724848922378","seed":69593973115550477280377957336079237690711923320350969355989867604724848922378,"line":89,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  10674461 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  10674461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"14.clkmgr_csr_mem_rw_with_rand_reset.39713667104678485442385134803203949640812379141781449182067866168431886941357","seed":39713667104678485442385134803203949640812379141781449182067866168431886941357,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   4947767 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   4947767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"15.clkmgr_shadow_reg_errors_with_csr_rw.12184834650378123044274038221065024110863587371703001548186275765067548599369","seed":12184834650378123044274038221065024110863587371703001548186275765067548599369,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2359707 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2359707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"15.clkmgr_csr_mem_rw_with_rand_reset.85288706225380858174689173642189381708826498817208398974239522800021445172409","seed":85288706225380858174689173642189381708826498817208398974239522800021445172409,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  20217147 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  20217147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"16.clkmgr_tl_intg_err.8449229851750050044761404289163285063836382890580892374927100389667636411893","seed":8449229851750050044761404289163285063836382890580892374927100389667636411893,"line":124,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @  92054397 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  92054397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"16.clkmgr_csr_mem_rw_with_rand_reset.84619817941652015576311240529419328673052196405775435754087868282659586116060","seed":84619817941652015576311240529419328673052196405775435754087868282659586116060,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  13829259 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  13829259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"17.clkmgr_shadow_reg_errors_with_csr_rw.31832600047048635612730019290575617814698007165199639722205687341110777218651","seed":31832600047048635612730019290575617814698007165199639722205687341110777218651,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   5292524 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   5292524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"17.clkmgr_tl_intg_err.76992397334006493438858990839530495049093614563126128046715957219201708555314","seed":76992397334006493438858990839530495049093614563126128046715957219201708555314,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   2062869 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2062869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"18.clkmgr_shadow_reg_errors_with_csr_rw.10650510322291614610520604517358803976165119580615784322782778792871077729768","seed":10650510322291614610520604517358803976165119580615784322782778792871077729768,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @   7760369 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   7760369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"18.clkmgr_csr_rw.68010068444288700859385987111616815744242887218714364444974252599745818698783","seed":68010068444288700859385987111616815744242887218714364444974252599745818698783,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   2322729 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   2322729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"19.clkmgr_tl_intg_err.43089353318418769670171028822084131333517245671667087529836212059335401057104","seed":43089353318418769670171028822084131333517245671667087529836212059335401057104,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   3716569 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   3716569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"19.clkmgr_csr_mem_rw_with_rand_reset.2268831789110657013338943358699919411470993870002274103587316795777494195360","seed":2268831789110657013338943358699919411470993870002274103587316795777494195360,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   9172311 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   9172311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":374,"total":710,"percent":52.67605633802817}